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lorom256k.cfg
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lorom256k.cfg
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# ca65 linker config for 256 KiB (2 Mbit) sfc file
# Physical areas of memory
MEMORY {
# I usually reserve $000000-$00000F for local variables
# allocated just below the .proc statement of a subroutine.
# The rest is open for global variables.
ZEROPAGE: start = $000010, size = $00F0;
# Make sure to change BSS based on where you put
# the stack and how big you expect it to get.
# Unlike on the NES, we include shadow OAM in BSS here
# because there's not as much of a benefit to having it
# page-aligned.
BSS: start = $000200, size = $1E00;
BSS7E: start = $7E2000, size = $E000;
BSS7F: start = $7F0000, size =$10000;
# The fast ROM area starts at $808000.
# It's mirrored into the slow ROM area.
ROM0: start = $808000, size = $8000, type = ro, file = %O, fill=yes, fillval=$FF;
ROM1: start = $818000, size = $8000, type = ro, file = %O, fill=yes, fillval=$FF;
ROM2: start = $828000, size = $8000, type = ro, file = %O, fill=yes, fillval=$FF;
ROM3: start = $838000, size = $8000, type = ro, file = %O, fill=yes, fillval=$FF;
ROM4: start = $848000, size = $8000, type = ro, file = %O, fill=yes, fillval=$FF;
ROM5: start = $858000, size = $8000, type = ro, file = %O, fill=yes, fillval=$FF;
ROM6: start = $868000, size = $8000, type = ro, file = %O, fill=yes, fillval=$FF;
ROM7: start = $878000, size = $8000, type = ro, file = %O, fill=yes, fillval=$FF;
# The sound processor has its own address space
SPCZEROPAGE:start = $0010, size = $00E0;
SPCRAM: start = $0200, size = $FDC0;
}
# Logical areas code/data can be put into.
SEGMENTS {
# Read-only areas for main CPU
CODE: load = ROM0, type = ro, align = $100;
RODATA: load = ROM0, type = ro, align = $100;
SNESHEADER: load = ROM0, type = ro, start = $80FFB0;
CODE1: load = ROM1, type = ro, align = $100, optional=yes;
RODATA1: load = ROM1, type = ro, align = $100, optional=yes;
CODE2: load = ROM2, type = ro, align = $100, optional=yes;
RODATA2: load = ROM2, type = ro, align = $100, optional=yes;
CODE3: load = ROM3, type = ro, align = $100, optional=yes;
RODATA3: load = ROM3, type = ro, align = $100, optional=yes;
CODE4: load = ROM4, type = ro, align = $100, optional=yes;
RODATA4: load = ROM4, type = ro, align = $100, optional=yes;
CODE5: load = ROM5, type = ro, align = $100, optional=yes;
RODATA5: load = ROM5, type = ro, align = $100, optional=yes;
CODE6: load = ROM6, type = ro, align = $100, optional=yes;
RODATA6: load = ROM6, type = ro, align = $100, optional=yes;
CODE7: load = ROM7, type = ro, align = $100, optional=yes;
RODATA7: load = ROM7, type = ro, align = $100, optional=yes;
# Read-only areas for sound CPU
SPCIMAGE: load = ROM7, run=SPCRAM, align = $100, define=yes;
# Areas for variables for main CPU
ZEROPAGE: load = ZEROPAGE, type = zp, define=yes;
BSS: load = BSS, type = bss, align = $100, optional=yes;
BSS7E: load = BSS7E, type = bss, align = $100, optional=yes;
BSS7F: load = BSS7F, type = bss, align = $100, optional=yes;
# Areas for variables for sound CPU
SPCZEROPAGE:load = SPCZEROPAGE, type=zp, optional=yes;
SPCBSS: load = SPCRAM, type = bss, align = $100, optional=yes;
}