From 6c83b898b21d9f7bc7276f2f329656b19f3afed6 Mon Sep 17 00:00:00 2001 From: SamuelmsWong <45978186+SamuelmsWong@users.noreply.github.com> Date: Sat, 18 Jan 2020 12:09:20 +0000 Subject: [PATCH 1/5] Changed R4 format excecution to use bit masking Within function riscvstep() --- sim/pipeline-riscv.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/sim/pipeline-riscv.c b/sim/pipeline-riscv.c index fdeafd6b..9d50a557 100644 --- a/sim/pipeline-riscv.c +++ b/sim/pipeline-riscv.c @@ -638,13 +638,15 @@ riscvstep(Engine *E, State *S, int drain_pipeline) S->riscv->instruction_distribution[S->riscv->P.EX.op]++; break; } - case INSTR_R4: { - instr_r4 *tmp; - - tmp = (instr_r4 *)&S->riscv->P.EX.instr; - (*(S->riscv->P.EX.fptr))(E, S, tmp->rs1, tmp->rs2, tmp->rs3, tmp->rm, tmp->rd); + uint32_t tmp = S->riscv->P.EX.instr; + (*(S->riscv->P.EX.fptr))(E, S, + (tmp&maskExtractBits15to19) >> 15, + (tmp&maskExtractBits20to24) >> 20, + (tmp&maskExtractBits27to31) >> 27, + (tmp&maskExtractBits12to14) >> 12, + (tmp&maskExtractBits7to11) >> 7); break; } @@ -750,7 +752,6 @@ riscvstep(Engine *E, State *S, int drain_pipeline) (tmp&maskExtractBit20) >> 20, (tmp&maskExtractBits12to19) >> 12, (tmp&maskExtractBit31) >> 31); - S->riscv->instruction_distribution[S->riscv->P.ID.op]++; } else { @@ -762,8 +763,8 @@ riscvstep(Engine *E, State *S, int drain_pipeline) (tmp&maskExtractBits25to30) >> 25, (tmp&maskExtractBit7) >> 7, (tmp&maskExtractBit31) >> 31); - S->riscv->instruction_distribution[S->riscv->P.ID.op]++; } + S->riscv->instruction_distribution[S->riscv->P.ID.op]++; S->dyncnt++; riscvIFflush(S); } From ee80d51d05ab54b57e36d36b559fd86d0c0c5936 Mon Sep 17 00:00:00 2001 From: SamuelmsWong <45978186+SamuelmsWong@users.noreply.github.com> Date: Sat, 18 Jan 2020 12:10:42 +0000 Subject: [PATCH 2/5] Added 2 bit masks --- sim/bit.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/sim/bit.h b/sim/bit.h index 5fc0a3f6..81bf23b3 100755 --- a/sim/bit.h +++ b/sim/bit.h @@ -134,6 +134,7 @@ enum maskExtractBit7 = 0x1 << 7, maskExtractBits7to11 = 0x1F << 7, maskExtractBits8to11 = 0xF << 8, + maskExtractBits12to14 = 0x7 << 12, maskExtractBits12to19 = 0xFF << 12, maskExtractBits12to31 = 0xFFFFF << 12, maskExtractBits15to19 = 0x1F << 15, @@ -141,8 +142,10 @@ enum maskExtractBits20to24 = 0x1F << 20, maskExtractBits20to31 = 0xFFF << 20, maskExtractBits21to30 = 0x7FE << 20, + maskExtractBits25to26 = 0x3 << 25, maskExtractBits25to30 = 0x3F << 25, maskExtractBits25to31 = 0x7F << 25, + maskExtractBits27to31 = 0x1F << 27, maskExtractBit31 = 0x1 << 31, }; From 9460320b20a4db8080abe16b589a93ccd5c72dfc Mon Sep 17 00:00:00 2001 From: SamuelmsWong <45978186+SamuelmsWong@users.noreply.github.com> Date: Sat, 18 Jan 2020 12:12:37 +0000 Subject: [PATCH 3/5] Spacing edit --- sim/pipeline-riscv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sim/pipeline-riscv.c b/sim/pipeline-riscv.c index 9d50a557..d58ed10e 100644 --- a/sim/pipeline-riscv.c +++ b/sim/pipeline-riscv.c @@ -638,6 +638,7 @@ riscvstep(Engine *E, State *S, int drain_pipeline) S->riscv->instruction_distribution[S->riscv->P.EX.op]++; break; } + case INSTR_R4: { uint32_t tmp = S->riscv->P.EX.instr; From a5dfd696c21ae8401e74d69311d6505a86c9238b Mon Sep 17 00:00:00 2001 From: SamuelmsWong <45978186+SamuelmsWong@users.noreply.github.com> Date: Sat, 18 Jan 2020 12:20:23 +0000 Subject: [PATCH 4/5] Comment change, removed distribution increment --- sim/pipeline-riscv.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/sim/pipeline-riscv.c b/sim/pipeline-riscv.c index d58ed10e..a3339b00 100644 --- a/sim/pipeline-riscv.c +++ b/sim/pipeline-riscv.c @@ -95,7 +95,7 @@ Assumed pipeline implementation: 1 stall: LOAD instrs that write to a reg-required-by-next-instr after reading from mem: ...EX of next instr needs reg data from MA of LOAD instrs. - BRANCH instrs test for (in)equality in ID, dependent on previous instr: + BRANCH instrs test for (in)equality in ID which is dependent on previous instr: ...ID of BRANCH instr needs reg data from EX of previous instr. 2 stalls: LOAD instr followed by dependent BRANCH instr: @@ -634,8 +634,11 @@ riscvstep(Engine *E, State *S, int drain_pipeline) (tmp&maskExtractBit20) >> 20, (tmp&maskExtractBits12to19) >> 12, (tmp&maskExtractBit31) >> 31); - S->dyncnt++; */ + S->dyncnt++; + S->riscv->instruction_distribution[S->riscv->P.EX.op]++; + */ + break; } From 430762b2bdab99a86781f1911874082e5d7a9e24 Mon Sep 17 00:00:00 2001 From: SamuelmsWong <45978186+SamuelmsWong@users.noreply.github.com> Date: Sat, 18 Jan 2020 12:25:17 +0000 Subject: [PATCH 5/5] Spacing change --- sim/pipeline-riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/pipeline-riscv.c b/sim/pipeline-riscv.c index a3339b00..6f1db037 100644 --- a/sim/pipeline-riscv.c +++ b/sim/pipeline-riscv.c @@ -641,7 +641,7 @@ riscvstep(Engine *E, State *S, int drain_pipeline) break; } - + case INSTR_R4: { uint32_t tmp = S->riscv->P.EX.instr;