diff --git a/sim/Makefile b/sim/Makefile index bc990103..7fe32667 100755 --- a/sim/Makefile +++ b/sim/Makefile @@ -72,6 +72,7 @@ OBJS =\ uncertain_upe.o\ main.o\ merror.o\ + memory-hierarchy-riscv.o\ mmalloc.o\ mmu-hitachi-sh.o\ network-hitachi-sh.o\ @@ -120,7 +121,7 @@ op-ti-msp430.o: op-ti-msp430.c $(HEADERS) Makefile ## $(LINT) $(CCFLAGS) $(INCLUDEDIRS) op-ti-msp430.c $(CC) $(CCFLAGS) $(WFLAGS) $(INCLUDEDIRS) $(DBGFLAGS) $(OPTFLAGS) -c op-ti-msp430.c -o $@ -op-riscv.o: op-riscv.c memory-hierarchy.c regaccess-riscv.c $(HEADERS) Makefile +op-riscv.o: op-riscv.c memory-hierarchy.c memory-hierarchy-riscv.c regaccess-riscv.c $(HEADERS) Makefile ## $(LINT) $(CCFLAGS) $(INCLUDEDIRS) op-hitachi-sh.c $(CC) $(CCFLAGS) $(WFLAGS) $(INCLUDEDIRS) $(DBGFLAGS) $(OPTFLAGS) -c op-riscv.c -o $@ diff --git a/sim/machine-riscv.c b/sim/machine-riscv.c index b1b8521d..a766566c 100644 --- a/sim/machine-riscv.c +++ b/sim/machine-riscv.c @@ -128,7 +128,7 @@ riscvstallaction(Engine *E, State *S, ulong addr, int type, int latency) /* the stall actually occurs when in MA, since we've */ /* completed the EX wait before we get executed. */ /* */ - if (S->superH->mem_access_type == MEM_ACCESS_IFETCH) + if (S->riscv->mem_access_type == MEM_ACCESS_IFETCH) { /* I don't know why Philip used fetch_stall_cycles, and not */ /* IF.cycles (he doesn't remember either) but I'll leave it as it is... */ @@ -428,7 +428,8 @@ riscvexpectedvaluehist(Engine *E, State *S, int histogram_id0, int output_reg) * DistLess returns the probability Pr(X < Rs2) */ void -riscvdistlesshist(Engine *E, State *S, int histogram_id0, int Rs2, int output_reg){ +riscvdistlesshist(Engine *E, State *S, int histogram_id0, int Rs2, int output_reg) +{ int result = Histogram_DistLess( E, S, @@ -446,7 +447,8 @@ riscvdistlesshist(Engine *E, State *S, int histogram_id0, int Rs2, int output_re * DistGrt returns the probability Pr(X >= Rs2) */ void -riscvdistgrthist(Engine *E, State *S, int histogram_id0, int Rs2, int output_reg){ +riscvdistgrthist(Engine *E, State *S, int histogram_id0, int Rs2, int output_reg) +{ int result = Histogram_DistGrt( E, S, @@ -470,30 +472,243 @@ uncertainnewstate(Engine *E, char *ID) mexit(E, "Failed to allocate memory uncertain state.", -1); } - for (i = 0; i < 32; ++i) { + for (i = 0; i < 32; ++i) + { uncertain_inst_sv(S, i, nan("")); } return S; } +void +riscVresetcpu(Engine *E, State *S) +{ + int i; + + + riscvflushpipe(S); + + + S->MEMSIZE = DEFLT_MEMSIZE; + S->MEMBASE = SUPERH_MEMBASE; + S->MEMEND = S->MEMBASE + S->MEMSIZE; + + S->mem_r_latency = DEFAULT_MEMREAD_LATENCY; + S->mem_w_latency = DEFAULT_MEMWRITE_LATENCY; + + /* + * Initialisation of shadow memory: + */ + + S->TAINTMEMSIZE = DEFLT_MEMSIZE*sizeof(ShadowMem); + S->TAINTMEMBASE = SUPERH_MEMBASE; + S->TAINTMEMEND = S->TAINTMEMBASE + S->TAINTMEMSIZE; + + + memset(&S->riscv->P, 0, sizeof(SuperHPipe)); + memset(&S->energyinfo, 0, sizeof(EnergyInfo)); + // memset(&S->superH->R, 0, sizeof(ulong)*16); + // memset(&S->superH->R_BANK, 0, sizeof(ulong)*8); + // memset(&S->superH->SR, 0, sizeof(SuperHSREG)); + // memset(&S->superH->SSR, 0, sizeof(SuperHSREG)); + memset(S->MEM, 0, S->MEMSIZE); + if (SF_NUMA) + { + memset(S->riscv->B, 0, sizeof(SuperHBuses)); + } + + /* */ + /* The only the ratio of size:blocksize and assoc are */ + /* significant when Cache struct is used for modeling TLB */ + /* */ + // superHtlb_init(E, S, 128, 1, 4); + + S->PC = SUPERH_MEMBASE; + S->pcstackheight = 0; + S->fpstackheight = 0; + + + S->TIME = E->globaltimepsec; + S->riscv->TIMER_LASTACTIVATE = 0.0; + S->riscv->TIMER_INTR_DELAY = 1E-3; + S->dyncnt = 0; + S->nfetched = 0; + S->CLK = 0; + S->ICLK = 0; + S->cmdbuf_nbytes = 0; + + S->CYCLETIME = SUPERH_ORIG_CYCLE; + S->VDD = SUPERH_ORIG_VDD; + S->SVDD = 0.0; + S->LOWVDD = S->VDD/2.0; + + S->voltscale_alpha = 2.0; + //BUG? + S->voltscale_K = SUPERH_ORIG_VDD * SUPERH_ORIG_CYCLE; + S->voltscale_Vt = 0.0; + + S->Cycletrans = 0; + S->riscv->mem_access_type = 0; + + S->riscv->PTEL = 0; + S->riscv->PTEH = 0; + S->riscv->TTB = 0; + S->riscv->TEA = 0; + S->riscv->MMUCR = 0; + + // S->superH->TRA = 0; + // S->superH->EXPEVT = 0; + // S->superH->INTEVT = 0; + + // S->superH->ICR = 0; + // S->superH->ICRA = 0; + // S->superH->ICRB = 0; + + S->runnable = 0; + S->sleep = 0; + S->ustart = 0; + S->ufinish = 0; + S->startclk = 0; + S->finishclk = 0; + + S->step = riscvstep; + S->pipelined = 1; + S->pipeshow = 0; + + fault_setnodepfun(E, S, "urnd"); + + if (SF_PAU_DEFINED) + { + pau_init(E, S, S->riscv->npau); + mprint(E, S, nodeinfo, + "Done with pauinit, for %d PAU entries...\n", + S->riscv->npau); + } + + /* Since we've reset VDD, need to update this */ + E->mincycpsec = PICOSEC_MAX; + E->maxcycpsec = 0; + for (i = 0; i < E->nnodes; i++) + { + E->mincycpsec = min(E->mincycpsec, E->sp[i]->CYCLETIME); + E->maxcycpsec = max(E->maxcycpsec, E->sp[i]->CYCLETIME); + } + + return; +} + State * riscvnewstate(Engine *E, double xloc, double yloc, double zloc, char *trajfilename) { - State * S = superHnewstate(E, xloc, yloc, zloc, trajfilename); + State *S; + + S = (State *)mcalloc(E, 1, sizeof(State), "(State *)S"); + if (S == NULL) + { + mexit(E, "Failed to allocate memory for State *S.", -1); + } S->riscv = (RiscvState *) mcalloc(E, 1, sizeof(RiscvState), "S->riscv"); if (S->riscv == NULL) + { + mexit(E, "Failed to allocate memory for S->riscv.", -1); + } + +#if (SF_UNCERTAIN_UPE == 1) + S->riscv->uncertain = uncertainnewstate(E, "S->riscv->uncertain"); +#endif + + S->MEM = (uchar *)mcalloc(E, 1, DEFLT_MEMSIZE, "(uchar *)S->MEM"); + if (S->MEM == NULL) + { + mexit(E, "Failed to allocate memory for S->MEM.", -1); + } + + if (SF_TAINTANALYSIS) + { + S->TAINTMEM = (ShadowMem *)mcalloc(E, 1, S->TAINTMEMSIZE, "(ShadowMem *)S->TAINTMEM"); + if (S->TAINTMEM == NULL) { - mexit(E, "Failed to allocate memory for S->riscv.", -1); + mexit(E, "Failed to allocate memory for S->TAINTMEM.", -1); } + } - S->riscv->uncertain = uncertainnewstate(E, "S->riscv->uncertain"); + if (SF_NUMA) + { + S->riscv->B = (SuperHBuses *)mcalloc(E, 1, sizeof(SuperHBuses), "(SuperHBuses *)S->riscv->B"); + if (S->riscv->B == NULL) + { + mexit(E, "Failed to allocate memory for S->riscv->B.", -1); + } + } + + E->cp = S; + E->sp[E->nnodes] = S; + mprint(E, NULL, siminfo, "New node created with node ID %d\n", E->nnodes); + + /* Update the min cycle time */ + E->mincycpsec = PICOSEC_MAX; + E->maxcycpsec = 0; + for (int i = 0; i < E->nnodes; i++) + { + E->mincycpsec = min(E->mincycpsec, E->sp[i]->CYCLETIME); + E->maxcycpsec = max(E->maxcycpsec, E->sp[i]->CYCLETIME); + } + + S->machinetype = MACHINE_RISCV; + /* FIXME superH related functions need to be cleaned up. */ + S->endian = Little; S->dumpregs = riscvdumpregs; - S->dumpsysregs = riscvdumpsysregs; + S->dumpsysregs = riscvdumpsysregs; + S->fatalaction = riscvfatalaction; + S->stallaction = riscvstallaction; + S->settimerintrdelay = superHsettimerintrdelay; + + S->take_nic_intr = superHtake_nic_intr; + S->take_timer_intr = superHtake_timer_intr; + S->take_batt_intr = superHtake_batt_intr; + S->check_batt_intr = superHcheck_batt_intr; + S->check_nic_intr = superHcheck_nic_intr; + + S->cache_init = superHcache_init; + S->resetcpu = riscVresetcpu; + S->step = riscvstep; + S->cyclestep = riscvstep; + S->faststep = riscvfaststep; S->dumppipe = riscvdumppipe; - S->flushpipe = riscvflushpipe; + S->flushpipe = riscvflushpipe; + + /* Most of the device registers are SH7708 specific */ + S->devreadbyte = dev7708readbyte; + S->devreadword = dev7708readword; + S->devreadlong = dev7708readlong; + S->devwritebyte = dev7708writebyte; + S->devwriteword = dev7708writeword; + S->devwritelong = dev7708writelong; + S->split = superHsplit; + S->vmtranslate = riscVvmtranslate; + S->dumptlb = superHdumptlb; + S->cache_deactivate = riscVcache_deactivate; + S->cache_printstats = superHcache_printstats; + + S->writebyte = riscVwritebyte; + + S->xloc = xloc; + S->yloc = yloc; + S->zloc = zloc; + + if (trajfilename != NULL) + { + mexit(E, "S->trajfilename is not supported in SF Risc-V", -1); + } + + S->NODE_ID = E->baseid + E->nnodes; + + /* Must know correct number of nodes in resetcpu() */ + E->nnodes++; + S->resetcpu(E, S); + /* * Histogram-specific menu items @@ -503,14 +718,5 @@ riscvnewstate(Engine *E, double xloc, double yloc, double zloc, char *trajfilena S->ldhistrandom = riscvldhistrandom; S->addhist = riscvaddhist; - S->fatalaction = riscvfatalaction; - S->endian = Little; - S->machinetype = MACHINE_RISCV; - S->dumpdistribution = riscvdumpdistribution; - S->stallaction = riscvstallaction; - - S->step = riscvstep; - S->faststep = riscvfaststep; - return S; } diff --git a/sim/machine-riscv.h b/sim/machine-riscv.h index 583b71f7..ed5292e5 100644 --- a/sim/machine-riscv.h +++ b/sim/machine-riscv.h @@ -55,4 +55,40 @@ typedef struct * Histograms */ Histogram histograms[RISCV_XMAX]; + + /* + * Features borrowed from superH + */ + int cache_activated; + + SuperHBuses *B; + + /* Time of last generated timer intr */ + Picosec TIMER_LASTACTIVATE; + + /* Delay b/n timer interrupts */ + Picosec TIMER_INTR_DELAY; + + /* Power Adaptation Unit */ + PAUentry *PAUs; + int npau; + int influenced; + int controlling_pau; + ulong pauaddrmask; + + Cache *TLB; + + int *PAUvalids; + int numpauvalids; + + /* Whether mem access is in IF or EX */ + int mem_access_type; + + /* MMU stuff */ + ulong PTEH; + ulong PTEL; + ulong TTB; + ulong TEA; + ulong MMUCR; + } RiscvState; diff --git a/sim/memory-hierarchy-riscv.c b/sim/memory-hierarchy-riscv.c new file mode 100755 index 00000000..838a8fc6 --- /dev/null +++ b/sim/memory-hierarchy-riscv.c @@ -0,0 +1,462 @@ +/* + Copyright (c) 2019, Vasileios Tsoutsouras (author) + + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + * Redistributions of source code must retain the above + copyright notice, this list of conditions and the following + disclaimer. + + * Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials + provided with the distribution. + + * Neither the name of the author nor the names of its + contributors may be used to endorse or promote products + derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ +#include "sf.h" +#include "mmu-hitachi-sh.h" + +int +riscVcache_init(Engine *E, State *S, int size, int blocksize, int assoc) +{ + mprint(E, S, nodeinfo, "Cache not currently supported in RiscV simulation\n"); + return 0; +} + +void +riscVcache_deactivate(Engine *E, State *S) +{ + mprint(E, S, nodeinfo, "Cache deactivated\n"); + S->riscv->cache_activated = 0; +} + +void +riscVvmtranslate(Engine *E, State *S, int op, TransAddr *tr) +{ + ulong vaddr = tr->vaddr; + + /* */ + /* First, for MMU_AREA_P4 (priv, ctrl space), no translation */ + /* */ + if ((vaddr >= MMU_AREA_P4_START) && (vaddr <= MMU_AREA_P4_END)) + { + tr->error = 0; + tr->paddr = vaddr; + tr->cacheable = 0; + //fprintf(stderr, "MMU_AREA_P4. Address [0x" UHLONGFMT "] translated to [0x" UHLONGFMT "]...\n", tr->vaddr, tr->paddr); + + return; + } + + /* */ + /* If MMU is disabled, virtual addr is used directly */ + /* as phy addr by ignoring top 3 bits of virtual addr */ + /* See rej09b0146_sh7706.pdf, page 55, para 4. */ + /* */ + if (mmucr_field_at(S->riscv->MMUCR) == 0) + { + tr->error = 0; + tr->paddr = vaddr & ~(B0111 << 29); + tr->cacheable = 1; + + return; + } + else + { + mprint(E, S, nodeinfo, "MMU seems to be enabled in RiscV simulation. However it is not currently supported.\n"); + } +} + +tuck void +riscVwritebyte(Engine *E, State *S, ulong vaddr, ulong xdata) +{ + int inram, latency = 0; + TransAddr trans; + ulong paddr; + uchar data = xdata & 0xFF; + + /* */ + /* Translate address. If error occured, we do nothing: */ + /* faulting instruction will get re-executed after the */ + /* exception is handled. */ + /* */ + trans.vaddr = vaddr; + trans.error = 0; + S->vmtranslate(E, S, MEM_WRITE_BYTE, &trans); + if (trans.error) + { + return; + } + + paddr = trans.paddr; + inram = 0; + + if ((paddr >= S->MEMBASE) && (paddr < S->MEMEND)) + { + inram = 1; + latency = S->mem_w_latency; + } + + if (!inram) + { + /* */ + /* Pass this address off to the devices. */ + /* We perform the necessary bitflip analysis in */ + /* devport. If addr not found in devport, try */ + /* arch-specific dev if not, fail with sfatal. */ + /* */ + devportwritebyte(E, S, vaddr, data); + + return; + } + + if (inram) + { + S->MEM[paddr - S->MEMBASE] = data; + } + + if (!S->riscv->cache_activated || !trans.cacheable) + { + S->stallaction(E, S, paddr, MEM_WRITE_STALL, latency); + } + + return; +} + +tuck void +riscVwriteword(Engine *E, State *S, ulong vaddr, ulong xdata) +{ + int inram, latency = 0; + TransAddr trans; + ulong paddr; + ushort data = xdata & 0xFFFF; + + /* */ + /* Translate address. If error occured, we do nothing: */ + /* faulting instruction will get re-executed after the */ + /* exception is handled. */ + /* */ + trans.vaddr = vaddr; + trans.error = 0; + S->vmtranslate(E, S, MEM_WRITE_WORD, &trans); + if (trans.error) + { + return; + } + + paddr = trans.paddr; + inram = 0; + + /* */ + /* An address error if word data is written to an */ + /* address other than 2n or if longword data is written */ + /* to an address other than 4n */ + /* */ + if (paddr & B0001) + { + /* raise address error */ + } + + if ((paddr >= S->MEMBASE) && (paddr < S->MEMEND-1)) /* -1 for 2nd byte */ + { + inram = 1; + latency = S->mem_w_latency; + } + + if (!inram) + { + /* */ + /* Pass this address off to the devices. */ + /* We perform the necessary bitflip analysis in */ + /* devport. If addr not found in devport, try */ + /* arch-specific dev if not, fail with sfatal. */ + /* */ + devportwriteword(E, S, vaddr, data); + + return; + } + + + + if (inram) + { + write_2(S, data, &S->MEM[paddr - S->MEMBASE]); + + /*S->MEM[paddr - S->MEMBASE] = (uchar)((data>>8)&0xFF); + S->MEM[paddr+1 - S->MEMBASE] = (uchar)data&0xFF;*/ + } + + if (!S->riscv->cache_activated || !trans.cacheable) + { + S->stallaction(E, S, paddr, MEM_WRITE_STALL, latency); + } + + return; +} + +tuck void +riscVwritelong(Engine *E, State *S, ulong vaddr, ulong data) +{ + int inram, latency = 0; + TransAddr trans; + ulong paddr; + + /* */ + /* Translate address. If error occured, we do nothing: */ + /* faulting instruction will get re-executed after the */ + /* exception is handled. */ + /* */ + trans.vaddr = vaddr; + trans.error = 0; + S->vmtranslate(E, S, MEM_WRITE_LONG, &trans); + if (trans.error) + { + return; + } + + paddr = trans.paddr; + inram = 0; + + /* */ + /* An address error if word data is written to an */ + /* address other than 2n or if longword data is written */ + /* to an address other than 4n */ + /* */ + if (paddr & B0011) + { + /* raise address error */ + } + + if ((paddr >= S->MEMBASE) && (paddr < S->MEMEND - 3)) /* -3 for 4th byte */ + { + inram = 1; + latency = S->mem_w_latency; + } + + if (!inram) + { + /* */ + /* Pass this address off to the devices. */ + /* We perform the necessary bitflip analysis in */ + /* devport. If addr not found in devport, try */ + /* arch-specific dev if not, fail with sfatal. */ + /* */ + devportwritelong(E, S, vaddr, data); + + return; + } + + if (inram) + { + write_4(S, data, &(S->MEM[paddr - S->MEMBASE])); + + /*S->MEM[paddr - S->MEMBASE] = (uchar)((data>>24)&0xFF); + S->MEM[paddr+1 - S->MEMBASE] = (uchar)((data>>16)&0xFF); + S->MEM[paddr+2 - S->MEMBASE] = (uchar)((data>>8)&0xFF); + S->MEM[paddr+3 - S->MEMBASE] = (uchar)data&0xFF;*/ + } + + if (!S->riscv->cache_activated || !trans.cacheable) + { + S->stallaction(E, S, paddr, MEM_WRITE_STALL, latency); + } + + return; +} + + +tuck uchar +riscVreadbyte(Engine *E, State *S, ulong vaddr) +{ + int inram, latency = 0; + TransAddr trans; + ulong paddr; + uchar data = 0; + + /* */ + /* Translate address. If error occured, we do nothing: */ + /* faulting instruction will get re-executed after the */ + /* exception is handled. */ + /* */ + trans.vaddr = vaddr; + trans.error = 0; + S->vmtranslate(E, S, MEM_READ_BYTE, &trans); + if (trans.error) + { + return; + } + + paddr = trans.paddr; + inram = 0; + + if ((paddr >= S->MEMBASE) && (paddr < S->MEMEND)) + { + inram = 1; + latency = S->mem_r_latency; + data = S->MEM[paddr - S->MEMBASE]; + } + + if (!inram) + { + /* */ + /* Pass this address off to the devices. */ + /* We perform the necessary bitflip analysis in */ + /* devport. If addr not found in devport, try */ + /* arch-specific dev if not, fail with sfatal. */ + /* */ + return devportreadbyte(E, S, vaddr); + } + + if (!S->riscv->cache_activated || !trans.cacheable) + { + S->stallaction(E, S, paddr, MEM_READ_STALL, latency); + } + + return data; +} + +tuck ushort +riscVreadword(Engine *E, State *S, ulong vaddr) +{ + int inram, latency = 0; + TransAddr trans; + ulong paddr; + ushort data = 0; + + /* */ + /* Translate address. If error occured, we do nothing: */ + /* faulting instruction will get re-executed after the */ + /* exception is handled. */ + /* */ + trans.vaddr = vaddr; + trans.error = 0; + S->vmtranslate(E, S, MEM_READ_WORD, &trans); + if (trans.error) + { + return; + } + + paddr = trans.paddr; + inram = 0; + + /* */ + /* An address error if word data is written to an */ + /* address other than 2n or if longword data is written */ + /* to an address other than 4n */ + /* */ + if (paddr & B0001) + { + /* raise address error */ + } + + if ((paddr >= S->MEMBASE) && (paddr < S->MEMEND - 1)) /* -1 for second byte */ + { + inram = 1; + latency = S->mem_r_latency; + read_2(S, &S->MEM[paddr - S->MEMBASE], &data); + //data = (ushort)(S->MEM[paddr - S->MEMBASE]<<8)|S->MEM[paddr+1 - S->MEMBASE]; + } + + if (!inram) + { + /* */ + /* Pass this address off to the devices. */ + /* We perform the necessary bitflip analysis in */ + /* devport. If addr not found in devport, try */ + /* arch-specific dev if not, fail with sfatal. */ + /* */ + return devportreadword(E, S, vaddr); + } + + if (!S->riscv->cache_activated || !trans.cacheable) + { + S->stallaction(E, S, paddr, MEM_READ_STALL, latency); + } + + return data; +} + +tuck ulong +riscVreadlong(Engine *E, State *S, ulong vaddr) +{ + int inram, latency = 0; + TransAddr trans; + ulong paddr; + ulong data = 0; + + /* */ + /* Translate address. If error occured, we do nothing: */ + /* faulting instruction will get re-executed after the */ + /* exception is handled. */ + /* */ + trans.vaddr = vaddr; + trans.error = 0; + S->vmtranslate(E, S, MEM_READ_LONG, &trans); + if (trans.error) + { + return; + } + + paddr = trans.paddr; + inram = 0; + + /* */ + /* An address error if word data is written to an */ + /* address other than 2n or if longword data is written */ + /* to an address other than 4n */ + /* */ + if (paddr & B0011) + { + /* raise address error */ + } + + if ((paddr >= S->MEMBASE) && (paddr < S->MEMEND - 3)) /* -3 for 4th byte */ + { + inram = 1; + latency = S->mem_r_latency; + read_4(S, &(S->MEM[paddr - S->MEMBASE]), &data); + /*data = (ulong)(S->MEM[paddr - S->MEMBASE]<<24)|\ + (S->MEM[paddr+1 - S->MEMBASE]<<16)|\ + (S->MEM[paddr+2 - S->MEMBASE]<<8)|\ + S->MEM[paddr+3 - S->MEMBASE];*/ + } + + if (!inram) + { + /* */ + /* Pass this address off to the devices. */ + /* We perform the necessary bitflip analysis in */ + /* devport. If addr not found in devport, try */ + /* arch-specific dev if not, fail with sfatal. */ + /* */ + return devportreadlong(E, S, vaddr); + } + + if (!S->riscv->cache_activated || !trans.cacheable) + { + S->stallaction(E, S, paddr, MEM_READ_STALL, latency); + } + + return data; +} diff --git a/sim/mfns.h b/sim/mfns.h index fbf3d458..f3a56e7b 100755 --- a/sim/mfns.h +++ b/sim/mfns.h @@ -425,6 +425,16 @@ void superHwritelong(Engine *, State *S, ulong addr, ulong data); void superHwriteword(Engine *, State *S, ulong addr, ulong data); void superHwritebyte(Engine *, State *S, ulong addr, ulong data); +uchar riscVreadbyte(Engine *, State *S, ulong addr); +ulong riscVreadlong(Engine *, State *S, ulong addr); +ushort riscVreadword(Engine *, State *S, ulong addr); +void riscVwritelong(Engine *, State *S, ulong addr, ulong data); +void riscVwriteword(Engine *, State *S, ulong addr, ulong data); +void riscVwritebyte(Engine *, State *S, ulong addr, ulong data); +void riscVcache_deactivate(Engine *, State *S); +int riscVcache_init(Engine *, State *S, int size, int blocksize, int assoc); +void riscVvmtranslate(Engine *E, State *S, int op, TransAddr *tr); + ulong devportreadlong(Engine *E, State *S, ulong addr); ushort devportreadword(Engine *E, State *S, ulong addr); uchar devportreadbyte(Engine *E, State *S, ulong addr); diff --git a/sim/op-riscv.c b/sim/op-riscv.c index c97130a6..fc9670b6 100644 --- a/sim/op-riscv.c +++ b/sim/op-riscv.c @@ -648,7 +648,7 @@ riscv_lw(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint16_t imm0) { uint32_t addr = reg_read_riscv(E,S, rs1) + sign_extend(imm0, 12); - uint32_t value = superHreadlong(E, S, addr); + uint32_t value = riscVreadlong(E, S, addr); reg_set_riscv(E, S, rd, value); @@ -666,7 +666,7 @@ riscv_lh(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint16_t imm0) { uint32_t addr = reg_read_riscv(E,S, rs1) + sign_extend(imm0, 12); - reg_set_riscv(E, S, rd, sign_extend(superHreadword(E, S, addr), 16)); + reg_set_riscv(E, S, rd, sign_extend(riscVreadword(E, S, addr), 16)); if (SF_TAINTANALYSIS) { @@ -682,7 +682,7 @@ riscv_lhu(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint16_t imm0) { uint32_t addr = reg_read_riscv(E,S, rs1) + sign_extend(imm0, 12); - reg_set_riscv(E, S, rd, (uint32_t) superHreadword(E, S, addr)); + reg_set_riscv(E, S, rd, (uint32_t) riscVreadword(E, S, addr)); if (SF_TAINTANALYSIS) { @@ -697,7 +697,7 @@ void riscv_lb(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint16_t imm0) { uint32_t addr = reg_read_riscv(E,S, rs1) + sign_extend(imm0, 12); - uint8_t data_b = superHreadword(E, S, addr) & 0xff; + uint8_t data_b = riscVreadword(E, S, addr) & 0xff; reg_set_riscv(E, S, rd, sign_extend(data_b, 8)); @@ -714,7 +714,7 @@ void riscv_lbu(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint16_t imm0) { uint32_t addr = reg_read_riscv(E,S, rs1) + sign_extend(imm0, 12); - uint8_t data_b = superHreadword(E, S, addr) & 0xff; + uint8_t data_b = riscVreadword(E, S, addr) & 0xff; reg_set_riscv(E, S, rd, (uint32_t) data_b); @@ -733,7 +733,7 @@ riscv_sw(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint16_t imm0, uint16_t uint32_t addr = reg_read_riscv(E,S, rs1) + sign_extend(imm0 + (imm5 << 5), 12); uint32_t value = reg_read_riscv(E,S, rs2); - superHwritelong(E, S, addr, value); + riscVwritelong(E, S, addr, value); if (SF_TAINTANALYSIS) { @@ -750,7 +750,7 @@ riscv_sh(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint16_t imm0, uint16_t { uint32_t addr = reg_read_riscv(E,S, rs1) + sign_extend(imm0 + (imm5 << 5), 12); - superHwriteword(E, S,addr, reg_read_riscv(E,S, rs2) & 0xffff); + riscVwriteword(E, S,addr, reg_read_riscv(E,S, rs2) & 0xffff); if (SF_TAINTANALYSIS) { @@ -767,7 +767,7 @@ riscv_sb(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint16_t imm0, uint16_t { uint32_t addr = reg_read_riscv(E,S, rs1) + sign_extend(imm0 + (imm5 << 5), 12); - superHwritebyte(E, S,addr, reg_read_riscv(E,S, rs2) & 0xff); + riscVwritebyte(E, S,addr, reg_read_riscv(E,S, rs2) & 0xff); if (SF_TAINTANALYSIS) { @@ -873,7 +873,7 @@ rv32f_flw(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint16_t imm0) /* * Perform a normal floating point load. */ - freg_set_riscv(E, S, rd, nan_box(superHreadlong(E, S, addr))); + freg_set_riscv(E, S, rd, nan_box(riscVreadlong(E, S, addr))); if (SF_TAINTANALYSIS) { @@ -917,7 +917,7 @@ rv32f_fsw(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint16_t imm0, uint16_t /* * Perform a normal floating point store. */ - superHwritelong(E, S, addr, freg_read_riscv(E, S, rs2)); + riscVwritelong(E, S, addr, freg_read_riscv(E, S, rs2)); if (SF_TAINTANALYSIS) { @@ -1748,8 +1748,8 @@ void rv32d_fld(Engine *E, State *S, uint8_t rs1, uint8_t rd, uint16_t imm0) { uint32_t addr = reg_read_riscv(E, S, rs1) + sign_extend(imm0, 12); - uint64_t data_lsw = (uint64_t)superHreadlong(E, S, addr); - uint64_t data_msw = (uint64_t)superHreadlong(E, S, (addr+4)); + uint64_t data_lsw = (uint64_t)riscVreadlong(E, S, addr); + uint64_t data_msw = (uint64_t)riscVreadlong(E, S, (addr+4)); uint64_t data = (data_msw << 32) | data_lsw; freg_set_riscv(E, S, rd, data); @@ -1771,8 +1771,8 @@ rv32d_fsd(Engine *E, State *S, uint8_t rs1, uint8_t rs2, uint16_t imm0, uint16_t uint32_t data_lsw = (uint32_t)(data & 0xffffffff); uint32_t data_msw = (uint32_t)((data >> 32) & 0xffffffff); - superHwritelong(E, S, addr, data_lsw); - superHwritelong(E, S, addr+4, data_msw); + riscVwritelong(E, S, addr, data_lsw); + riscVwritelong(E, S, addr+4, data_msw); if (SF_TAINTANALYSIS) { diff --git a/sim/pipeline-riscv.c b/sim/pipeline-riscv.c index fdeafd6b..da5c9218 100644 --- a/sim/pipeline-riscv.c +++ b/sim/pipeline-riscv.c @@ -312,7 +312,7 @@ riscvfaststep(Engine *E, State *S, int drain_pipeline) /* need to check for exceptions/interrupts here */ tmpPC = S->PC; - tmpinstr = superHreadlong(E, S, S->PC); + tmpinstr = riscVreadlong(E, S, S->PC); riscvdecode(E, tmpinstr, &(S->riscv->P.EX)); @@ -423,7 +423,7 @@ riscvstep(Engine *E, State *S, int drain_pipeline) int i, exec_energy_updated = 0, stall_energy_updated = 0; ulong tmpPC; Picosec saved_globaltime; - S->superH->SR.MD = 1; + //S->superH->SR.MD = 1; saved_globaltime = E->globaltimepsec; for (i = 0; (i < E->quantum) && E->on && S->runnable; i++) @@ -841,10 +841,10 @@ riscvstep(Engine *E, State *S, int drain_pipeline) } else { - S->superH->mem_access_type = MEM_ACCESS_IFETCH; - instrlong = superHreadlong(E, S, S->PC); + S->riscv->mem_access_type = MEM_ACCESS_IFETCH; + instrlong = riscVreadlong(E, S, S->PC); S->nfetched++; - S->superH->mem_access_type = MEM_ACCESS_NIL; + S->riscv->mem_access_type = MEM_ACCESS_NIL; } /* Count # bits flipping in IF */