-
Notifications
You must be signed in to change notification settings - Fork 1
/
afu_top.sv
186 lines (147 loc) · 5.58 KB
/
afu_top.sv
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
import ccip_if_pkg::*;
module afu_top #(
parameter NEXT_DFH_BYTE_OFFSET = 0
) (
input wire clk,
input wire CLK_200M,
input wire spl_reset,
// AFU TX read request
input wire spl_tx_rd_almostfull,
output wire afu_tx_rd_valid,
output t_ccip_c0_ReqMemHdr afu_tx_rd_hdr,
// AFU TX write request
input wire spl_tx_wr_almostfull,
output wire afu_tx_wr_valid,
output t_ccip_c1_ReqMemHdr afu_tx_wr_hdr,
output wire [511:0] afu_tx_data,
// AFU TX MMIO read response
output t_if_ccip_c2_Tx afu_tx_mmio,
// AFU RX read response
input wire spl_rx_rd_valid,
input wire spl_mmio_rd_valid,
input wire spl_mmio_wr_valid,
input t_ccip_c0_RspMemHdr spl_rx_rd_hdr,
input wire [511:0] spl_rx_data,
// AFU RX write response
input wire spl_rx_wr_valid,
input t_ccip_c1_RspMemHdr spl_rx_wr_hdr
);
//-------------------------------------------------
wire io_rx_rd_valid;
wire [511:0] io_rx_data;
wire cor_tx_rd_valid;
wire [57:0] cor_tx_rd_addr;
wire [5:0] cor_tx_rd_len;
wire cor_tx_wr_valid;
wire cor_tx_dsr_valid;
wire cor_tx_fence_valid;
wire cor_tx_done_valid;
wire [57:0] cor_tx_wr_addr;
wire [5:0] cor_tx_wr_len;
wire [511:0] cor_tx_data;
wire csr_id_valid;
wire csr_id_done;
wire [31:0] csr_id_addr;
wire csr_ctx_base_valid;
wire [57:0] csr_ctx_base;
wire core_reset_n;
wire core_start;
wire [63:0] io_src_ptr;
wire [63:0] io_dst_ptr;
wire [63:0] io_hand_ptr;
wire [63:0] io_input_base;
wire [63:0] dsm_base_addr;
afu_core afu_core(
.CLK_400M(clk),
.CLK_200M(CLK_200M),
.reset_n(core_reset_n),
.core_start_d(core_start),
.spl_reset(spl_reset),
// TX_RD request, afu_core --> afu_io
.spl_tx_rd_almostfull(spl_tx_rd_almostfull),
.cor_tx_rd_valid(cor_tx_rd_valid),
.cor_tx_rd_addr(cor_tx_rd_addr),
.cor_tx_rd_len(cor_tx_rd_len), // in CL, 0-64, 1-1, 2-2, ...63-63
// TX_WR request, afu_core --> afu_io
.spl_tx_wr_almostfull(spl_tx_wr_almostfull),
.cor_tx_wr_valid(cor_tx_wr_valid),
.cor_tx_dsr_valid(cor_tx_dsr_valid),
.cor_tx_fence_valid(cor_tx_fence_valid),
.cor_tx_done_valid(cor_tx_done_valid),
.cor_tx_wr_addr(cor_tx_wr_addr),
.cor_tx_wr_len(cor_tx_wr_len),
.cor_tx_data(cor_tx_data),
// RX_RD response, afu_io --> afu_core
.io_rx_rd_valid(io_rx_rd_valid),
.io_rx_data(io_rx_data),
// afu_csr --> afu_core, afu_id
.csr_id_valid(csr_id_valid),
.csr_id_done(csr_id_done),
.csr_id_addr(csr_id_addr),
// afu_csr --> afu_core, afu_ctx
.csr_ctx_base_valid(csr_ctx_base_valid),
.csr_ctx_base(csr_ctx_base),
.dsm_base_addr(dsm_base_addr),
.io_src_ptr(io_src_ptr),
.io_dst_ptr(io_dst_ptr),
.io_hand_ptr(io_hand_ptr),
.io_input_base(io_input_base)
);
afu_io #(
.NEXT_DFH_BYTE_OFFSET(NEXT_DFH_BYTE_OFFSET)
) afu_io (
.clk(clk),
.spl_reset(spl_reset),
// AFU TX read request
.spl_tx_rd_almostfull(spl_tx_rd_almostfull), //[Not needed here]
.afu_tx_rd_valid(afu_tx_rd_valid),
.afu_tx_rd_hdr(afu_tx_rd_hdr),
// AFU TX write request
.spl_tx_wr_almostfull(spl_tx_wr_almostfull), //[Not needed here]
.afu_tx_wr_valid(afu_tx_wr_valid),
.afu_tx_wr_hdr(afu_tx_wr_hdr),
.afu_tx_data(afu_tx_data),
// AFU TX MMIO read response
.afu_tx_mmio(afu_tx_mmio),
// AFU RX read response, MMIO request
.spl_rx_rd_valid(spl_rx_rd_valid),
.spl_mmio_rd_valid(spl_mmio_rd_valid),
.spl_mmio_wr_valid(spl_mmio_wr_valid),
.spl_rx_rd_hdr(spl_rx_rd_hdr),
.spl_rx_data(spl_rx_data),
// AFU RX write response
.spl_rx_wr_valid(spl_rx_wr_valid),
.spl_rx_wr_hdr(spl_rx_wr_hdr),
//============================================================
// RX_RD response, afu_io --> afu_core
.io_rx_rd_valid(io_rx_rd_valid),
.io_rx_data(io_rx_data),
// TX_RD request(), afu_core --> afu_io
.cor_tx_rd_valid(cor_tx_rd_valid),
.cor_tx_rd_addr(cor_tx_rd_addr),
.cor_tx_rd_len(cor_tx_rd_len),
// TX_WR request, afu_core --> afu_io
.cor_tx_wr_valid(cor_tx_wr_valid),
.cor_tx_dsr_valid(cor_tx_dsr_valid),
.cor_tx_fence_valid(cor_tx_fence_valid),
.cor_tx_done_valid(cor_tx_done_valid),
.cor_tx_wr_addr(cor_tx_wr_addr),
.cor_tx_wr_len(cor_tx_wr_len),
.cor_tx_data(cor_tx_data),
// afu_io --> afu_core
.dsm_base_addr(dsm_base_addr),
.io_src_ptr(io_src_ptr),
.io_dst_ptr(io_dst_ptr),
.io_hand_ptr(io_hand_ptr),
.io_input_base(io_input_base),
// afu_csr-->afu_core, afu_id
.csr_id_valid(csr_id_valid),
.csr_id_done(csr_id_done),
.csr_id_addr(csr_id_addr),
// afu_csr-->afu_core, afu_ctx_base
.csr_ctx_base_valid(csr_ctx_base_valid),
.csr_ctx_base(csr_ctx_base),
.core_reset_n(core_reset_n),
.core_start(core_start)
);
endmodule