sw_pe_array_sw_extend_eh_arr.v

// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
// 
// ==============================================================

`timescale 1 ns / 1 ps
module sw_pe_array_sw_extend_eh_arr_ram (clk, addr0, q0, addr1, d1, we1);

parameter DWIDTH = 16;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;

input[AWIDTH-1:0] addr0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input[DWIDTH-1:0] d1;
input we1;
input clk;

    (* `GRAM_STYLE = `GRAM_BLCK *)
 reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];




always @(posedge clk)  
begin 
   q0 <= ram[addr0];
end


always @(posedge clk)  
begin 
    if (we1) 
    begin 
        ram[addr1] <= d1; 
    end 
end


endmodule



`timescale 1 ns / 1 ps
module sw_pe_array_sw_extend_eh_arr(
    reset,
    clk,
    address0,
    ce0,
    q0,
    address1,
    ce1,
    we1,
    d1,
    q1);

parameter DataWidth = 32'd16;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
input we1;
input[DataWidth - 1:0] d1;
output[DataWidth - 1:0] q1;



sw_pe_array_sw_extend_eh_arr_ram sw_pe_array_sw_extend_eh_arr_ram_U(
    .clk( clk ),
    .addr0( address0 ),
    .q0( q0 ),
    .addr1( address1 ),
    .d1( d1 ),
    .we1( we1 ));

endmodule