sw_pe_array_receive_match.v

// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

module sw_pe_array_receive_match (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_continue,
        ap_idle,
        ap_ready,
        matchs_0_V_dout,
        matchs_0_V_empty_n,
        matchs_0_V_read,
        matchs_1_V_dout,
        matchs_1_V_empty_n,
        matchs_1_V_read,
        matchs_2_V_dout,
        matchs_2_V_empty_n,
        matchs_2_V_read,
        matchs_3_V_dout,
        matchs_3_V_empty_n,
        matchs_3_V_read,
        matchs_4_V_dout,
        matchs_4_V_empty_n,
        matchs_4_V_read,
        matchs_5_V_dout,
        matchs_5_V_empty_n,
        matchs_5_V_read,
        matchs_6_V_dout,
        matchs_6_V_empty_n,
        matchs_6_V_read,
        matchs_7_V_dout,
        matchs_7_V_empty_n,
        matchs_7_V_read,
        matchs_8_V_dout,
        matchs_8_V_empty_n,
        matchs_8_V_read,
        matchs_9_V_dout,
        matchs_9_V_empty_n,
        matchs_9_V_read,
        matchs_10_V_dout,
        matchs_10_V_empty_n,
        matchs_10_V_read,
        matchs_11_V_dout,
        matchs_11_V_empty_n,
        matchs_11_V_read,
        matchs_12_V_dout,
        matchs_12_V_empty_n,
        matchs_12_V_read,
        matchs_13_V_dout,
        matchs_13_V_empty_n,
        matchs_13_V_read,
        matchs_14_V_dout,
        matchs_14_V_empty_n,
        matchs_14_V_read,
        matchs_15_V_dout,
        matchs_15_V_empty_n,
        matchs_15_V_read,
        matchs_16_V_dout,
        matchs_16_V_empty_n,
        matchs_16_V_read,
        matchs_17_V_dout,
        matchs_17_V_empty_n,
        matchs_17_V_read,
        matchs_18_V_dout,
        matchs_18_V_empty_n,
        matchs_18_V_read,
        matchs_19_V_dout,
        matchs_19_V_empty_n,
        matchs_19_V_read,
        peArr_blockMatchs_V_din,
        peArr_blockMatchs_V_full_n,
        peArr_blockMatchs_V_write
);

parameter    ap_const_logic_1 = 1'b1;
parameter    ap_const_logic_0 = 1'b0;
parameter    ap_ST_st1_fsm_0 = 8'b1;
parameter    ap_ST_st2_fsm_1 = 8'b10;
parameter    ap_ST_st3_fsm_2 = 8'b100;
parameter    ap_ST_st4_fsm_3 = 8'b1000;
parameter    ap_ST_pp0_stg0_fsm_4 = 8'b10000;
parameter    ap_ST_st9_fsm_5 = 8'b100000;
parameter    ap_ST_pp1_stg0_fsm_6 = 8'b1000000;
parameter    ap_ST_st12_fsm_7 = 8'b10000000;
parameter    ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter    ap_const_lv1_1 = 1'b1;
parameter    ap_const_lv32_1 = 32'b1;
parameter    ap_const_lv5_12 = 5'b10010;
parameter    ap_const_lv1_0 = 1'b0;
parameter    ap_const_lv5_11 = 5'b10001;
parameter    ap_const_lv5_10 = 5'b10000;
parameter    ap_const_lv5_F = 5'b1111;
parameter    ap_const_lv5_E = 5'b1110;
parameter    ap_const_lv5_D = 5'b1101;
parameter    ap_const_lv5_C = 5'b1100;
parameter    ap_const_lv5_B = 5'b1011;
parameter    ap_const_lv5_A = 5'b1010;
parameter    ap_const_lv5_9 = 5'b1001;
parameter    ap_const_lv5_8 = 5'b1000;
parameter    ap_const_lv5_7 = 5'b111;
parameter    ap_const_lv5_6 = 5'b110;
parameter    ap_const_lv5_5 = 5'b101;
parameter    ap_const_lv5_4 = 5'b100;
parameter    ap_const_lv5_3 = 5'b11;
parameter    ap_const_lv5_2 = 5'b10;
parameter    ap_const_lv5_1 = 5'b1;
parameter    ap_const_lv5_0 = 5'b00000;
parameter    ap_const_lv32_4 = 32'b100;
parameter    ap_const_lv32_3 = 32'b11;
parameter    ap_const_lv32_5 = 32'b101;
parameter    ap_const_lv32_6 = 32'b110;
parameter    ap_const_lv32_2 = 32'b10;
parameter    ap_const_lv3_0 = 3'b000;
parameter    ap_const_lv2_0 = 2'b00;
parameter    ap_const_lv2_2 = 2'b10;
parameter    ap_const_lv2_1 = 2'b1;
parameter    ap_const_lv64_0 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter    ap_const_lv32_7 = 32'b111;
parameter    ap_const_lv32_FFFFFFFF = 32'b11111111111111111111111111111111;
parameter    ap_const_lv8_0 = 8'b00000000;
parameter    ap_const_lv3_4 = 3'b100;
parameter    ap_const_lv3_1 = 3'b1;
parameter    ap_const_lv8_1 = 8'b1;
parameter    ap_const_lv8_13 = 8'b10011;
parameter    ap_const_lv3_5 = 3'b101;
parameter    ap_true = 1'b1;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
input   ap_continue;
output   ap_idle;
output   ap_ready;
input  [31:0] matchs_0_V_dout;
input   matchs_0_V_empty_n;
output   matchs_0_V_read;
input  [31:0] matchs_1_V_dout;
input   matchs_1_V_empty_n;
output   matchs_1_V_read;
input  [31:0] matchs_2_V_dout;
input   matchs_2_V_empty_n;
output   matchs_2_V_read;
input  [31:0] matchs_3_V_dout;
input   matchs_3_V_empty_n;
output   matchs_3_V_read;
input  [31:0] matchs_4_V_dout;
input   matchs_4_V_empty_n;
output   matchs_4_V_read;
input  [31:0] matchs_5_V_dout;
input   matchs_5_V_empty_n;
output   matchs_5_V_read;
input  [31:0] matchs_6_V_dout;
input   matchs_6_V_empty_n;
output   matchs_6_V_read;
input  [31:0] matchs_7_V_dout;
input   matchs_7_V_empty_n;
output   matchs_7_V_read;
input  [31:0] matchs_8_V_dout;
input   matchs_8_V_empty_n;
output   matchs_8_V_read;
input  [31:0] matchs_9_V_dout;
input   matchs_9_V_empty_n;
output   matchs_9_V_read;
input  [31:0] matchs_10_V_dout;
input   matchs_10_V_empty_n;
output   matchs_10_V_read;
input  [31:0] matchs_11_V_dout;
input   matchs_11_V_empty_n;
output   matchs_11_V_read;
input  [31:0] matchs_12_V_dout;
input   matchs_12_V_empty_n;
output   matchs_12_V_read;
input  [31:0] matchs_13_V_dout;
input   matchs_13_V_empty_n;
output   matchs_13_V_read;
input  [31:0] matchs_14_V_dout;
input   matchs_14_V_empty_n;
output   matchs_14_V_read;
input  [31:0] matchs_15_V_dout;
input   matchs_15_V_empty_n;
output   matchs_15_V_read;
input  [31:0] matchs_16_V_dout;
input   matchs_16_V_empty_n;
output   matchs_16_V_read;
input  [31:0] matchs_17_V_dout;
input   matchs_17_V_empty_n;
output   matchs_17_V_read;
input  [31:0] matchs_18_V_dout;
input   matchs_18_V_empty_n;
output   matchs_18_V_read;
input  [31:0] matchs_19_V_dout;
input   matchs_19_V_empty_n;
output   matchs_19_V_read;
output  [31:0] peArr_blockMatchs_V_din;
input   peArr_blockMatchs_V_full_n;
output   peArr_blockMatchs_V_write;

reg ap_done;
reg ap_idle;
reg ap_ready;
reg matchs_0_V_read;
reg matchs_1_V_read;
reg matchs_2_V_read;
reg matchs_3_V_read;
reg matchs_4_V_read;
reg matchs_5_V_read;
reg matchs_6_V_read;
reg matchs_7_V_read;
reg matchs_8_V_read;
reg matchs_9_V_read;
reg matchs_10_V_read;
reg matchs_11_V_read;
reg matchs_12_V_read;
reg matchs_13_V_read;
reg matchs_14_V_read;
reg matchs_15_V_read;
reg matchs_16_V_read;
reg matchs_17_V_read;
reg matchs_18_V_read;
reg matchs_19_V_read;
reg[31:0] peArr_blockMatchs_V_din;
reg peArr_blockMatchs_V_write;
reg    ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg   [7:0] ap_CS_fsm = 8'b1;
reg    ap_sig_cseq_ST_st1_fsm_0;
reg    ap_sig_bdd_27;
reg   [2:0] i_0_i_reg_661;
reg   [2:0] l_reg_735;
reg   [31:0] reg_750;
reg    ap_sig_cseq_ST_st2_fsm_1;
reg    ap_sig_bdd_131;
wire   [4:0] tmp_34_fu_883_p1;
reg   [0:0] tmp_phi_fu_553_p40;
reg    ap_sig_bdd_292;
reg    ap_sig_cseq_ST_pp0_stg0_fsm_4;
reg    ap_sig_bdd_301;
reg    ap_reg_ppiten_pp0_it0 = 1'b0;
reg   [4:0] tmp_34_reg_1004;
reg   [0:0] exitcond_i_reg_1012;
reg    ap_sig_bdd_423;
reg    ap_reg_ppiten_pp0_it1 = 1'b0;
reg    ap_reg_ppiten_pp0_it2 = 1'b0;
reg    ap_reg_ppiten_pp0_it3 = 1'b0;
reg   [31:0] reg_756;
reg   [31:0] reg_762;
reg   [31:0] reg_768;
reg   [31:0] reg_774;
reg   [31:0] reg_780;
reg   [31:0] reg_786;
reg   [31:0] reg_792;
reg   [31:0] reg_798;
reg   [31:0] reg_804;
reg   [31:0] reg_810;
reg   [31:0] reg_816;
reg   [31:0] reg_822;
reg   [31:0] reg_828;
reg   [31:0] reg_834;
reg   [31:0] reg_840;
reg   [31:0] reg_846;
reg   [31:0] reg_852;
reg   [31:0] reg_858;
reg   [31:0] reg_864;
wire   [2:0] matchBuf_addr_gep_fu_524_p3;
reg   [2:0] matchBuf_addr_reg_993;
reg    ap_sig_bdd_535;
reg   [7:0] j_load_reg_998;
wire   [0:0] tmp_s_fu_887_p2;
reg    ap_sig_cseq_ST_st4_fsm_3;
reg    ap_sig_bdd_547;
wire   [0:0] exitcond_i_fu_893_p2;
reg   [0:0] ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1;
reg   [0:0] ap_reg_ppstg_exitcond_i_reg_1012_pp0_it2;
wire   [2:0] i_fu_899_p2;
reg   [2:0] i_reg_1016;
reg   [2:0] matchBuf_addr_1_reg_1021;
reg   [2:0] ap_reg_ppstg_matchBuf_addr_1_reg_1021_pp0_it1;
reg   [2:0] ap_reg_ppstg_matchBuf_addr_1_reg_1021_pp0_it2;
wire   [0:0] tmp_22_fu_910_p2;
reg    ap_sig_cseq_ST_st9_fsm_5;
reg    ap_sig_bdd_571;
wire   [0:0] tmp_26_fu_916_p2;
wire   [0:0] exitcond_fu_956_p2;
reg   [0:0] exitcond_reg_1034;
reg    ap_sig_cseq_ST_pp1_stg0_fsm_6;
reg    ap_sig_bdd_584;
reg    ap_reg_ppiten_pp1_it0 = 1'b0;
reg    ap_sig_bdd_591;
reg    ap_reg_ppiten_pp1_it1 = 1'b0;
wire   [2:0] l_1_fu_962_p2;
reg   [2:0] matchBuf_address0;
reg    matchBuf_ce0;
reg    matchBuf_we0;
reg   [31:0] matchBuf_d0;
wire   [31:0] matchBuf_q0;
reg   [31:0] tmp_55_reg_615;
reg    ap_sig_cseq_ST_st3_fsm_2;
reg    ap_sig_bdd_694;
reg   [2:0] i_0_i_phi_fu_665_p4;
wire   [31:0] ap_reg_phiprechg_tmp_610_reg_672pp0_it2;
reg   [31:0] ap_reg_phiprechg_tmp_610_reg_672pp0_it3;
reg   [1:0] getPeMatchFlag_reg_718;
wire   [63:0] tmp_24_fu_905_p1;
wire   [63:0] tmp_29_fu_968_p1;
reg    ap_sig_cseq_ST_st12_fsm_7;
reg    ap_sig_bdd_853;
wire   [0:0] tmp_27_fu_973_p2;
reg    ap_sig_bdd_859;
reg   [7:0] peOver_cnt_fu_224;
wire   [7:0] peOver_cnt_1_fu_922_p2;
reg   [7:0] j_fu_228;
wire   [7:0] j_1_fu_943_p3;
wire   [0:0] tmp_25_fu_933_p2;
wire   [7:0] j_2_fu_938_p2;
reg   [7:0] ap_NS_fsm;
reg    ap_sig_bdd_728;
reg    ap_sig_bdd_731;
reg    ap_sig_bdd_733;
reg    ap_sig_bdd_735;
reg    ap_sig_bdd_737;
reg    ap_sig_bdd_739;
reg    ap_sig_bdd_741;
reg    ap_sig_bdd_743;
reg    ap_sig_bdd_745;
reg    ap_sig_bdd_747;
reg    ap_sig_bdd_749;
reg    ap_sig_bdd_751;
reg    ap_sig_bdd_753;
reg    ap_sig_bdd_755;
reg    ap_sig_bdd_757;
reg    ap_sig_bdd_759;
reg    ap_sig_bdd_761;
reg    ap_sig_bdd_763;
reg    ap_sig_bdd_765;
reg    ap_sig_bdd_767;
reg    ap_sig_bdd_725;
reg    ap_sig_bdd_402;
reg    ap_sig_bdd_271;


sw_pe_array_receive_match_matchBuf #(
    .DataWidth( 32 ),
    .AddressRange( 5 ),
    .AddressWidth( 3 ))
matchBuf_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( matchBuf_address0 ),
    .ce0( matchBuf_ce0 ),
    .we0( matchBuf_we0 ),
    .d0( matchBuf_d0 ),
    .q0( matchBuf_q0 )
);



/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_st1_fsm_0;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
    if (ap_rst == 1'b1) begin
        ap_done_reg <= ap_const_logic_0;
    end else begin
        if ((ap_const_logic_1 == ap_continue)) begin
            ap_done_reg <= ap_const_logic_0;
        end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_7) & ~(ap_const_lv1_0 == tmp_27_fu_973_p2) & ~ap_sig_bdd_859)) begin
            ap_done_reg <= ap_const_logic_1;
        end
    end
end

/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
    end else begin
        if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(ap_const_lv1_0 == exitcond_i_fu_893_p2))) begin
            ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
        end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (ap_const_lv1_0 == tmp_s_fu_887_p2))) begin
            ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
        end
    end
end

/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
    end else begin
        if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == exitcond_i_fu_893_p2))) begin
            ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
        end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (ap_const_lv1_0 == tmp_s_fu_887_p2)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(ap_const_lv1_0 == exitcond_i_fu_893_p2)))) begin
            ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
        end
    end
end

/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
    end else begin
        if (~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
            ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
        end
    end
end

/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
    end else begin
        if (~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
            ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
        end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (ap_const_lv1_0 == tmp_s_fu_887_p2))) begin
            ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
        end
    end
end

/// ap_reg_ppiten_pp1_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it0
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
    end else begin
        if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_6) & ~(ap_sig_bdd_591 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(ap_const_lv1_0 == exitcond_fu_956_p2))) begin
            ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
        end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_5) & (ap_const_lv1_0 == tmp_22_fu_910_p2) & ~(ap_const_lv1_0 == tmp_26_fu_916_p2))) begin
            ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
        end
    end
end

/// ap_reg_ppiten_pp1_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it1
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
    end else begin
        if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_6) & ~(ap_sig_bdd_591 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == exitcond_fu_956_p2))) begin
            ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
        end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_5) & (ap_const_lv1_0 == tmp_22_fu_910_p2) & ~(ap_const_lv1_0 == tmp_26_fu_916_p2)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_6) & ~(ap_sig_bdd_591 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(ap_const_lv1_0 == exitcond_fu_956_p2)))) begin
            ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
        end
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (ap_sig_bdd_725) begin
        if (ap_sig_bdd_767) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_858;
        end else if (ap_sig_bdd_765) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_852;
        end else if (ap_sig_bdd_763) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_846;
        end else if (ap_sig_bdd_761) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_840;
        end else if (ap_sig_bdd_759) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_834;
        end else if (ap_sig_bdd_757) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_828;
        end else if (ap_sig_bdd_755) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_822;
        end else if (ap_sig_bdd_753) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_816;
        end else if (ap_sig_bdd_751) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_810;
        end else if (ap_sig_bdd_749) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_804;
        end else if (ap_sig_bdd_747) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_798;
        end else if (ap_sig_bdd_745) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_792;
        end else if (ap_sig_bdd_743) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_786;
        end else if (ap_sig_bdd_741) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_780;
        end else if (ap_sig_bdd_739) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_774;
        end else if (ap_sig_bdd_737) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_768;
        end else if (ap_sig_bdd_735) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_762;
        end else if (ap_sig_bdd_733) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_756;
        end else if (ap_sig_bdd_731) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_750;
        end else if (ap_sig_bdd_728) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= reg_864;
        end else if ((ap_true == ap_true)) begin
            ap_reg_phiprechg_tmp_610_reg_672pp0_it3 <= ap_reg_phiprechg_tmp_610_reg_672pp0_it2;
        end
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(ap_const_lv1_0 == exitcond_i_fu_893_p2))) begin
        getPeMatchFlag_reg_718 <= ap_const_lv2_1;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(ap_const_lv1_0 == tmp_s_fu_887_p2))) begin
        getPeMatchFlag_reg_718 <= ap_const_lv2_2;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (tmp_phi_fu_553_p40 == ap_const_lv1_0) & ~ap_sig_bdd_292)) begin
        getPeMatchFlag_reg_718 <= ap_const_lv2_0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (ap_const_lv1_0 == tmp_s_fu_887_p2))) begin
        i_0_i_reg_661 <= ap_const_lv3_0;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
        i_0_i_reg_661 <= i_reg_1016;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_5) & ~(ap_const_lv1_0 == tmp_22_fu_910_p2))) begin
        j_fu_228 <= j_1_fu_943_p3;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_535)) begin
        j_fu_228 <= ap_const_lv8_0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_5) & (ap_const_lv1_0 == tmp_22_fu_910_p2) & ~(ap_const_lv1_0 == tmp_26_fu_916_p2))) begin
        l_reg_735 <= ap_const_lv3_0;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_6) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_591 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & (ap_const_lv1_0 == exitcond_fu_956_p2))) begin
        l_reg_735 <= l_1_fu_962_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_5) & (ap_const_lv1_0 == tmp_22_fu_910_p2) & (ap_const_lv1_0 == tmp_26_fu_916_p2))) begin
        peOver_cnt_fu_224 <= peOver_cnt_1_fu_922_p2;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_535)) begin
        peOver_cnt_fu_224 <= ap_const_lv8_0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
        if ((ap_const_lv5_0 == tmp_34_reg_1004)) begin
            tmp_55_reg_615 <= reg_858;
        end else if ((ap_const_lv5_1 == tmp_34_reg_1004)) begin
            tmp_55_reg_615 <= reg_852;
        end else if ((ap_const_lv5_2 == tmp_34_reg_1004)) begin
            tmp_55_reg_615 <= reg_846;
        end else if ((ap_const_lv5_3 == tmp_34_reg_1004)) begin
            tmp_55_reg_615 <= reg_840;
        end else if ((ap_const_lv5_4 == tmp_34_reg_1004)) begin
            tmp_55_reg_615 <= reg_834;
        end else if ((ap_const_lv5_5 == tmp_34_reg_1004)) begin
            tmp_55_reg_615 <= reg_828;
        end else if ((ap_const_lv5_6 == tmp_34_reg_1004)) begin
            tmp_55_reg_615 <= reg_822;
        end else if ((ap_const_lv5_7 == tmp_34_reg_1004)) begin
            tmp_55_reg_615 <= reg_816;
        end else if ((ap_const_lv5_8 == tmp_34_reg_1004)) begin
            tmp_55_reg_615 <= reg_810;
        end else if ((ap_const_lv5_9 == tmp_34_reg_1004)) begin
            tmp_55_reg_615 <= reg_804;
        end else if ((ap_const_lv5_A == tmp_34_reg_1004)) begin
            tmp_55_reg_615 <= reg_798;
        end else if ((ap_const_lv5_B == tmp_34_reg_1004)) begin
            tmp_55_reg_615 <= reg_792;
        end else if ((ap_const_lv5_C == tmp_34_reg_1004)) begin
            tmp_55_reg_615 <= reg_786;
        end else if ((ap_const_lv5_D == tmp_34_reg_1004)) begin
            tmp_55_reg_615 <= reg_780;
        end else if ((ap_const_lv5_E == tmp_34_reg_1004)) begin
            tmp_55_reg_615 <= reg_774;
        end else if ((ap_const_lv5_F == tmp_34_reg_1004)) begin
            tmp_55_reg_615 <= reg_768;
        end else if ((ap_const_lv5_10 == tmp_34_reg_1004)) begin
            tmp_55_reg_615 <= reg_762;
        end else if ((ap_const_lv5_11 == tmp_34_reg_1004)) begin
            tmp_55_reg_615 <= reg_756;
        end else if ((ap_const_lv5_12 == tmp_34_reg_1004)) begin
            tmp_55_reg_615 <= reg_750;
        end else if (ap_sig_bdd_402) begin
            tmp_55_reg_615 <= reg_864;
        end
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
        ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1 <= exitcond_i_reg_1012;
        ap_reg_ppstg_matchBuf_addr_1_reg_1021_pp0_it1 <= matchBuf_addr_1_reg_1021;
        exitcond_i_reg_1012 <= exitcond_i_fu_893_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
        ap_reg_ppstg_exitcond_i_reg_1012_pp0_it2 <= ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1;
        ap_reg_ppstg_matchBuf_addr_1_reg_1021_pp0_it2 <= ap_reg_ppstg_matchBuf_addr_1_reg_1021_pp0_it1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_6) & ~(ap_sig_bdd_591 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
        exitcond_reg_1034 <= exitcond_fu_956_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
        i_reg_1016 <= i_fu_899_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~ap_sig_bdd_292)) begin
        j_load_reg_998 <= j_fu_228;
        tmp_34_reg_1004 <= tmp_34_fu_883_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == exitcond_i_fu_893_p2))) begin
        matchBuf_addr_1_reg_1021 <= tmp_24_fu_905_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (tmp_34_fu_883_p1 == ap_const_lv5_12) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv5_12 == tmp_34_reg_1004) & (ap_const_lv1_0 == exitcond_i_reg_1012) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_750 <= matchs_18_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_11) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_11 == tmp_34_reg_1004) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_756 <= matchs_17_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_10) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_10 == tmp_34_reg_1004) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_762 <= matchs_16_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_F) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_F == tmp_34_reg_1004) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_768 <= matchs_15_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_E) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_E == tmp_34_reg_1004) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_774 <= matchs_14_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_D) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_D == tmp_34_reg_1004) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_780 <= matchs_13_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_C) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_C == tmp_34_reg_1004) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_786 <= matchs_12_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_B) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_B == tmp_34_reg_1004) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_792 <= matchs_11_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_A) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_A == tmp_34_reg_1004) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_798 <= matchs_10_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_9) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_9 == tmp_34_reg_1004) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_804 <= matchs_9_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_8) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_8 == tmp_34_reg_1004) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_810 <= matchs_8_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_7) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_7 == tmp_34_reg_1004) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_816 <= matchs_7_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_6) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_6 == tmp_34_reg_1004) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_822 <= matchs_6_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_5) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_5 == tmp_34_reg_1004) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_828 <= matchs_5_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_4) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_4 == tmp_34_reg_1004) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_834 <= matchs_4_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_3) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_3 == tmp_34_reg_1004) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_840 <= matchs_3_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_2) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_2 == tmp_34_reg_1004) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_846 <= matchs_2_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_1) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_1 == tmp_34_reg_1004) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_852 <= matchs_1_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_0) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_0 == tmp_34_reg_1004) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_858 <= matchs_0_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & ~(tmp_34_fu_883_p1 == ap_const_lv5_12) & ~(tmp_34_fu_883_p1 == ap_const_lv5_11) & ~(tmp_34_fu_883_p1 == ap_const_lv5_10) & ~(tmp_34_fu_883_p1 == ap_const_lv5_F) & ~(tmp_34_fu_883_p1 == ap_const_lv5_E) & ~(tmp_34_fu_883_p1 == ap_const_lv5_D) & ~(tmp_34_fu_883_p1 == ap_const_lv5_C) & ~(tmp_34_fu_883_p1 == ap_const_lv5_B) & ~(tmp_34_fu_883_p1 == ap_const_lv5_A) & ~(tmp_34_fu_883_p1 == ap_const_lv5_9) & ~(tmp_34_fu_883_p1 == ap_const_lv5_8) & ~(tmp_34_fu_883_p1 == ap_const_lv5_7) & ~(tmp_34_fu_883_p1 == ap_const_lv5_6) & ~(tmp_34_fu_883_p1 == ap_const_lv5_5) & ~(tmp_34_fu_883_p1 == ap_const_lv5_4) & ~(tmp_34_fu_883_p1 == ap_const_lv5_3) & ~(tmp_34_fu_883_p1 == ap_const_lv5_2) & ~(tmp_34_fu_883_p1 == ap_const_lv5_1) & ~(tmp_34_fu_883_p1 == ap_const_lv5_0) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & ~(ap_const_lv5_12 == tmp_34_reg_1004) & ~(ap_const_lv5_11 == tmp_34_reg_1004) & ~(ap_const_lv5_10 == tmp_34_reg_1004) & ~(ap_const_lv5_F == tmp_34_reg_1004) & ~(ap_const_lv5_E == tmp_34_reg_1004) & ~(ap_const_lv5_D == tmp_34_reg_1004) & ~(ap_const_lv5_C == tmp_34_reg_1004) & ~(ap_const_lv5_B == tmp_34_reg_1004) & ~(ap_const_lv5_A == tmp_34_reg_1004) & ~(ap_const_lv5_9 == tmp_34_reg_1004) & ~(ap_const_lv5_8 == tmp_34_reg_1004) & ~(ap_const_lv5_7 == tmp_34_reg_1004) & ~(ap_const_lv5_6 == tmp_34_reg_1004) & ~(ap_const_lv5_5 == tmp_34_reg_1004) & ~(ap_const_lv5_4 == tmp_34_reg_1004) & ~(ap_const_lv5_3 == tmp_34_reg_1004) & ~(ap_const_lv5_2 == tmp_34_reg_1004) & ~(ap_const_lv5_1 == tmp_34_reg_1004) & ~(ap_const_lv5_0 == tmp_34_reg_1004) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        reg_864 <= matchs_19_V_dout;
    end
end

/// ap_done assign process. ///
always @ (ap_done_reg or ap_sig_cseq_ST_st12_fsm_7 or tmp_27_fu_973_p2 or ap_sig_bdd_859)
begin
    if (((ap_const_logic_1 == ap_done_reg) | ((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_7) & ~(ap_const_lv1_0 == tmp_27_fu_973_p2) & ~ap_sig_bdd_859))) begin
        ap_done = ap_const_logic_1;
    end else begin
        ap_done = ap_const_logic_0;
    end
end

/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
    if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
        ap_idle = ap_const_logic_1;
    end else begin
        ap_idle = ap_const_logic_0;
    end
end

/// ap_ready assign process. ///
always @ (ap_sig_cseq_ST_st12_fsm_7 or tmp_27_fu_973_p2 or ap_sig_bdd_859)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_7) & ~(ap_const_lv1_0 == tmp_27_fu_973_p2) & ~ap_sig_bdd_859)) begin
        ap_ready = ap_const_logic_1;
    end else begin
        ap_ready = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_pp0_stg0_fsm_4 assign process. ///
always @ (ap_sig_bdd_301)
begin
    if (ap_sig_bdd_301) begin
        ap_sig_cseq_ST_pp0_stg0_fsm_4 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_pp0_stg0_fsm_4 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_pp1_stg0_fsm_6 assign process. ///
always @ (ap_sig_bdd_584)
begin
    if (ap_sig_bdd_584) begin
        ap_sig_cseq_ST_pp1_stg0_fsm_6 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_pp1_stg0_fsm_6 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st12_fsm_7 assign process. ///
always @ (ap_sig_bdd_853)
begin
    if (ap_sig_bdd_853) begin
        ap_sig_cseq_ST_st12_fsm_7 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st12_fsm_7 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_27)
begin
    if (ap_sig_bdd_27) begin
        ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_131)
begin
    if (ap_sig_bdd_131) begin
        ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st3_fsm_2 assign process. ///
always @ (ap_sig_bdd_694)
begin
    if (ap_sig_bdd_694) begin
        ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st4_fsm_3 assign process. ///
always @ (ap_sig_bdd_547)
begin
    if (ap_sig_bdd_547) begin
        ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st9_fsm_5 assign process. ///
always @ (ap_sig_bdd_571)
begin
    if (ap_sig_bdd_571) begin
        ap_sig_cseq_ST_st9_fsm_5 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st9_fsm_5 = ap_const_logic_0;
    end
end

/// i_0_i_phi_fu_665_p4 assign process. ///
always @ (i_0_i_reg_661 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or exitcond_i_reg_1012 or ap_reg_ppiten_pp0_it1 or i_reg_1016)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
        i_0_i_phi_fu_665_p4 = i_reg_1016;
    end else begin
        i_0_i_phi_fu_665_p4 = i_0_i_reg_661;
    end
end

/// matchBuf_address0 assign process. ///
always @ (ap_reg_ppiten_pp0_it3 or matchBuf_addr_reg_993 or ap_sig_cseq_ST_st4_fsm_3 or ap_reg_ppstg_matchBuf_addr_1_reg_1021_pp0_it2 or ap_sig_cseq_ST_pp1_stg0_fsm_6 or ap_reg_ppiten_pp1_it0 or tmp_29_fu_968_p1)
begin
    if ((ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) begin
        matchBuf_address0 = ap_reg_ppstg_matchBuf_addr_1_reg_1021_pp0_it2;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3)) begin
        matchBuf_address0 = matchBuf_addr_reg_993;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_6) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0))) begin
        matchBuf_address0 = tmp_29_fu_968_p1;
    end else begin
        matchBuf_address0 = 'bx;
    end
end

/// matchBuf_ce0 assign process. ///
always @ (ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it3 or ap_sig_cseq_ST_st4_fsm_3 or ap_sig_cseq_ST_pp1_stg0_fsm_6 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_591 or ap_reg_ppiten_pp1_it1)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_6) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_591 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchBuf_ce0 = ap_const_logic_1;
    end else begin
        matchBuf_ce0 = ap_const_logic_0;
    end
end

/// matchBuf_d0 assign process. ///
always @ (ap_reg_ppiten_pp0_it3 or ap_sig_cseq_ST_st4_fsm_3 or tmp_55_reg_615 or ap_reg_phiprechg_tmp_610_reg_672pp0_it3)
begin
    if ((ap_const_logic_1 == ap_reg_ppiten_pp0_it3)) begin
        matchBuf_d0 = ap_reg_phiprechg_tmp_610_reg_672pp0_it3;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3)) begin
        matchBuf_d0 = tmp_55_reg_615;
    end else begin
        matchBuf_d0 = 'bx;
    end
end

/// matchBuf_we0 assign process. ///
always @ (ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it3 or ap_sig_cseq_ST_st4_fsm_3 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it2)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it2)))) begin
        matchBuf_we0 = ap_const_logic_1;
    end else begin
        matchBuf_we0 = ap_const_logic_0;
    end
end

/// matchs_0_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_0) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_0 == tmp_34_reg_1004) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_0_V_read = ap_const_logic_1;
    end else begin
        matchs_0_V_read = ap_const_logic_0;
    end
end

/// matchs_10_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_A) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_A == tmp_34_reg_1004) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_10_V_read = ap_const_logic_1;
    end else begin
        matchs_10_V_read = ap_const_logic_0;
    end
end

/// matchs_11_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_B) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_B == tmp_34_reg_1004) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_11_V_read = ap_const_logic_1;
    end else begin
        matchs_11_V_read = ap_const_logic_0;
    end
end

/// matchs_12_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_C) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_C == tmp_34_reg_1004) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_12_V_read = ap_const_logic_1;
    end else begin
        matchs_12_V_read = ap_const_logic_0;
    end
end

/// matchs_13_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_D) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_D == tmp_34_reg_1004) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_13_V_read = ap_const_logic_1;
    end else begin
        matchs_13_V_read = ap_const_logic_0;
    end
end

/// matchs_14_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_E) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_E == tmp_34_reg_1004) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_14_V_read = ap_const_logic_1;
    end else begin
        matchs_14_V_read = ap_const_logic_0;
    end
end

/// matchs_15_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_F) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_F == tmp_34_reg_1004) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_15_V_read = ap_const_logic_1;
    end else begin
        matchs_15_V_read = ap_const_logic_0;
    end
end

/// matchs_16_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_10) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_10 == tmp_34_reg_1004) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_16_V_read = ap_const_logic_1;
    end else begin
        matchs_16_V_read = ap_const_logic_0;
    end
end

/// matchs_17_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_11) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_11 == tmp_34_reg_1004) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_17_V_read = ap_const_logic_1;
    end else begin
        matchs_17_V_read = ap_const_logic_0;
    end
end

/// matchs_18_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (tmp_34_fu_883_p1 == ap_const_lv5_12) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv5_12 == tmp_34_reg_1004) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_18_V_read = ap_const_logic_1;
    end else begin
        matchs_18_V_read = ap_const_logic_0;
    end
end

/// matchs_19_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & ~(tmp_34_fu_883_p1 == ap_const_lv5_12) & ~(tmp_34_fu_883_p1 == ap_const_lv5_11) & ~(tmp_34_fu_883_p1 == ap_const_lv5_10) & ~(tmp_34_fu_883_p1 == ap_const_lv5_F) & ~(tmp_34_fu_883_p1 == ap_const_lv5_E) & ~(tmp_34_fu_883_p1 == ap_const_lv5_D) & ~(tmp_34_fu_883_p1 == ap_const_lv5_C) & ~(tmp_34_fu_883_p1 == ap_const_lv5_B) & ~(tmp_34_fu_883_p1 == ap_const_lv5_A) & ~(tmp_34_fu_883_p1 == ap_const_lv5_9) & ~(tmp_34_fu_883_p1 == ap_const_lv5_8) & ~(tmp_34_fu_883_p1 == ap_const_lv5_7) & ~(tmp_34_fu_883_p1 == ap_const_lv5_6) & ~(tmp_34_fu_883_p1 == ap_const_lv5_5) & ~(tmp_34_fu_883_p1 == ap_const_lv5_4) & ~(tmp_34_fu_883_p1 == ap_const_lv5_3) & ~(tmp_34_fu_883_p1 == ap_const_lv5_2) & ~(tmp_34_fu_883_p1 == ap_const_lv5_1) & ~(tmp_34_fu_883_p1 == ap_const_lv5_0) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & ~(ap_const_lv5_12 == tmp_34_reg_1004) & ~(ap_const_lv5_11 == tmp_34_reg_1004) & ~(ap_const_lv5_10 == tmp_34_reg_1004) & ~(ap_const_lv5_F == tmp_34_reg_1004) & ~(ap_const_lv5_E == tmp_34_reg_1004) & ~(ap_const_lv5_D == tmp_34_reg_1004) & ~(ap_const_lv5_C == tmp_34_reg_1004) & ~(ap_const_lv5_B == tmp_34_reg_1004) & ~(ap_const_lv5_A == tmp_34_reg_1004) & ~(ap_const_lv5_9 == tmp_34_reg_1004) & ~(ap_const_lv5_8 == tmp_34_reg_1004) & ~(ap_const_lv5_7 == tmp_34_reg_1004) & ~(ap_const_lv5_6 == tmp_34_reg_1004) & ~(ap_const_lv5_5 == tmp_34_reg_1004) & ~(ap_const_lv5_4 == tmp_34_reg_1004) & ~(ap_const_lv5_3 == tmp_34_reg_1004) & ~(ap_const_lv5_2 == tmp_34_reg_1004) & ~(ap_const_lv5_1 == tmp_34_reg_1004) & ~(ap_const_lv5_0 == tmp_34_reg_1004) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_19_V_read = ap_const_logic_1;
    end else begin
        matchs_19_V_read = ap_const_logic_0;
    end
end

/// matchs_1_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_1) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_1 == tmp_34_reg_1004) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_1_V_read = ap_const_logic_1;
    end else begin
        matchs_1_V_read = ap_const_logic_0;
    end
end

/// matchs_2_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_2) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_2 == tmp_34_reg_1004) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_2_V_read = ap_const_logic_1;
    end else begin
        matchs_2_V_read = ap_const_logic_0;
    end
end

/// matchs_3_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_3) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_3 == tmp_34_reg_1004) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_3_V_read = ap_const_logic_1;
    end else begin
        matchs_3_V_read = ap_const_logic_0;
    end
end

/// matchs_4_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_4) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_4 == tmp_34_reg_1004) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_4_V_read = ap_const_logic_1;
    end else begin
        matchs_4_V_read = ap_const_logic_0;
    end
end

/// matchs_5_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_5) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_5 == tmp_34_reg_1004) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_5_V_read = ap_const_logic_1;
    end else begin
        matchs_5_V_read = ap_const_logic_0;
    end
end

/// matchs_6_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_6) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_6 == tmp_34_reg_1004) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_6_V_read = ap_const_logic_1;
    end else begin
        matchs_6_V_read = ap_const_logic_0;
    end
end

/// matchs_7_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_7) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_7 == tmp_34_reg_1004) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_7_V_read = ap_const_logic_1;
    end else begin
        matchs_7_V_read = ap_const_logic_0;
    end
end

/// matchs_8_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_8) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_8 == tmp_34_reg_1004) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_8_V_read = ap_const_logic_1;
    end else begin
        matchs_8_V_read = ap_const_logic_0;
    end
end

/// matchs_9_V_read assign process. ///
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_sig_cseq_ST_pp0_stg0_fsm_4 or tmp_34_reg_1004 or exitcond_i_reg_1012 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (tmp_34_fu_883_p1 == ap_const_lv5_9) & ~ap_sig_bdd_292) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_4) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_9 == tmp_34_reg_1004) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))))) begin
        matchs_9_V_read = ap_const_logic_1;
    end else begin
        matchs_9_V_read = ap_const_logic_0;
    end
end

/// peArr_blockMatchs_V_din assign process. ///
always @ (exitcond_reg_1034 or ap_sig_cseq_ST_pp1_stg0_fsm_6 or ap_sig_bdd_591 or ap_reg_ppiten_pp1_it1 or matchBuf_q0 or ap_sig_cseq_ST_st12_fsm_7 or tmp_27_fu_973_p2 or ap_sig_bdd_859)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_7) & ~(ap_const_lv1_0 == tmp_27_fu_973_p2) & ~ap_sig_bdd_859)) begin
        peArr_blockMatchs_V_din = ap_const_lv32_FFFFFFFF;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_6) & (ap_const_lv1_0 == exitcond_reg_1034) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_591 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))) begin
        peArr_blockMatchs_V_din = matchBuf_q0;
    end else begin
        peArr_blockMatchs_V_din = 'bx;
    end
end

/// peArr_blockMatchs_V_write assign process. ///
always @ (exitcond_reg_1034 or ap_sig_cseq_ST_pp1_stg0_fsm_6 or ap_sig_bdd_591 or ap_reg_ppiten_pp1_it1 or ap_sig_cseq_ST_st12_fsm_7 or tmp_27_fu_973_p2 or ap_sig_bdd_859)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_6) & (ap_const_lv1_0 == exitcond_reg_1034) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~(ap_sig_bdd_591 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) | ((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_7) & ~(ap_const_lv1_0 == tmp_27_fu_973_p2) & ~ap_sig_bdd_859))) begin
        peArr_blockMatchs_V_write = ap_const_logic_1;
    end else begin
        peArr_blockMatchs_V_write = ap_const_logic_0;
    end
end

/// tmp_phi_fu_553_p40 assign process. ///
always @ (matchs_0_V_empty_n or matchs_1_V_empty_n or matchs_2_V_empty_n or matchs_3_V_empty_n or matchs_4_V_empty_n or matchs_5_V_empty_n or matchs_6_V_empty_n or matchs_7_V_empty_n or matchs_8_V_empty_n or matchs_9_V_empty_n or matchs_10_V_empty_n or matchs_11_V_empty_n or matchs_12_V_empty_n or matchs_13_V_empty_n or matchs_14_V_empty_n or matchs_15_V_empty_n or matchs_16_V_empty_n or matchs_17_V_empty_n or matchs_18_V_empty_n or matchs_19_V_empty_n or ap_sig_cseq_ST_st2_fsm_1 or tmp_34_fu_883_p1 or ap_sig_bdd_271)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
        if (ap_sig_bdd_271) begin
            tmp_phi_fu_553_p40 = matchs_19_V_empty_n;
        end else if ((tmp_34_fu_883_p1 == ap_const_lv5_12)) begin
            tmp_phi_fu_553_p40 = matchs_18_V_empty_n;
        end else if ((tmp_34_fu_883_p1 == ap_const_lv5_11)) begin
            tmp_phi_fu_553_p40 = matchs_17_V_empty_n;
        end else if ((tmp_34_fu_883_p1 == ap_const_lv5_10)) begin
            tmp_phi_fu_553_p40 = matchs_16_V_empty_n;
        end else if ((tmp_34_fu_883_p1 == ap_const_lv5_F)) begin
            tmp_phi_fu_553_p40 = matchs_15_V_empty_n;
        end else if ((tmp_34_fu_883_p1 == ap_const_lv5_E)) begin
            tmp_phi_fu_553_p40 = matchs_14_V_empty_n;
        end else if ((tmp_34_fu_883_p1 == ap_const_lv5_D)) begin
            tmp_phi_fu_553_p40 = matchs_13_V_empty_n;
        end else if ((tmp_34_fu_883_p1 == ap_const_lv5_C)) begin
            tmp_phi_fu_553_p40 = matchs_12_V_empty_n;
        end else if ((tmp_34_fu_883_p1 == ap_const_lv5_B)) begin
            tmp_phi_fu_553_p40 = matchs_11_V_empty_n;
        end else if ((tmp_34_fu_883_p1 == ap_const_lv5_A)) begin
            tmp_phi_fu_553_p40 = matchs_10_V_empty_n;
        end else if ((tmp_34_fu_883_p1 == ap_const_lv5_9)) begin
            tmp_phi_fu_553_p40 = matchs_9_V_empty_n;
        end else if ((tmp_34_fu_883_p1 == ap_const_lv5_8)) begin
            tmp_phi_fu_553_p40 = matchs_8_V_empty_n;
        end else if ((tmp_34_fu_883_p1 == ap_const_lv5_7)) begin
            tmp_phi_fu_553_p40 = matchs_7_V_empty_n;
        end else if ((tmp_34_fu_883_p1 == ap_const_lv5_6)) begin
            tmp_phi_fu_553_p40 = matchs_6_V_empty_n;
        end else if ((tmp_34_fu_883_p1 == ap_const_lv5_5)) begin
            tmp_phi_fu_553_p40 = matchs_5_V_empty_n;
        end else if ((tmp_34_fu_883_p1 == ap_const_lv5_4)) begin
            tmp_phi_fu_553_p40 = matchs_4_V_empty_n;
        end else if ((tmp_34_fu_883_p1 == ap_const_lv5_3)) begin
            tmp_phi_fu_553_p40 = matchs_3_V_empty_n;
        end else if ((tmp_34_fu_883_p1 == ap_const_lv5_2)) begin
            tmp_phi_fu_553_p40 = matchs_2_V_empty_n;
        end else if ((tmp_34_fu_883_p1 == ap_const_lv5_1)) begin
            tmp_phi_fu_553_p40 = matchs_1_V_empty_n;
        end else if ((tmp_34_fu_883_p1 == ap_const_lv5_0)) begin
            tmp_phi_fu_553_p40 = matchs_0_V_empty_n;
        end else begin
            tmp_phi_fu_553_p40 = 'bx;
        end
    end else begin
        tmp_phi_fu_553_p40 = 'bx;
    end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or tmp_phi_fu_553_p40 or ap_sig_bdd_292 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp0_it3 or ap_sig_bdd_535 or tmp_s_fu_887_p2 or exitcond_i_fu_893_p2 or tmp_22_fu_910_p2 or tmp_26_fu_916_p2 or exitcond_fu_956_p2 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_591 or ap_reg_ppiten_pp1_it1 or tmp_27_fu_973_p2 or ap_sig_bdd_859)
begin
    case (ap_CS_fsm)
        ap_ST_st1_fsm_0 : 
        begin
            if (~ap_sig_bdd_535) begin
                ap_NS_fsm = ap_ST_st2_fsm_1;
            end else begin
                ap_NS_fsm = ap_ST_st1_fsm_0;
            end
        end
        ap_ST_st2_fsm_1 : 
        begin
            if ((~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & ~ap_sig_bdd_292)) begin
                ap_NS_fsm = ap_ST_st3_fsm_2;
            end else if (((tmp_phi_fu_553_p40 == ap_const_lv1_0) & ~ap_sig_bdd_292)) begin
                ap_NS_fsm = ap_ST_st9_fsm_5;
            end else begin
                ap_NS_fsm = ap_ST_st2_fsm_1;
            end
        end
        ap_ST_st3_fsm_2 : 
        begin
            ap_NS_fsm = ap_ST_st4_fsm_3;
        end
        ap_ST_st4_fsm_3 : 
        begin
            if (~(ap_const_lv1_0 == tmp_s_fu_887_p2)) begin
                ap_NS_fsm = ap_ST_st9_fsm_5;
            end else begin
                ap_NS_fsm = ap_ST_pp0_stg0_fsm_4;
            end
        end
        ap_ST_pp0_stg0_fsm_4 : 
        begin
            if ((~((ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(ap_const_lv1_0 == exitcond_i_fu_893_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
                ap_NS_fsm = ap_ST_pp0_stg0_fsm_4;
            end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(ap_const_lv1_0 == exitcond_i_fu_893_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
                ap_NS_fsm = ap_ST_st9_fsm_5;
            end else begin
                ap_NS_fsm = ap_ST_pp0_stg0_fsm_4;
            end
        end
        ap_ST_st9_fsm_5 : 
        begin
            if (((ap_const_lv1_0 == tmp_26_fu_916_p2) | ~(ap_const_lv1_0 == tmp_22_fu_910_p2))) begin
                ap_NS_fsm = ap_ST_st12_fsm_7;
            end else begin
                ap_NS_fsm = ap_ST_pp1_stg0_fsm_6;
            end
        end
        ap_ST_pp1_stg0_fsm_6 : 
        begin
            if (~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_591 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(ap_const_lv1_0 == exitcond_fu_956_p2))) begin
                ap_NS_fsm = ap_ST_pp1_stg0_fsm_6;
            end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~(ap_sig_bdd_591 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)) & ~(ap_const_lv1_0 == exitcond_fu_956_p2))) begin
                ap_NS_fsm = ap_ST_st12_fsm_7;
            end else begin
                ap_NS_fsm = ap_ST_pp1_stg0_fsm_6;
            end
        end
        ap_ST_st12_fsm_7 : 
        begin
            if ((~(ap_const_lv1_0 == tmp_27_fu_973_p2) & ~ap_sig_bdd_859)) begin
                ap_NS_fsm = ap_ST_st1_fsm_0;
            end else if (((ap_const_lv1_0 == tmp_27_fu_973_p2) & ~ap_sig_bdd_859)) begin
                ap_NS_fsm = ap_ST_st2_fsm_1;
            end else begin
                ap_NS_fsm = ap_ST_st12_fsm_7;
            end
        end
        default : 
        begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign ap_reg_phiprechg_tmp_610_reg_672pp0_it2 = 'bx;

/// ap_sig_bdd_131 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_131 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end

/// ap_sig_bdd_27 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_27 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end

/// ap_sig_bdd_271 assign process. ///
always @ (tmp_34_fu_883_p1)
begin
    ap_sig_bdd_271 = (~(tmp_34_fu_883_p1 == ap_const_lv5_12) & ~(tmp_34_fu_883_p1 == ap_const_lv5_11) & ~(tmp_34_fu_883_p1 == ap_const_lv5_10) & ~(tmp_34_fu_883_p1 == ap_const_lv5_F) & ~(tmp_34_fu_883_p1 == ap_const_lv5_E) & ~(tmp_34_fu_883_p1 == ap_const_lv5_D) & ~(tmp_34_fu_883_p1 == ap_const_lv5_C) & ~(tmp_34_fu_883_p1 == ap_const_lv5_B) & ~(tmp_34_fu_883_p1 == ap_const_lv5_A) & ~(tmp_34_fu_883_p1 == ap_const_lv5_9) & ~(tmp_34_fu_883_p1 == ap_const_lv5_8) & ~(tmp_34_fu_883_p1 == ap_const_lv5_7) & ~(tmp_34_fu_883_p1 == ap_const_lv5_6) & ~(tmp_34_fu_883_p1 == ap_const_lv5_5) & ~(tmp_34_fu_883_p1 == ap_const_lv5_4) & ~(tmp_34_fu_883_p1 == ap_const_lv5_3) & ~(tmp_34_fu_883_p1 == ap_const_lv5_2) & ~(tmp_34_fu_883_p1 == ap_const_lv5_1) & ~(tmp_34_fu_883_p1 == ap_const_lv5_0));
end

/// ap_sig_bdd_292 assign process. ///
always @ (matchs_0_V_empty_n or matchs_1_V_empty_n or matchs_2_V_empty_n or matchs_3_V_empty_n or matchs_4_V_empty_n or matchs_5_V_empty_n or matchs_6_V_empty_n or matchs_7_V_empty_n or matchs_8_V_empty_n or matchs_9_V_empty_n or matchs_10_V_empty_n or matchs_11_V_empty_n or matchs_12_V_empty_n or matchs_13_V_empty_n or matchs_14_V_empty_n or matchs_15_V_empty_n or matchs_16_V_empty_n or matchs_17_V_empty_n or matchs_18_V_empty_n or matchs_19_V_empty_n or tmp_34_fu_883_p1 or tmp_phi_fu_553_p40)
begin
    ap_sig_bdd_292 = (((matchs_18_V_empty_n == ap_const_logic_0) & (tmp_34_fu_883_p1 == ap_const_lv5_12) & ~(tmp_phi_fu_553_p40 == ap_const_lv1_0)) | (~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (matchs_17_V_empty_n == ap_const_logic_0) & (tmp_34_fu_883_p1 == ap_const_lv5_11)) | (~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (matchs_16_V_empty_n == ap_const_logic_0) & (tmp_34_fu_883_p1 == ap_const_lv5_10)) | (~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (matchs_15_V_empty_n == ap_const_logic_0) & (tmp_34_fu_883_p1 == ap_const_lv5_F)) | (~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (matchs_14_V_empty_n == ap_const_logic_0) & (tmp_34_fu_883_p1 == ap_const_lv5_E)) | (~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (matchs_13_V_empty_n == ap_const_logic_0) & (tmp_34_fu_883_p1 == ap_const_lv5_D)) | (~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (matchs_12_V_empty_n == ap_const_logic_0) & (tmp_34_fu_883_p1 == ap_const_lv5_C)) | (~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (matchs_11_V_empty_n == ap_const_logic_0) & (tmp_34_fu_883_p1 == ap_const_lv5_B)) | (~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (matchs_10_V_empty_n == ap_const_logic_0) & (tmp_34_fu_883_p1 == ap_const_lv5_A)) | (~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (matchs_9_V_empty_n == ap_const_logic_0) & (tmp_34_fu_883_p1 == ap_const_lv5_9)) | (~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (matchs_8_V_empty_n == ap_const_logic_0) & (tmp_34_fu_883_p1 == ap_const_lv5_8)) | (~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (matchs_7_V_empty_n == ap_const_logic_0) & (tmp_34_fu_883_p1 == ap_const_lv5_7)) | (~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (matchs_6_V_empty_n == ap_const_logic_0) & (tmp_34_fu_883_p1 == ap_const_lv5_6)) | (~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (matchs_5_V_empty_n == ap_const_logic_0) & (tmp_34_fu_883_p1 == ap_const_lv5_5)) | (~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (matchs_4_V_empty_n == ap_const_logic_0) & (tmp_34_fu_883_p1 == ap_const_lv5_4)) | (~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (matchs_3_V_empty_n == ap_const_logic_0) & (tmp_34_fu_883_p1 == ap_const_lv5_3)) | (~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (matchs_2_V_empty_n == ap_const_logic_0) & (tmp_34_fu_883_p1 == ap_const_lv5_2)) | (~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (matchs_1_V_empty_n == ap_const_logic_0) & (tmp_34_fu_883_p1 == ap_const_lv5_1)) | (~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (matchs_0_V_empty_n == ap_const_logic_0) & (tmp_34_fu_883_p1 == ap_const_lv5_0)) | (~(tmp_phi_fu_553_p40 == ap_const_lv1_0) & (matchs_19_V_empty_n == ap_const_logic_0) & ~(tmp_34_fu_883_p1 == ap_const_lv5_12) & ~(tmp_34_fu_883_p1 == ap_const_lv5_11) & ~(tmp_34_fu_883_p1 == ap_const_lv5_10) & ~(tmp_34_fu_883_p1 == ap_const_lv5_F) & ~(tmp_34_fu_883_p1 == ap_const_lv5_E) & ~(tmp_34_fu_883_p1 == ap_const_lv5_D) & ~(tmp_34_fu_883_p1 == ap_const_lv5_C) & ~(tmp_34_fu_883_p1 == ap_const_lv5_B) & ~(tmp_34_fu_883_p1 == ap_const_lv5_A) & ~(tmp_34_fu_883_p1 == ap_const_lv5_9) & ~(tmp_34_fu_883_p1 == ap_const_lv5_8) & ~(tmp_34_fu_883_p1 == ap_const_lv5_7) & ~(tmp_34_fu_883_p1 == ap_const_lv5_6) & ~(tmp_34_fu_883_p1 == ap_const_lv5_5) & ~(tmp_34_fu_883_p1 == ap_const_lv5_4) & ~(tmp_34_fu_883_p1 == ap_const_lv5_3) & ~(tmp_34_fu_883_p1 == ap_const_lv5_2) & ~(tmp_34_fu_883_p1 == ap_const_lv5_1) & ~(tmp_34_fu_883_p1 == ap_const_lv5_0)));
end

/// ap_sig_bdd_301 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_301 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4]);
end

/// ap_sig_bdd_402 assign process. ///
always @ (tmp_34_reg_1004)
begin
    ap_sig_bdd_402 = (~(ap_const_lv5_12 == tmp_34_reg_1004) & ~(ap_const_lv5_11 == tmp_34_reg_1004) & ~(ap_const_lv5_10 == tmp_34_reg_1004) & ~(ap_const_lv5_F == tmp_34_reg_1004) & ~(ap_const_lv5_E == tmp_34_reg_1004) & ~(ap_const_lv5_D == tmp_34_reg_1004) & ~(ap_const_lv5_C == tmp_34_reg_1004) & ~(ap_const_lv5_B == tmp_34_reg_1004) & ~(ap_const_lv5_A == tmp_34_reg_1004) & ~(ap_const_lv5_9 == tmp_34_reg_1004) & ~(ap_const_lv5_8 == tmp_34_reg_1004) & ~(ap_const_lv5_7 == tmp_34_reg_1004) & ~(ap_const_lv5_6 == tmp_34_reg_1004) & ~(ap_const_lv5_5 == tmp_34_reg_1004) & ~(ap_const_lv5_4 == tmp_34_reg_1004) & ~(ap_const_lv5_3 == tmp_34_reg_1004) & ~(ap_const_lv5_2 == tmp_34_reg_1004) & ~(ap_const_lv5_1 == tmp_34_reg_1004) & ~(ap_const_lv5_0 == tmp_34_reg_1004));
end

/// ap_sig_bdd_423 assign process. ///
always @ (matchs_0_V_empty_n or matchs_1_V_empty_n or matchs_2_V_empty_n or matchs_3_V_empty_n or matchs_4_V_empty_n or matchs_5_V_empty_n or matchs_6_V_empty_n or matchs_7_V_empty_n or matchs_8_V_empty_n or matchs_9_V_empty_n or matchs_10_V_empty_n or matchs_11_V_empty_n or matchs_12_V_empty_n or matchs_13_V_empty_n or matchs_14_V_empty_n or matchs_15_V_empty_n or matchs_16_V_empty_n or matchs_17_V_empty_n or matchs_18_V_empty_n or matchs_19_V_empty_n or tmp_34_reg_1004 or exitcond_i_reg_1012)
begin
    ap_sig_bdd_423 = (((matchs_18_V_empty_n == ap_const_logic_0) & (ap_const_lv5_12 == tmp_34_reg_1004) & (ap_const_lv1_0 == exitcond_i_reg_1012)) | ((matchs_17_V_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_11 == tmp_34_reg_1004)) | ((matchs_16_V_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_10 == tmp_34_reg_1004)) | ((matchs_15_V_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_F == tmp_34_reg_1004)) | ((matchs_14_V_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_E == tmp_34_reg_1004)) | ((matchs_13_V_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_D == tmp_34_reg_1004)) | ((matchs_12_V_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_C == tmp_34_reg_1004)) | ((matchs_11_V_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_B == tmp_34_reg_1004)) | ((matchs_10_V_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_A == tmp_34_reg_1004)) | ((matchs_9_V_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_9 == tmp_34_reg_1004)) | ((matchs_8_V_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_8 == tmp_34_reg_1004)) | ((matchs_7_V_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_7 == tmp_34_reg_1004)) | ((matchs_6_V_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_6 == tmp_34_reg_1004)) | ((matchs_5_V_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_5 == tmp_34_reg_1004)) | ((matchs_4_V_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_4 == tmp_34_reg_1004)) | ((matchs_3_V_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_3 == tmp_34_reg_1004)) | ((matchs_2_V_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_2 == tmp_34_reg_1004)) | ((matchs_1_V_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_1 == tmp_34_reg_1004)) | ((matchs_0_V_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_i_reg_1012) & (ap_const_lv5_0 == tmp_34_reg_1004)) | ((matchs_19_V_empty_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_i_reg_1012) & ~(ap_const_lv5_12 == tmp_34_reg_1004) & ~(ap_const_lv5_11 == tmp_34_reg_1004) & ~(ap_const_lv5_10 == tmp_34_reg_1004) & ~(ap_const_lv5_F == tmp_34_reg_1004) & ~(ap_const_lv5_E == tmp_34_reg_1004) & ~(ap_const_lv5_D == tmp_34_reg_1004) & ~(ap_const_lv5_C == tmp_34_reg_1004) & ~(ap_const_lv5_B == tmp_34_reg_1004) & ~(ap_const_lv5_A == tmp_34_reg_1004) & ~(ap_const_lv5_9 == tmp_34_reg_1004) & ~(ap_const_lv5_8 == tmp_34_reg_1004) & ~(ap_const_lv5_7 == tmp_34_reg_1004) & ~(ap_const_lv5_6 == tmp_34_reg_1004) & ~(ap_const_lv5_5 == tmp_34_reg_1004) & ~(ap_const_lv5_4 == tmp_34_reg_1004) & ~(ap_const_lv5_3 == tmp_34_reg_1004) & ~(ap_const_lv5_2 == tmp_34_reg_1004) & ~(ap_const_lv5_1 == tmp_34_reg_1004) & ~(ap_const_lv5_0 == tmp_34_reg_1004)));
end

/// ap_sig_bdd_535 assign process. ///
always @ (ap_start or ap_done_reg)
begin
    ap_sig_bdd_535 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end

/// ap_sig_bdd_547 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_547 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end

/// ap_sig_bdd_571 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_571 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5]);
end

/// ap_sig_bdd_584 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_584 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_6]);
end

/// ap_sig_bdd_591 assign process. ///
always @ (peArr_blockMatchs_V_full_n or exitcond_reg_1034)
begin
    ap_sig_bdd_591 = ((peArr_blockMatchs_V_full_n == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_reg_1034));
end

/// ap_sig_bdd_694 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_694 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end

/// ap_sig_bdd_725 assign process. ///
always @ (ap_sig_bdd_423 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2)
begin
    ap_sig_bdd_725 = ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(ap_sig_bdd_423 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)));
end

/// ap_sig_bdd_728 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_728 = (~(ap_const_lv5_12 == tmp_34_reg_1004) & ~(ap_const_lv5_11 == tmp_34_reg_1004) & ~(ap_const_lv5_10 == tmp_34_reg_1004) & ~(ap_const_lv5_F == tmp_34_reg_1004) & ~(ap_const_lv5_E == tmp_34_reg_1004) & ~(ap_const_lv5_D == tmp_34_reg_1004) & ~(ap_const_lv5_C == tmp_34_reg_1004) & ~(ap_const_lv5_B == tmp_34_reg_1004) & ~(ap_const_lv5_A == tmp_34_reg_1004) & ~(ap_const_lv5_9 == tmp_34_reg_1004) & ~(ap_const_lv5_8 == tmp_34_reg_1004) & ~(ap_const_lv5_7 == tmp_34_reg_1004) & ~(ap_const_lv5_6 == tmp_34_reg_1004) & ~(ap_const_lv5_5 == tmp_34_reg_1004) & ~(ap_const_lv5_4 == tmp_34_reg_1004) & ~(ap_const_lv5_3 == tmp_34_reg_1004) & ~(ap_const_lv5_2 == tmp_34_reg_1004) & ~(ap_const_lv5_1 == tmp_34_reg_1004) & ~(ap_const_lv5_0 == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_731 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_731 = ((ap_const_lv5_12 == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_733 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_733 = ((ap_const_lv5_11 == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_735 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_735 = ((ap_const_lv5_10 == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_737 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_737 = ((ap_const_lv5_F == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_739 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_739 = ((ap_const_lv5_E == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_741 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_741 = ((ap_const_lv5_D == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_743 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_743 = ((ap_const_lv5_C == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_745 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_745 = ((ap_const_lv5_B == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_747 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_747 = ((ap_const_lv5_A == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_749 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_749 = ((ap_const_lv5_9 == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_751 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_751 = ((ap_const_lv5_8 == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_753 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_753 = ((ap_const_lv5_7 == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_755 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_755 = ((ap_const_lv5_6 == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_757 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_757 = ((ap_const_lv5_5 == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_759 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_759 = ((ap_const_lv5_4 == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_761 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_761 = ((ap_const_lv5_3 == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_763 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_763 = ((ap_const_lv5_2 == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_765 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_765 = ((ap_const_lv5_1 == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_767 assign process. ///
always @ (tmp_34_reg_1004 or ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1)
begin
    ap_sig_bdd_767 = ((ap_const_lv5_0 == tmp_34_reg_1004) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_i_reg_1012_pp0_it1));
end

/// ap_sig_bdd_853 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_853 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_7]);
end

/// ap_sig_bdd_859 assign process. ///
always @ (peArr_blockMatchs_V_full_n or tmp_27_fu_973_p2)
begin
    ap_sig_bdd_859 = ((peArr_blockMatchs_V_full_n == ap_const_logic_0) & ~(ap_const_lv1_0 == tmp_27_fu_973_p2));
end
assign exitcond_fu_956_p2 = (l_reg_735 == ap_const_lv3_5? 1'b1: 1'b0);
assign exitcond_i_fu_893_p2 = (i_0_i_phi_fu_665_p4 == ap_const_lv3_4? 1'b1: 1'b0);
assign i_fu_899_p2 = (i_0_i_phi_fu_665_p4 + ap_const_lv3_1);
assign j_1_fu_943_p3 = ((tmp_25_fu_933_p2[0:0]===1'b1)? ap_const_lv8_0: j_2_fu_938_p2);
assign j_2_fu_938_p2 = (j_load_reg_998 + ap_const_lv8_1);
assign l_1_fu_962_p2 = (l_reg_735 + ap_const_lv3_1);
assign matchBuf_addr_gep_fu_524_p3 = ap_const_lv64_0;
assign peOver_cnt_1_fu_922_p2 = (peOver_cnt_fu_224 + ap_const_lv8_1);
assign tmp_22_fu_910_p2 = (getPeMatchFlag_reg_718 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_24_fu_905_p1 = i_fu_899_p2;
assign tmp_25_fu_933_p2 = ($signed(j_load_reg_998) > $signed(8'b10011)? 1'b1: 1'b0);
assign tmp_26_fu_916_p2 = (getPeMatchFlag_reg_718 == ap_const_lv2_1? 1'b1: 1'b0);
assign tmp_27_fu_973_p2 = ($signed(peOver_cnt_fu_224) > $signed(8'b10011)? 1'b1: 1'b0);
assign tmp_29_fu_968_p1 = l_reg_735;
assign tmp_34_fu_883_p1 = j_fu_228[4:0];
assign tmp_s_fu_887_p2 = (tmp_55_reg_615 == ap_const_lv32_FFFFFFFF? 1'b1: 1'b0);
always @ (posedge ap_clk)
begin
    matchBuf_addr_reg_993[2:0] <= 3'b000;
end



endmodule //sw_pe_array_receive_match