sw_pe_array_proc_element_query_mem_V.v

// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
// 
// ==============================================================


`include "nlb_cfg_pkg.vh"

module sw_pe_array_proc_element_query_mem_V(
    reset,
    clk,
    address0,
    ce0,
    we0,
    d0,
    q0);

parameter DataWidth = 32'd4;
parameter AddressRange = 32'd2048;
parameter AddressWidth = 32'd11;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;



nlb_gram_ssp 
   # (.BUS_SIZE_ADDR(11),
      .BUS_SIZE_DATA(4),
      .GRAM_STYLE(`GRAM_AUTO))
   inst_nlb_gram_ssp
   (
    .clk( clk ),
    .we(we0),
    .addr( address0 ),
    .din( d0 ),
    .dout( q0 ));

endmodule