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If both SAT DMA and VRAM DMA are pending, they will execute one after the other automatically whenever vblank is entered. There is an issue when the CPU does a VRAM write during SAT DMA as the CPU write is executed upon SAT DMA completion and then proceeds to VRAM DMA. The correct behaviour is that CPU write occurs after the VRAM DMA.
I have attached a small PCE demo that shows a sprite glitch on real hardware but not in Mednafen. I can only assume that this program was only ever tested on Mednafen or another emulator making the same assumption. pce_test_sprite_glitch.zip
The text was updated successfully, but these errors were encountered:
If both SAT DMA and VRAM DMA are pending, they will execute one after the other automatically whenever vblank is entered. There is an issue when the CPU does a VRAM write during SAT DMA as the CPU write is executed upon SAT DMA completion and then proceeds to VRAM DMA. The correct behaviour is that CPU write occurs after the VRAM DMA.
I have attached a small PCE demo that shows a sprite glitch on real hardware but not in Mednafen. I can only assume that this program was only ever tested on Mednafen or another emulator making the same assumption.
pce_test_sprite_glitch.zip
The text was updated successfully, but these errors were encountered: