From 51b091a70ebc469a922ac663dad4cac8fb41f785 Mon Sep 17 00:00:00 2001 From: Nathanael Huffman Date: Tue, 19 Nov 2024 10:38:14 -0600 Subject: [PATCH] Initial structure for cosmo hotplug fpga --- hdl/projects/cosmo_hp/BUCK | 17 +++ hdl/projects/cosmo_hp/cosmo_hp.pcf | 151 +++++++++++++++++++++ hdl/projects/cosmo_hp/cosmo_hp_top.vhd | 176 +++++++++++++++++++++++++ tools/yosys.bzl | 6 + 4 files changed, 350 insertions(+) create mode 100644 hdl/projects/cosmo_hp/BUCK create mode 100644 hdl/projects/cosmo_hp/cosmo_hp.pcf create mode 100644 hdl/projects/cosmo_hp/cosmo_hp_top.vhd diff --git a/hdl/projects/cosmo_hp/BUCK b/hdl/projects/cosmo_hp/BUCK new file mode 100644 index 00000000..58b553a6 --- /dev/null +++ b/hdl/projects/cosmo_hp/BUCK @@ -0,0 +1,17 @@ +load("//tools:hdl.bzl", "vhdl_unit") +load("//tools:yosys.bzl", "ice40_bitstream") + +vhdl_unit( + name = "cosmo_hp_top", + srcs = glob(["*.vhd"]), + standard = "2008", +) + +ice40_bitstream( + name="cosmo_hp_bitstream", + top_entity_name="cosmo_hp_top", + top= ":cosmo_hp_top", + family="hx8k", + package="ct256", + pinmap="cosmo_hp.pcf" +) \ No newline at end of file diff --git a/hdl/projects/cosmo_hp/cosmo_hp.pcf b/hdl/projects/cosmo_hp/cosmo_hp.pcf new file mode 100644 index 00000000..97ad6194 --- /dev/null +++ b/hdl/projects/cosmo_hp/cosmo_hp.pcf @@ -0,0 +1,151 @@ +set_io --warn-no-port cema_to_fpga2_alert_l F13 +set_io --warn-no-port cema_to_fpga2_ifdet_l F12 +set_io --warn-no-port cema_to_fpga2_pg_l C16 +set_io --warn-no-port cema_to_fpga2_prsnt_l G12 +set_io --warn-no-port cema_to_fpga2_pwrflt_l D16 +set_io --warn-no-port cema_to_fpga2_sharkfin_present F11 +set_io --warn-no-port cemb_to_fpga2_alert_l H16 +set_io --warn-no-port cemb_to_fpga2_ifdet_l J12 +set_io --warn-no-port cemb_to_fpga2_pg_l H11 +set_io --warn-no-port cemb_to_fpga2_prsnt_l K16 +set_io --warn-no-port cemb_to_fpga2_pwrflt_l K15 +set_io --warn-no-port cemb_to_fpga2_sharkfin_present J16 +set_io --warn-no-port cemc_to_fpga2_alert_l N16 +set_io --warn-no-port cemc_to_fpga2_ifdet_l P14 +set_io --warn-no-port cemc_to_fpga2_pg_l L12 +set_io --warn-no-port cemc_to_fpga2_prsnt_l R14 +set_io --warn-no-port cemc_to_fpga2_pwrflt_l P15 +set_io --warn-no-port cemc_to_fpga2_sharkfin_present M13 +set_io --warn-no-port cemd_to_fpga2_alert_l B4 +set_io --warn-no-port cemd_to_fpga2_ifdet_l A6 +set_io --warn-no-port cemd_to_fpga2_pg_l E6 +set_io --warn-no-port cemd_to_fpga2_prsnt_l D7 +set_io --warn-no-port cemd_to_fpga2_pwrflt_l B6 +set_io --warn-no-port cemd_to_fpga2_sharkfin_present A5 +set_io --warn-no-port ceme_to_fpga2_alert_l A11 +set_io --warn-no-port ceme_to_fpga2_ifdet_l B12 +set_io --warn-no-port ceme_to_fpga2_pg_l A10 +set_io --warn-no-port ceme_to_fpga2_prsnt_l D11 +set_io --warn-no-port ceme_to_fpga2_pwrflt_l E10 +set_io --warn-no-port ceme_to_fpga2_sharkfin_present B11 +set_io --warn-no-port cemf_to_fpga2_alert_l E16 +set_io --warn-no-port cemf_to_fpga2_ifdet_l G10 +set_io --warn-no-port cemf_to_fpga2_pg_l G14 +set_io --warn-no-port cemf_to_fpga2_prsnt_l H12 +set_io --warn-no-port cemf_to_fpga2_pwrflt_l G16 +set_io --warn-no-port cemf_to_fpga2_sharkfin_present G11 +set_io --warn-no-port cemg_to_fpga2_alert_l K14 +set_io --warn-no-port cemg_to_fpga2_ifdet_l J10 +set_io --warn-no-port cemg_to_fpga2_pg_l K13 +set_io --warn-no-port cemg_to_fpga2_prsnt_l K12 +set_io --warn-no-port cemg_to_fpga2_pwrflt_l L14 +set_io --warn-no-port cemg_to_fpga2_sharkfin_present J11 +set_io --warn-no-port cemh_to_fpga2_alert_l C3 +set_io --warn-no-port cemh_to_fpga2_ifdet_l C4 +set_io --warn-no-port cemh_to_fpga2_pg_l D3 +set_io --warn-no-port cemh_to_fpga2_prsnt_l C5 +set_io --warn-no-port cemh_to_fpga2_pwrflt_l D5 +set_io --warn-no-port cemh_to_fpga2_sharkfin_present D4 +set_io --warn-no-port cemi_to_fpga2_alert_l C7 +set_io --warn-no-port cemi_to_fpga2_ifdet_l A9 +set_io --warn-no-port cemi_to_fpga2_pg_l A7 +set_io --warn-no-port cemi_to_fpga2_prsnt_l D9 +set_io --warn-no-port cemi_to_fpga2_pwrflt_l C9 +set_io --warn-no-port cemi_to_fpga2_sharkfin_present D8 +set_io --warn-no-port cemj_to_fpga2_alert_l A15 +set_io --warn-no-port cemj_to_fpga2_ifdet_l B14 +set_io --warn-no-port cemj_to_fpga2_pg_l A16 +set_io --warn-no-port cemj_to_fpga2_prsnt_l D13 +set_io --warn-no-port cemj_to_fpga2_pwrflt_l C14 +set_io --warn-no-port cemj_to_fpga2_sharkfin_present E11 +set_io --warn-no-port clk_50mhz_fpga2 F7 +set_io --warn-no-port clk_buff_cemabcd_to_fpga2_los_l K9 +set_io --warn-no-port clk_buff_cemefg_to_fpga2_los_l N12 +set_io --warn-no-port clk_buff_cemhij_to_fpga2_los_l T10 +set_io --warn-no-port fpga1_to_fpga2_io[0] D1 +set_io --warn-no-port fpga1_to_fpga2_io[1] G4 +set_io --warn-no-port fpga1_to_fpga2_io[2] E3 +set_io --warn-no-port fpga1_to_fpga2_io[3] H5 +set_io --warn-no-port fpga1_to_fpga2_io[4] E2 +set_io --warn-no-port fpga1_to_fpga2_io[5] G3 +set_io --warn-no-port fpga2_spare_v3p3[0] E4 +set_io --warn-no-port fpga2_spare_v3p3[1] B2 +set_io --warn-no-port fpga2_spare_v3p3[2] F5 +set_io --warn-no-port fpga2_spare_v3p3[3] B1 +set_io --warn-no-port fpga2_spare_v3p3[4] C1 +set_io --warn-no-port fpga2_spare_v3p3[5] C2 +set_io --warn-no-port fpga2_spare_v3p3[6] F4 +set_io --warn-no-port fpga2_spare_v3p3[7] D2 +set_io --warn-no-port fpga2_status_led B9 +set_io --warn-no-port fpga2_to_cema_attnled R4 +set_io --warn-no-port fpga2_to_cema_perst_l F14 +set_io --warn-no-port fpga2_to_cema_pwren E14 +set_io --warn-no-port fpga2_to_cemb_attnled T3 +set_io --warn-no-port fpga2_to_cemb_perst_l J14 +set_io --warn-no-port fpga2_to_cemb_pwren H13 +set_io --warn-no-port fpga2_to_cemc_attnled R3 +set_io --warn-no-port fpga2_to_cemc_perst_l R15 +set_io --warn-no-port fpga2_to_cemc_pwren M14 +set_io --warn-no-port fpga2_to_cemd_attnled T2 +set_io --warn-no-port fpga2_to_cemd_perst_l C6 +set_io --warn-no-port fpga2_to_cemd_pwren B5 +set_io --warn-no-port fpga2_to_ceme_attnled R2 +set_io --warn-no-port fpga2_to_ceme_perst_l C11 +set_io --warn-no-port fpga2_to_ceme_pwren C10 +set_io --warn-no-port fpga2_to_cemf_attnled R5 +set_io --warn-no-port fpga2_to_cemf_perst_l G15 +set_io --warn-no-port fpga2_to_cemf_pwren F15 +set_io --warn-no-port fpga2_to_cemg_attnled P4 +set_io --warn-no-port fpga2_to_cemg_perst_l M16 +set_io --warn-no-port fpga2_to_cemg_pwren L16 +set_io --warn-no-port fpga2_to_cemh_attnled P5 +set_io --warn-no-port fpga2_to_cemh_perst_l A1 +set_io --warn-no-port fpga2_to_cemh_pwren E5 +set_io --warn-no-port fpga2_to_cemi_attnled N5 +set_io --warn-no-port fpga2_to_cemi_perst_l E9 +set_io --warn-no-port fpga2_to_cemi_pwren B8 +set_io --warn-no-port fpga2_to_cemj_attnled M7 +set_io --warn-no-port fpga2_to_cemj_perst_l B15 +set_io --warn-no-port fpga2_to_cemj_pwren C13 +set_io --warn-no-port fpga2_to_clk_buff_cema_oe_l N9 +set_io --warn-no-port fpga2_to_clk_buff_cemb_oe_l T9 +set_io --warn-no-port fpga2_to_clk_buff_cemc_oe_l M9 +set_io --warn-no-port fpga2_to_clk_buff_cemd_oe_l R9 +set_io --warn-no-port fpga2_to_clk_buff_ceme_oe_l T15 +set_io --warn-no-port fpga2_to_clk_buff_cemf_oe_l T14 +set_io --warn-no-port fpga2_to_clk_buff_cemg_oe_l M11 +set_io --warn-no-port fpga2_to_clk_buff_cemh_oe_l R10 +set_io --warn-no-port fpga2_to_clk_buff_cemi_oe_l L10 +set_io --warn-no-port fpga2_to_clk_buff_cemj_oe_l P10 +set_io --warn-no-port fpga2_to_clk_buff_mcio_oe_l T13 +set_io --warn-no-port fpga2_to_clk_buff_ufl_oe_l N10 +set_io --warn-no-port fpga2_to_i2c_mux4_sel[0] K1 +set_io --warn-no-port fpga2_to_i2c_mux4_sel[1] J1 +set_io --warn-no-port fpga2_to_i2c_mux5_sel[0] L1 +set_io --warn-no-port fpga2_to_i2c_mux5_sel[1] M1 +set_io --warn-no-port fpga2_to_i2c_mux6_sel[0] M3 +set_io --warn-no-port fpga2_to_i2c_mux6_sel[1] L5 +set_io --warn-no-port fpga2_to_i2c_mux7_sel[0] H2 +set_io --warn-no-port fpga2_to_i2c_mux7_sel[1] G2 +set_io --warn-no-port fpga2_to_i2c_mux8_sel[0] F1 +set_io --warn-no-port fpga2_to_i2c_mux8_sel[1] G1 +set_io --warn-no-port fpga2_to_mcio_perst_l J3 +set_io --warn-no-port fpga2_to_mcio_prpe H1 +set_io --warn-no-port fpga2_to_sp_int_l[0] M4 +set_io --warn-no-port fpga2_to_sp_int_l[1] P2 +set_io --warn-no-port fpga2_to_sp_int_l[2] M5 +set_io --warn-no-port fpga2_to_v12_mcio_a0hp_hsc_en F2 +set_io --warn-no-port i2c_sp5_to_fpga2_scl M2 +set_io --warn-no-port i2c_sp5_to_fpga2_sda L7 +set_io --warn-no-port i2c_sp5_to_fpga2_xltr_en N2 +set_io --warn-no-port smbus_sp_to_fpga2_smclk T7 +set_io --warn-no-port smbus_sp_to_fpga2_smdat T8 +set_io --warn-no-port sp5_to_fpga_genint_3v3_l K5 +set_io --warn-no-port sp_to_fpga2_system_reset_l N6 +set_io --warn-no-port spi_fpga2_to_sp_mux_dat P12 +set_io --warn-no-port spi_sp_mux_to_fpga2_cs_l R12 +set_io --warn-no-port spi_sp_mux_to_fpga2_dat P11 +set_io --warn-no-port spi_sp_mux_to_fpga2_sck R11 +set_io --warn-no-port uart_fpga2_to_sp_dat N4 +set_io --warn-no-port uart_sp_to_fpga2_dat R1 +set_io --warn-no-port v12_mcio_a0hp_pg H6 diff --git a/hdl/projects/cosmo_hp/cosmo_hp_top.vhd b/hdl/projects/cosmo_hp/cosmo_hp_top.vhd new file mode 100644 index 00000000..a579fe8d --- /dev/null +++ b/hdl/projects/cosmo_hp/cosmo_hp_top.vhd @@ -0,0 +1,176 @@ +-- This Source Code Form is subject to the terms of the Mozilla Public +-- License, v. 2.0. If a copy of the MPL was not distributed with this +-- file, You can obtain one at https://mozilla.org/MPL/2.0/. +-- +-- Copyright 2024 Oxide Computer Company + +-- Cosmo Front Hot-plug FPGA targeting an ice40 HX8k +-- Pin names snapshot from 20Nov2024 + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.numeric_std_unsigned.all; + +entity cosmo_hp_top is + port ( + clk_50mhz_fpga2: in std_logic; + sp_to_fpga2_system_reset_l: in std_logic; + + -- CEM A + cema_to_fpga2_alert_l : in std_logic; + cema_to_fpga2_ifdet_l : in std_logic; + cema_to_fpga2_pg_l : in std_logic; + cema_to_fpga2_prsnt_l : in std_logic; + cema_to_fpga2_pwrflt_l : in std_logic; + cema_to_fpga2_sharkfin_present : in std_logic; + fpga2_to_cema_attnled: out std_logic; + fpga2_to_cema_perst_l : out std_logic; + fpga2_to_cema_pwren : out std_logic; + -- CEM B + cemb_to_fpga2_alert_l : in std_logic; + cemb_to_fpga2_ifdet_l : in std_logic; + cemb_to_fpga2_pg_l : in std_logic; + cemb_to_fpga2_prsnt_l : in std_logic; + cemb_to_fpga2_pwrflt_l : in std_logic; + cemb_to_fpga2_sharkfin_present : in std_logic; + fpga2_to_cemb_attnled: out std_logic; + fpga2_to_cemb_perst_l : out std_logic; + fpga2_to_cemb_pwren : out std_logic; + -- CEM C + cemc_to_fpga2_alert_l : in std_logic; + cemc_to_fpga2_ifdet_l : in std_logic; + cemc_to_fpga2_pg_l : in std_logic; + cemc_to_fpga2_prsnt_l : in std_logic; + cemc_to_fpga2_pwrflt_l : in std_logic; + cemc_to_fpga2_sharkfin_present : in std_logic; + fpga2_to_cemc_attnled: out std_logic; + fpga2_to_cemc_perst_l : out std_logic; + fpga2_to_cemc_pwren : out std_logic; + -- CEM D + cemd_to_fpga2_alert_l: in std_logic; + cemd_to_fpga2_ifdet_l: in std_logic; + cemd_to_fpga2_pg_l: in std_logic; + cemd_to_fpga2_prsnt_l: in std_logic; + cemd_to_fpga2_pwrflt_l: in std_logic; + cemd_to_fpga2_sharkfin_present: in std_logic; + fpga2_to_cemd_attnled: out std_logic; + fpga2_to_cemd_perst_l: out std_logic; + fpga2_to_cemd_pwren: out std_logic; + -- CEM E + ceme_to_fpga2_alert_l : in std_logic; + ceme_to_fpga2_ifdet_l : in std_logic; + ceme_to_fpga2_pg_l : in std_logic; + ceme_to_fpga2_prsnt_l : in std_logic; + ceme_to_fpga2_pwrflt_l : in std_logic; + ceme_to_fpga2_sharkfin_present : in std_logic; + fpga2_to_ceme_attnled: out std_logic; + fpga2_to_ceme_perst_l : out std_logic; + fpga2_to_ceme_pwren : out std_logic; + -- CEM F + cemf_to_fpga2_alert_l : in std_logic; + cemf_to_fpga2_ifdet_l : in std_logic; + cemf_to_fpga2_pg_l : in std_logic; + cemf_to_fpga2_prsnt_l : in std_logic; + cemf_to_fpga2_pwrflt_l : in std_logic; + cemf_to_fpga2_sharkfin_present : in std_logic; + fpga2_to_cemf_attnled: out std_logic; + fpga2_to_cemf_perst_l : out std_logic; + fpga2_to_cemf_pwren : out std_logic; + -- CEM G + cemg_to_fpga2_alert_l : in std_logic; + cemg_to_fpga2_ifdet_l : in std_logic; + cemg_to_fpga2_pg_l : in std_logic; + cemg_to_fpga2_prsnt_l : in std_logic; + cemg_to_fpga2_pwrflt_l : in std_logic; + cemg_to_fpga2_sharkfin_present : in std_logic; + fpga2_to_cemg_attnled: out std_logic; + fpga2_to_cemg_perst_l : out std_logic; + fpga2_to_cemg_pwren : out std_logic; + -- CEM H + cemh_to_fpga2_alert_l: in std_logic; + cemh_to_fpga2_ifdet_l: in std_logic; + cemh_to_fpga2_pg_l: in std_logic; + cemh_to_fpga2_prsnt_l: in std_logic; + cemh_to_fpga2_pwrflt_l: in std_logic; + cemh_to_fpga2_sharkfin_present: in std_logic; + fpga2_to_cemh_attnled: out std_logic; + fpga2_to_cemh_perst_l: out std_logic; + fpga2_to_cemh_pwren: out std_logic; + -- CEM I + cemi_to_fpga2_alert_l: in std_logic; + cemi_to_fpga2_ifdet_l: in std_logic; + cemi_to_fpga2_pg_l: in std_logic; + cemi_to_fpga2_prsnt_l: in std_logic; + cemi_to_fpga2_pwrflt_l: in std_logic; + cemi_to_fpga2_sharkfin_present: in std_logic; + fpga2_to_cemi_attnled: out std_logic; + fpga2_to_cemi_perst_l: out std_logic; + fpga2_to_cemi_pwren: out std_logic; + -- CEM J + cemj_to_fpga2_alert_l : in std_logic; + cemj_to_fpga2_ifdet_l : in std_logic; + cemj_to_fpga2_pg_l : in std_logic; + cemj_to_fpga2_prsnt_l : in std_logic; + cemj_to_fpga2_pwrflt_l : in std_logic; + cemj_to_fpga2_sharkfin_present : in std_logic; + fpga2_to_cemj_attnled: out std_logic; + fpga2_to_cemj_perst_l : out std_logic; + fpga2_to_cemj_pwren : out std_logic; + -- CLK Buffer I/F + clk_buff_cemabcd_to_fpga2_los_l: in std_logic; + clk_buff_cemefg_to_fpga2_los_l : in std_logic; + clk_buff_cemhij_to_fpga2_los_l : in std_logic; + fpga2_to_clk_buff_cema_oe_l: out std_logic; + fpga2_to_clk_buff_cemb_oe_l: out std_logic; + fpga2_to_clk_buff_cemc_oe_l: out std_logic; + fpga2_to_clk_buff_cemd_oe_l: out std_logic; + fpga2_to_clk_buff_ceme_oe_l : out std_logic; + fpga2_to_clk_buff_cemf_oe_l : out std_logic; + fpga2_to_clk_buff_cemg_oe_l : out std_logic; + fpga2_to_clk_buff_cemh_oe_l : out std_logic; + fpga2_to_clk_buff_cemi_oe_l : out std_logic; + fpga2_to_clk_buff_cemj_oe_l : out std_logic; + fpga2_to_clk_buff_mcio_oe_l : out std_logic; + fpga2_to_clk_buff_ufl_oe_l : out std_logic; + -- MCIO I/F + v12_mcio_a0hp_pg: in std_logic; + fpga2_to_mcio_perst_l: out std_logic; + fpga2_to_mcio_prpe: out std_logic; + fpga2_to_v12_mcio_a0hp_hsc_en: out std_logic; + -- FPGA1 I/F + fpga1_to_fpga2_io: in std_logic_vector(5 downto 0); + -- FPGA misc I/O + fpga2_spare_v3p3: in std_logic_vector(7 downto 0); + fpga2_status_led: out std_logic; + -- SP I/F + fpga2_to_sp_int_l: in std_logic_vector(2 downto 0); -- 3..1 in sch + smbus_sp_to_fpga2_smclk: inout std_logic; + smbus_sp_to_fpga2_smdat: inout std_logic; + spi_fpga2_to_sp_mux_dat: in std_logic; + spi_sp_mux_to_fpga2_cs_l : in std_logic; + spi_sp_mux_to_fpga2_dat : in std_logic; + spi_sp_mux_to_fpga2_sck : in std_logic; + uart_fpga2_to_sp_dat: in std_logic; + uart_sp_to_fpga2_dat: in std_logic; + -- I2C Muxes + fpga2_to_i2c_mux4_sel: in std_logic_vector(1 downto 0); + fpga2_to_i2c_mux5_sel: in std_logic_vector(1 downto 0); + fpga2_to_i2c_mux6_sel: in std_logic_vector(1 downto 0); + fpga2_to_i2c_mux7_sel: in std_logic_vector(1 downto 0); + fpga2_to_i2c_mux8_sel: in std_logic_vector(1 downto 0); + -- SP5 I/F + i2c_sp5_to_fpga2_scl: inout std_logic; + i2c_sp5_to_fpga2_sda: inout std_logic; + i2c_sp5_to_fpga2_xltr_en: in std_logic; + sp5_to_fpga_genint_3v3_l: in std_logic + + ); +end entity; + +architecture rtl of cosmo_hp_top is + +begin + +end rtl; \ No newline at end of file diff --git a/tools/yosys.bzl b/tools/yosys.bzl index 7dc39952..ad7da3ee 100644 --- a/tools/yosys.bzl +++ b/tools/yosys.bzl @@ -73,6 +73,7 @@ def ice40_nextpnr(ctx, yoys_providers): asc = ctx.actions.declare_output("{}.asc".format(ctx.attrs.name)) cmd = cmd_args() cmd.add(ctx.attrs._nextpnr_ice40[RunInfo]) + cmd.add(next_pnr_family_flags(ctx.attrs.family)) cmd.add("--package", ctx.attrs.package) cmd.add("--pcf", ctx.attrs.pinmap) cmd.add("--json", yosys_json) @@ -83,6 +84,10 @@ def ice40_nextpnr(ctx, yoys_providers): providers.append(DefaultInfo(default_output=asc)) return providers +# naive implemenation of turning family into nextpnr flags +def next_pnr_family_flags(family): + return "--{}".format(family) + def icepack(ctx, next_pnr_providers): providers = [] @@ -104,6 +109,7 @@ ice40_bitstream = rule( attrs={ "top_entity_name": attrs.string(), "top": attrs.dep(doc="Expected top HDL unit"), + "family": attrs.string(doc="FPGA family"), "package": attrs.string(doc="Supported FPGA package"), "pinmap": attrs.source(doc="Pin constraints file *.pcf"), "_yosys_gen": attrs.exec_dep(