From 7b171455ca620d75198091f2997d7274124029fb Mon Sep 17 00:00:00 2001 From: Nathanael Huffman Date: Fri, 11 Oct 2024 15:04:36 -0500 Subject: [PATCH 1/5] GHA and colo runner --- .github/filters.yml | 20 ++++++ .github/workflows/build.yml | 0 .github/workflows/simulation.yml | 61 +++++++++++++++++ .gitignore | 6 ++ BUILD.vars.gha | 14 ++++ hdl/ip/vhd/ip_tests/BUCK | 15 ----- hdl/ip/vhd/memories/BUCK | 1 + .../qspi_controller/sims/qspi_vc_tb.vhd | 65 ------------------- .../qspi_controller/sims/qspi_vc_th.vhd | 43 ------------ tools/vunit-sims.bxl | 29 +++++++++ 10 files changed, 131 insertions(+), 123 deletions(-) create mode 100644 .github/filters.yml create mode 100644 .github/workflows/build.yml create mode 100644 .github/workflows/simulation.yml create mode 100644 BUILD.vars.gha delete mode 100644 hdl/ip/vhd/ip_tests/BUCK delete mode 100644 hdl/ip/vhd/vunit_components/qspi_controller/sims/qspi_vc_tb.vhd delete mode 100644 hdl/ip/vhd/vunit_components/qspi_controller/sims/qspi_vc_th.vhd create mode 100644 tools/vunit-sims.bxl diff --git a/.github/filters.yml b/.github/filters.yml new file mode 100644 index 00000000..ee0eaa37 --- /dev/null +++ b/.github/filters.yml @@ -0,0 +1,20 @@ +cobble: + - 'tools/site_cobble/**/*' + - 'vnd/**/*' + - 'hdl/ip/bsv/**/*' + - 'hdl/projects/ecp5_evn/**/*' + - 'hdl/projects/gimlet/**/*' + - 'hdl/projects/icestick/**/*' + - 'hdl/projects/ignitionlet/**/*' + - 'hdl/projects/psc/**/*' + - 'hdl/projects/sidecar/**/*' + - 'hdl/projects/ulx3s/**/*' + +buck2: + - 'vnd/xpm/**/*' + - 'prelude/**/*' + - 'toolchains/**/*' + - 'hdl/ip/toolchains/**/*' + - 'tools/**/*' + - 'hdl/ip/vhd/**/*' + - 'hdl/projects/grapefruit/**/*' \ No newline at end of file diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml new file mode 100644 index 00000000..e69de29b diff --git a/.github/workflows/simulation.yml b/.github/workflows/simulation.yml new file mode 100644 index 00000000..0fc06c99 --- /dev/null +++ b/.github/workflows/simulation.yml @@ -0,0 +1,61 @@ +name: simulation +run-name: ${{ github.actor }} running HDL simulations +on: + [push] +jobs: + changes: + runs-on: self-hosted + permissions: + pull-requests: read + outputs: + cobble: ${{ steps.filter.outputs.cobble }} + buck2: ${{ steps.filter.outputs.buck2 }} + steps: + - uses: actions/checkout@v4 + with: + submodules: 'true' + - uses: dorny/paths-filter@v3 + id: filter + with: + filters: .github/filters.yml + + vunit-sim: + needs: changes + if: ${{ needs.changes.outputs.buck2 == 'true' }} + runs-on: self-hosted + steps: + - run: echo "The name of your branch is ${{ github.ref }} and your repository is ${{ github.repository }}." + - name: Check out repository code + uses: actions/checkout@v4 + with: + submodules: 'true' + - name: Update pip reqs + run : python3 -m pip install --upgrade -r tools/requirements.txt --break-system-packages + - name: Run VUnit tests + run: buck2 bxl //tools/vunit-sims.bxl:vunit_sim_gen | while IFS= read -r line; do eval "$line" ; done + + bsv-sim: + needs: changes + if: ${{ needs.changes.outputs.cobble == 'true' }} + runs-on: self-hosted + steps: + - run: echo "The name of your branch is ${{ github.ref }} and your repository is ${{ github.repository }}." + - name: Check out repository code + uses: actions/checkout@v4 + with: + submodules: 'true' + fetch-depth: 0 + - name: Update pip reqs + run : python3 -m pip install --upgrade -r tools/requirements.txt --break-system-packages + - name: Env setup + run: cp BUILD.vars.gha BUILD.vars && echo "/opt/bsc-2022.01/bin" >> "$GITHUB_PATH" + - name: Restore build-dir + run: if [ -d /tmp/cobble_build_bkup ]; then cp -R /tmp/cobble_build_bkup ./build; else mkdir ./build; fi + - name: cobble init + run: ../vnd/cobble/cobble init .. --reinit + working-directory: ./build + - name: Run BSIM tests + run: ./cobble bluesim_test "//.*SchmittRegTest.*" + working-directory: ./build + - name: backup build-dir + run: cp -R ./build /tmp/cobble_build_bkup \ No newline at end of file diff --git a/.gitignore b/.gitignore index 67b1051d..783f68f2 100644 --- a/.gitignore +++ b/.gitignore @@ -37,5 +37,11 @@ vivado*.log # Yep, even ignore Vivado core dump logs! *.log +# VUnit test results +**/*.xml + # DrawIO cruft **/*.svg.bkp + +# cobble local env +BUILD.vars \ No newline at end of file diff --git a/BUILD.vars.gha b/BUILD.vars.gha new file mode 100644 index 00000000..d9e6ab6b --- /dev/null +++ b/BUILD.vars.gha @@ -0,0 +1,14 @@ +[bluespec] +prefix = "/opt/bsc-2022.01" +bin = "/opt/bsc-2022.01/bin/bsc" +libdir = "/opt/bsc-2022.01/lib/" + +[yosys] +bin = "/opt/oss-cad-suite-20240513/bin/yosys" +libdir = "/opt/oss-cad-suite-20240513/share/yosys" + +[nextpnr] +ecp5 = "/opt/oss-cad-suite-20240513/bin/nextpnr-ecp5" +ecp5_pack = "/opt/oss-cad-suite-20240513/bin/ecppack" +ice40 = "/opt/oss-cad-suite-20240513/bin/nextpnr-ice40" +ice40_pack = "/opt/oss-cad-suite-20240513/bin/icepack" diff --git a/hdl/ip/vhd/ip_tests/BUCK b/hdl/ip/vhd/ip_tests/BUCK deleted file mode 100644 index 8537ffdd..00000000 --- a/hdl/ip/vhd/ip_tests/BUCK +++ /dev/null @@ -1,15 +0,0 @@ -load("//tools:hdl.bzl", "vhdl_unit") - -vhdl_unit( - name = "ip_regression_tb", - is_tb = True, - srcs = [], - deps = [ - "//hdl/ip/vhd/arb_mux_demux:arbiter_tb", - "//hdl/ip/vhd/fifos:fifos_tb", - "//hdl/ip/vhd/memories:memories_tb", - "//hdl/ip/vhd/synchronizers:synchronizers_tb", - "//hdl/ip/vhd/common:utilities_tb", - "//hdl/ip/vhd/fmc_if:fmc_tb", - ] -) \ No newline at end of file diff --git a/hdl/ip/vhd/memories/BUCK b/hdl/ip/vhd/memories/BUCK index 924511a5..2bd2b301 100644 --- a/hdl/ip/vhd/memories/BUCK +++ b/hdl/ip/vhd/memories/BUCK @@ -15,6 +15,7 @@ vhdl_unit( srcs = glob(["sims/*.vhd"]), deps = [ ":dual_clock_simple_dpr", + "//hdl/ip/vhd/fifos:dcfifo_xpm", "//hdl/ip/vhd/vunit_components:sim_gpio" ], visibility = ['PUBLIC'], diff --git a/hdl/ip/vhd/vunit_components/qspi_controller/sims/qspi_vc_tb.vhd b/hdl/ip/vhd/vunit_components/qspi_controller/sims/qspi_vc_tb.vhd deleted file mode 100644 index 32990fb5..00000000 --- a/hdl/ip/vhd/vunit_components/qspi_controller/sims/qspi_vc_tb.vhd +++ /dev/null @@ -1,65 +0,0 @@ --- This Source Code Form is subject to the terms of the Mozilla Public --- License, v. 2.0. If a copy of the MPL was not distributed with this --- file, You can obtain one at https://mozilla.org/MPL/2.0/. --- --- Copyright 2024 Oxide Computer Company - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library vunit_lib; - context vunit_lib.com_context; - context vunit_lib.vunit_context; -use vunit_lib.sync_pkg.all; -use work.qspi_vc_pkg.all; - -entity qspi_vc_tb is - generic ( - - runner_cfg : string - ); -end entity; - -architecture tb of qspi_vc_tb is - - constant tx_queue : queue_t := new_queue; - -begin - - th: entity work.qspi_vc_th; - - bench: process - alias sim_reset is <>; - alias ss_n is <>; - variable msg_target : actor_t; - begin - -- Always the first thing in the process, set up things for the VUnit test runner - test_runner_setup(runner, runner_cfg); - - -- Reach into the test harness, which generates and de-asserts reset and hold the - -- test cases off until we're out of reset. This runs for every test case - wait until sim_reset = '0'; - msg_target := find("espi_vc"); -- get actor for the qspi block - - while test_suite loop - if run("shift_bytes_single") then - -- set_mode(net, msg_target, QUAD); - push_byte(tx_queue, 16#A5#); - enqueue_tx_data_bytes(net, msg_target, 1, tx_queue); - enqueue_transaction(net, msg_target, 1, 1); - -- cear the chipsel - -- wait for 0 ns; - -- elsif run("shift_bytes_dual") then - -- elsif run("shift_bytes_quad") then - end if; - end loop; - wait for 4 us; - test_runner_cleanup(runner); - wait; - end process; - - -- Example total test timeout dog - test_runner_watchdog(runner, 4 us); - -end tb; diff --git a/hdl/ip/vhd/vunit_components/qspi_controller/sims/qspi_vc_th.vhd b/hdl/ip/vhd/vunit_components/qspi_controller/sims/qspi_vc_th.vhd deleted file mode 100644 index 9efdd211..00000000 --- a/hdl/ip/vhd/vunit_components/qspi_controller/sims/qspi_vc_th.vhd +++ /dev/null @@ -1,43 +0,0 @@ --- This Source Code Form is subject to the terms of the Mozilla Public --- License, v. 2.0. If a copy of the MPL was not distributed with this --- file, You can obtain one at https://mozilla.org/MPL/2.0/. --- --- Copyright 2024 Oxide Computer Company - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.qspi_vc_pkg.all; - -entity qspi_vc_th is -end entity; - -architecture th of qspi_vc_th is - - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - - signal ss_n : std_logic_vector(7 downto 0); - signal sclk : std_logic; - signal io : std_logic_vector(3 downto 0); - - constant qspi_vc : qspi_vc_t := new_qspi_vc("espi_vc"); - -begin - - -- set up a fastish clock for the sim - -- environment and release reset after a bit of time - clk <= not clk after 4 ns; - reset <= '0' after 200 ns; - - qspi_controller_vc_inst: entity work.qspi_controller_vc - generic map ( - qspi_vc => qspi_vc - ) - port map ( - ss_n => ss_n, - sclk => sclk, - io => io - ); - -end th; diff --git a/tools/vunit-sims.bxl b/tools/vunit-sims.bxl new file mode 100644 index 00000000..ea39bd1e --- /dev/null +++ b/tools/vunit-sims.bxl @@ -0,0 +1,29 @@ +# This Source Code Form is subject to the terms of the Mozilla Public +# License, v. 2.0. If a copy of the MPL was not distributed with this +# file, You can obtain one at https://mozilla.org/MPL/2.0/. +# +# Copyright 2024 Oxide Computer Company + +# This function queries the build graph and targets that are +# simulation targets and runs them +def vunit_sim(ctx): + # start with all the buck2 targets from the root + target_universe = ctx.target_universe("//...").target_set() + # Get the deps + targets = ctx.cquery().deps(target_universe) + # Filter for vhdl files in the project + vhdl_files = ctx.cquery().kind("vhdl.*", targets) + sims = ctx.cquery().attrfilter("is_tb", "True", vhdl_files) + sims = sorted(sims, key=lambda x: x.attrs_eager().standard.value()) + # Eagerly analyze targets + results = ctx.analysis(sims) + for lbl,result in results.items(): + ctx.output.print("buck2 run " + str(lbl.raw_target()) + " -- --clean -x " + lbl.name + ".xml") + + +vunit_sim_gen = bxl_main( + impl = vunit_sim, + cli_args = { + # cli args that you want to receive from the command line + }, +) \ No newline at end of file From f324a41ed73c3fa3d483e7b8963524f1fa34fcb8 Mon Sep 17 00:00:00 2001 From: Nathanael Huffman Date: Fri, 11 Oct 2024 15:04:36 -0500 Subject: [PATCH 2/5] Remove failing test --- hdl/projects/gimlet/sequencer/A1Block.bsv | 25 ----------------------- hdl/projects/gimlet/sequencer/BUILD | 1 - 2 files changed, 26 deletions(-) diff --git a/hdl/projects/gimlet/sequencer/A1Block.bsv b/hdl/projects/gimlet/sequencer/A1Block.bsv index 2d7776f5..7436fa31 100644 --- a/hdl/projects/gimlet/sequencer/A1Block.bsv +++ b/hdl/projects/gimlet/sequencer/A1Block.bsv @@ -348,31 +348,6 @@ import PowerRail::*; endmodule - module mkA1PowerDownA0InteractionTest(Empty); - - Bench bench <- mkBench(); - - mkAutoFSM(seq - dynamicAssert(bench.a1_ok == False, "Expected sequencer in A2"); - dynamicAssert(bench.seq_to_sp3_rsmrst_v3p3_l == 0, "Expected RSMRST_L asserted"); - bench.power_up(); - await(bench.a1_ok); - bench.a0_busy(); - dynamicAssert(bench.seq_to_sp3_rsmrst_v3p3_l == 1, "Expected RSMRST_L de-asserted"); - bench.power_down(); // Should not actually happen because A0 is busy - delay(200); - dynamicAssert(bench.a1_ok == True, "Expected a1_ok to still be asserted since it can't power down"); - dynamicAssert(bench.seq_to_sp3_rsmrst_v3p3_l == 1, "Expected RSMRST_L still de-asserted"); - bench.a0_idle(); - delay(5); - dynamicAssert(bench.a1_ok == False, "Expected a1_ok to be de-asserted we can now power down"); - dynamicAssert(bench.seq_to_sp3_rsmrst_v3p3_l == 0, "Expected RSMRST_L asserted"); - dynamicAssert(bench.v3p3_s5.enabled == False, "Expected v3p3_s5_en de-asserted"); - delay(200); - endseq); - - endmodule - module mkA1MAPOTest(Empty); Bench bench <- mkBench(); diff --git a/hdl/projects/gimlet/sequencer/BUILD b/hdl/projects/gimlet/sequencer/BUILD index ad6495e0..bf61b86e 100644 --- a/hdl/projects/gimlet/sequencer/BUILD +++ b/hdl/projects/gimlet/sequencer/BUILD @@ -93,7 +93,6 @@ bluesim_tests('A1Tests', 'mkA1PowerUpTest', 'mkA1PowerDownTest', 'mkA1MAPOTest', - 'mkA1PowerDownA0InteractionTest', ], deps = [ ':A1Block' From f057524085ff063e7ae02b082b7cb9d10564a879 Mon Sep 17 00:00:00 2001 From: Nathanael Huffman Date: Fri, 11 Oct 2024 15:04:36 -0500 Subject: [PATCH 3/5] add readme info --- README.md | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/README.md b/README.md index d72feba9..eb8b4089 100644 --- a/README.md +++ b/README.md @@ -96,6 +96,18 @@ but if you want to see a list of all available buck2 targets you can do: `buck2 To run a simulation, pick one of the testbench targets and `buck2 run ` you may do `-- ` if you need to pass arguments into VUnit. +### running all sims or sim regressions +We can use the build system to query for vunit simulation testbenches and have built a .bxl +that does this and gives you the command line options to run each one found: + +`buck2 bxl //tools/vunit-sims.bxl:vunit_sim_gen` + +If you'd like to run a regression run like the build machine does, you can pipe that into split +and use the shell to execute each line: + +`buck2 bxl //tools/vunit-sims.bxl:vunit_sim_gen | while IFS= read -r line; do eval "$line" ; done` + + ## multitool multitool is a collection of quality of live utilities built in-tree for regular use, but whose function is small enough to not warrant a self-contained project. From 46c69d8f249767941b3b7cd6d77db6a4dce7b91c Mon Sep 17 00:00:00 2001 From: Nathanael Huffman Date: Thu, 14 Nov 2024 20:35:08 -0600 Subject: [PATCH 4/5] Remove deprecated test --- .github/workflows/build.yml | 63 ++++++++++++++++++++++++++++++++ .github/workflows/simulation.yml | 4 +- 2 files changed, 66 insertions(+), 1 deletion(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index e69de29b..c4a92da5 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -0,0 +1,63 @@ +name: fpga-build +run-name: ${{ github.actor }} Building FPGA bitstreams +on: + [push] +jobs: + changes: + runs-on: self-hosted + permissions: + pull-requests: read + outputs: + cobble: ${{ steps.filter.outputs.cobble }} + buck2: ${{ steps.filter.outputs.buck2 }} + steps: + - uses: actions/checkout@v4 + with: + submodules: 'true' + - uses: dorny/paths-filter@v3 + id: filter + with: + filters: .github/filters.yml + + grapefruit: + needs: changes + if: ${{ needs.changes.outputs.buck2 == 'true' }} + runs-on: self-hosted + steps: + - run: echo "The name of your branch is ${{ github.ref }} and your repository is ${{ github.repository }}." + - name: Check out repository code + uses: actions/checkout@v4 + with: + submodules: 'true' + - name: Update pip reqs + run : python3 -m pip install --upgrade -r tools/requirements.txt --break-system-packages + - name: buck path + run: echo "~/.cargo/bin" >> "$GITHUB_PATH" + - name: Build grapefruit bitstream + run: buck2 build //hdl/projects/grapefruit:grapefruit --show-output + + bsv-streams: + needs: changes + if: ${{ needs.changes.outputs.buck2 == 'true' }} + runs-on: self-hosted + steps: + - run: echo "The name of your branch is ${{ github.ref }} and your repository is ${{ github.repository }}." + - name: Check out repository code + uses: actions/checkout@v4 + with: + submodules: 'true' + fetch-depth: 0 + - name: Update pip reqs + run : python3 -m pip install --upgrade -r tools/requirements.txt --break-system-packages + - name: Env setup + run: cp BUILD.vars.gha BUILD.vars && echo "/opt/bsc-2022.01/bin" >> "$GITHUB_PATH" + - name: Restore build-dir + run: if [ -d /tmp/cobble_build_bkup ]; then cp -R /tmp/cobble_build_bkup ./build; else mkdir ./build; fi + - name: cobble init + run: ../vnd/cobble/cobble init .. --reinit + working-directory: ./build + - name: Build FPGAs + run: ./cobble build -v "//.*#bitstream" + working-directory: ./build + - name: backup build-dir + run: cp -R ./build /tmp/cobble_build_bkup \ No newline at end of file diff --git a/.github/workflows/simulation.yml b/.github/workflows/simulation.yml index 0fc06c99..036c9166 100644 --- a/.github/workflows/simulation.yml +++ b/.github/workflows/simulation.yml @@ -31,6 +31,8 @@ jobs: submodules: 'true' - name: Update pip reqs run : python3 -m pip install --upgrade -r tools/requirements.txt --break-system-packages + - name: buck path + run: echo "~/.cargo/bin" >> "$GITHUB_PATH" - name: Run VUnit tests run: buck2 bxl //tools/vunit-sims.bxl:vunit_sim_gen | while IFS= read -r line; do eval "$line" ; done @@ -55,7 +57,7 @@ jobs: run: ../vnd/cobble/cobble init .. --reinit working-directory: ./build - name: Run BSIM tests - run: ./cobble bluesim_test "//.*SchmittRegTest.*" + run: ./cobble bluesim_test "//.*Test.*" working-directory: ./build - name: backup build-dir run: cp -R ./build /tmp/cobble_build_bkup \ No newline at end of file From 6e495c4157d33bf4b5204c8f60017e4824547589 Mon Sep 17 00:00:00 2001 From: Nathanael Huffman Date: Fri, 15 Nov 2024 14:14:48 -0600 Subject: [PATCH 5/5] Upload artifacts --- .github/workflows/build.yml | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index c4a92da5..eb166619 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -32,9 +32,13 @@ jobs: - name: Update pip reqs run : python3 -m pip install --upgrade -r tools/requirements.txt --break-system-packages - name: buck path - run: echo "~/.cargo/bin" >> "$GITHUB_PATH" + run: echo "~/.cargo/bin:/opt/Xilinx/Vivado/2024.1/bin" >> "$GITHUB_PATH" - name: Build grapefruit bitstream run: buck2 build //hdl/projects/grapefruit:grapefruit --show-output + - uses: actions/upload-artifact@v4 + with: + name: gfruit-image + path: "./buck-out/v2/gen/root/**/*" bsv-streams: needs: changes @@ -60,4 +64,8 @@ jobs: run: ./cobble build -v "//.*#bitstream" working-directory: ./build - name: backup build-dir - run: cp -R ./build /tmp/cobble_build_bkup \ No newline at end of file + run: cp -R ./build /tmp/cobble_build_bkup + - uses: actions/upload-artifact@v4 + with: + name: bsv-images + path: "./build/latest/**/*" \ No newline at end of file