From fb77d29f9571f682810a8bbea41029a6d4298c1c Mon Sep 17 00:00:00 2001 From: Nathanael Huffman Date: Fri, 22 Nov 2024 13:43:51 -0600 Subject: [PATCH] Fail the job if the bxl fails --- .github/filters.yml | 2 + .github/workflows/simulation.yml | 2 +- hdl/projects/gimlet/vhdl_test/BUCK | 16 ------ hdl/projects/gimlet/vhdl_test/leds.vhd | 70 ------------------------ hdl/projects/gimlet/vhdl_test/pinmap.pcf | 6 -- 5 files changed, 3 insertions(+), 93 deletions(-) delete mode 100644 hdl/projects/gimlet/vhdl_test/BUCK delete mode 100644 hdl/projects/gimlet/vhdl_test/leds.vhd delete mode 100644 hdl/projects/gimlet/vhdl_test/pinmap.pcf diff --git a/.github/filters.yml b/.github/filters.yml index ee0eaa37..d86a4a20 100644 --- a/.github/filters.yml +++ b/.github/filters.yml @@ -1,4 +1,5 @@ cobble: + - .github/**/* - 'tools/site_cobble/**/*' - 'vnd/**/*' - 'hdl/ip/bsv/**/*' @@ -11,6 +12,7 @@ cobble: - 'hdl/projects/ulx3s/**/*' buck2: + - .github/**/* - 'vnd/xpm/**/*' - 'prelude/**/*' - 'toolchains/**/*' diff --git a/.github/workflows/simulation.yml b/.github/workflows/simulation.yml index 036c9166..626d76cf 100644 --- a/.github/workflows/simulation.yml +++ b/.github/workflows/simulation.yml @@ -34,7 +34,7 @@ jobs: - name: buck path run: echo "~/.cargo/bin" >> "$GITHUB_PATH" - name: Run VUnit tests - run: buck2 bxl //tools/vunit-sims.bxl:vunit_sim_gen | while IFS= read -r line; do eval "$line" ; done + run: set -o pipefail; buck2 bxl //tools/vunit-sims.bxl:vunit_sim_gen | while IFS= read -r line; do eval "$line" ; done bsv-sim: needs: changes diff --git a/hdl/projects/gimlet/vhdl_test/BUCK b/hdl/projects/gimlet/vhdl_test/BUCK deleted file mode 100644 index bbccb292..00000000 --- a/hdl/projects/gimlet/vhdl_test/BUCK +++ /dev/null @@ -1,16 +0,0 @@ -load("//tools:hdl.bzl", "vhdl_unit") -load("//tools:yosys.bzl", "ice40_bitstream") - -vhdl_unit( - name = "leds", - srcs = glob(["*.vhd"]), - standard = "2008", -) - -ice40_bitstream( - name="leds_top", - top_entity_name="leds", - top= ":leds", - package="hx1k", - pinmap="pinmap.pcf" -) \ No newline at end of file diff --git a/hdl/projects/gimlet/vhdl_test/leds.vhd b/hdl/projects/gimlet/vhdl_test/leds.vhd deleted file mode 100644 index 9acc373a..00000000 --- a/hdl/projects/gimlet/vhdl_test/leds.vhd +++ /dev/null @@ -1,70 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity leds is - port ( - clk : in std_logic; - led1 : out; - led2 : out; - led3 : out; - led4 : out; - led5 : out std_logic - ); -end entity; - -architecture spin1 of leds is - - signal nrst : std_logic := '0'; - signal clk_4hz : std_logic; - signal leds : std_ulogic_vector (1 to 5); - -begin - - (led1, led2, led3, led4, led5) <= leds; - - process(clk) - variable cnt : unsigned (1 downto 0) := "00"; - begin - if rising_edge (clk) then - if cnt = 3 then - nrst <= '1'; - else - cnt := cnt + 1; - end if; - end if; - end process; - - process(clk) - -- 3_000_000 is 0x2dc6c0 - variable counter : unsigned (23 downto 0); - begin - if rising_edge(clk) then - if nrst = '0' then - counter := x"000000"; - else - if counter = 2_999_999 then - counter := x"000000"; - clk_4hz <= '1'; - else - counter := counter + 1; - clk_4hz <= '0'; - end if; - end if; - end if; - end process; - - process(clk) - begin - if rising_edge(clk) then - if nrst = '0' then - -- Initialize - leds <= "11000"; - elsif clk_4hz = '1' then - -- Rotate - leds <= (leds (4), leds (1), leds (2), leds (3), '0'); - end if; - end if; - end process; - -end spin1; diff --git a/hdl/projects/gimlet/vhdl_test/pinmap.pcf b/hdl/projects/gimlet/vhdl_test/pinmap.pcf deleted file mode 100644 index 1fd5fb48..00000000 --- a/hdl/projects/gimlet/vhdl_test/pinmap.pcf +++ /dev/null @@ -1,6 +0,0 @@ -set_io led1 99 -set_io led2 98 -set_io led3 97 -set_io led4 96 -set_io led5 95 -set_io clk 21 \ No newline at end of file