diff --git a/hdl/ip/vhd/espi/BUCK b/hdl/ip/vhd/espi/BUCK index 18a718d2..1251ccab 100644 --- a/hdl/ip/vhd/espi/BUCK +++ b/hdl/ip/vhd/espi/BUCK @@ -8,6 +8,13 @@ rdl_file( visibility = ['PUBLIC'] ) +rdl_file( + name = "vwire_regs_pkg", + src = "vwire_channel/vwire_regs.rdl", + outputs = ["vwire_regs_pkg.vhd", "vwire_regs.html"], + visibility = ['PUBLIC'] +) + rdl_file( name = "espi_regs_pkg", src = "sys_regs/espi_regs.rdl", @@ -23,10 +30,12 @@ vhdl_unit( "flash_channel/*.vhd", "sys_regs/*.vhd", "uart_channel/*.vhd", + "vwire_channel/*.vhd", "*.vhd"]), deps = [ ":espi_spec_regs_pkg", ":espi_regs_pkg", + ":vwire_regs_pkg", "//hdl/ip/vhd/crc:crc8atm_8wide", "//hdl/ip/vhd/fifos:dcfifo_xpm", "//hdl/ip/vhd/fifos:dcfifo_mixed_xpm", diff --git a/hdl/ip/vhd/espi/espi_spec_regs.rdl b/hdl/ip/vhd/espi/espi_spec_regs.rdl index 7b89e20c..3ab15927 100644 --- a/hdl/ip/vhd/espi/espi_spec_regs.rdl +++ b/hdl/ip/vhd/espi/espi_spec_regs.rdl @@ -70,7 +70,7 @@ addrmap eSPI_Spec { desc = "I/O Mode Support"; sw = r; encode = io_mode_support; - } io_mode_support[25:24] = io_mode_support::Any; + } io_mode_support[25:24] = io_mode_support::Single; field { desc = "Open Drain Alert# Select"; sw = rw; @@ -88,7 +88,7 @@ addrmap eSPI_Spec { desc = "Operating Frequency Support"; sw = r; encode = op_freq; - } op_freq_support[18:16] = op_freq::SixtySix; + } op_freq_support[18:16] = op_freq::Twenty; field { desc = "Maximum Wait State allowed"; sw = rw; @@ -112,7 +112,7 @@ addrmap eSPI_Spec { } general_capabilities; reg { - name = "Maximum Read Request Size"; + name = "Channel 0 Capabilities"; default sw = rw; field { @@ -156,6 +156,29 @@ addrmap eSPI_Spec { } ch0_capabilities @0x10; + reg { + name = "Channel 1 Capabilities"; + default sw = rw; + + field { + desc = ""; + } wire_count_sel[21:16] = 0x0; + + field { + desc = "Maximum Virtual Wire Count Supported"; + } wire_max_supported[13:8] = 0x7; + + field { + desc = "Channel Ready"; + sw = r; + } chan_rdy[1:1] = 0x0; + + field { + desc = "Channel Enable"; + } chan_en[0:0] = 0x1; + + } ch1_capabilities @0x20; + reg { name = "Channel 2(OOB) Capabilities"; default sw = rw; diff --git a/hdl/ip/vhd/espi/espi_spec_regs.vhd b/hdl/ip/vhd/espi/espi_spec_regs.vhd index a1892d1c..1008016d 100644 --- a/hdl/ip/vhd/espi/espi_spec_regs.vhd +++ b/hdl/ip/vhd/espi/espi_spec_regs.vhd @@ -34,6 +34,7 @@ architecture rtl of espi_spec_regs is signal device_id : device_id_type; signal gen_capabilities : general_capabilities_type; signal ch0_capabilities : ch0_capabilities_type; + signal ch1_capabilities : ch1_capabilities_type; signal ch3_capabilities : ch3_capabilities_type; signal readdata_valid : std_logic; signal readdata : std_logic_vector(31 downto 0); @@ -52,6 +53,7 @@ begin device_id <= rec_reset; gen_capabilities <= rec_reset; ch0_capabilities <= rec_reset; + ch1_capabilities <= rec_reset; ch3_capabilities <= rec_reset; elsif rising_edge(clk) then if regs_if.addr = GENERAL_CAPABILITIES_OFFSET and regs_if.write = '1' then @@ -73,6 +75,15 @@ begin ch0_capabilities.chan_rdy <= ch0_capabilities.chan_rdy; end if; + if regs_if.addr = CH1_CAPABILITIES_OFFSET and regs_if.write = '1' then + ch1_capabilities <= unpack(regs_if.wdata); + -- clean up RO fields by keeping current val + ch1_capabilities.wire_max_supported <= ch1_capabilities.wire_max_supported; + ch1_capabilities.chan_rdy <= ch1_capabilities.chan_rdy; + else + ch1_capabilities.chan_rdy <= ch1_capabilities.chan_en; + end if; + if regs_if.addr = CH3_CAPABILITIES_OFFSET and regs_if.write = '1' then ch3_capabilities <= unpack(regs_if.wdata); -- clean up RO fields by keeping current val @@ -105,6 +116,10 @@ begin readdata <= pack(gen_capabilities); when CH0_CAPABILITIES_OFFSET => readdata <= pack(ch0_capabilities); + when CH1_CAPABILITIES_OFFSET => + readdata <= pack(ch1_capabilities); + when CH3_CAPABILITIES_OFFSET => + readdata <= pack(ch3_capabilities); when others => readdata <= (others => '0'); end case; diff --git a/hdl/ip/vhd/espi/espi_target_top.vhd b/hdl/ip/vhd/espi/espi_target_top.vhd index 067db12f..bed94fc4 100644 --- a/hdl/ip/vhd/espi/espi_target_top.vhd +++ b/hdl/ip/vhd/espi/espi_target_top.vhd @@ -19,6 +19,8 @@ entity espi_target_top is port ( clk : in std_logic; reset : in std_logic; + axi_clk : in std_logic; + axi_reset : in std_logic; -- Axilite interface axi_if : view axil_target; -- phy interface @@ -68,16 +70,43 @@ architecture rtl of espi_target_top is signal host_to_sp_espi : st_uart_t; signal sp_to_host_espi : uart_resp_t; signal aborted_due_to_bad_crc : boolean; + signal cs_n_syncd : std_logic; + signal sclk_syncd : std_logic; + signal vwire_if : vwire_if_type; + signal vwire_avail : std_logic; begin + -- sync + cs_meta_sync_inst: entity work.meta_sync + generic map( + stages => 1 + ) + port map( + async_input => cs_n, + clk => clk, + sycnd_output => cs_n_syncd + ); + + sclk_meta_sync_inst: entity work.meta_sync + generic map( + stages => 1 + ) + port map( + async_input => sclk, + clk => clk, + sycnd_output => sclk_syncd + ); + -- link layer link_layer_top_inst: entity work.link_layer_top port map( clk => clk, reset => reset, - cs_n => cs_n, - sclk => sclk, + axi_clk => axi_clk, + axi_reset => axi_reset, + cs_n => cs_n_syncd, + sclk => sclk_syncd, io => io, io_o => io_o, io_oe => io_oe, @@ -95,8 +124,8 @@ begin -- system (axi-lite) register block espi_sys_regs_inst: entity work.espi_regs port map( - clk => clk, - reset => reset, + clk => axi_clk, + reset => axi_reset, axi_if => axi_if, dbg_chan => dbg_chan ); @@ -108,6 +137,7 @@ begin reset => reset, is_crc_byte => is_crc_byte, regs_if => regs_if, + vwire_if => vwire_if, chip_sel_active => chip_sel_active, data_to_host => data_to_host, data_from_host => data_from_host, @@ -124,7 +154,8 @@ begin pc_free => pc_free, pc_avail => pc_avail, np_free => np_free, - np_avail => np_avail + np_avail => np_avail, + vwire_avail => vwire_avail ); -- espi-internal register block @@ -173,4 +204,13 @@ begin np_avail => np_avail ); + -- vwire channel logic + vwire_block_inst: entity work.vwire_block + port map( + clk => clk, + reset => reset, + espi_reset_flag => '0', + wire_tx_avail => vwire_avail, + vwire_if => vwire_if + ); end rtl; diff --git a/hdl/ip/vhd/espi/link_layer/dbg_link_faker.vhd b/hdl/ip/vhd/espi/link_layer/dbg_link_faker.vhd index 388b1a53..4d26dc4f 100644 --- a/hdl/ip/vhd/espi/link_layer/dbg_link_faker.vhd +++ b/hdl/ip/vhd/espi/link_layer/dbg_link_faker.vhd @@ -21,6 +21,8 @@ entity dbg_link_faker is port ( clk : in std_logic; reset : in std_logic; + axi_clk : in std_logic; + axi_reset : in std_logic; -- Asserted by command processor during the -- transmission of the last command byte (the CRC) response_done : in boolean; @@ -72,15 +74,48 @@ architecture rtl of dbg_link_faker is signal cmd_fifo_wusedwds: std_logic_vector(log2ceil(1024) downto 0); signal rusedwds: std_logic_vector(log2ceil(1024) downto 0); signal resp_fifo_rusedwds: std_logic_vector(log2ceil(1024) downto 0); + signal busy: std_logic; + signal busy_axi_sync: std_logic; + signal alert_pending : std_logic; + signal alert_pending_axi_sync : std_logic; begin - dbg_chan.busy <= '1' when r.state /= idle else '0'; + sync_regs: process(clk, reset) + begin + if reset = '1' then + busy <= '0'; + alert_pending <= '0'; + elsif rising_edge(clk) then + busy <= '1' when r.state /= idle else '0'; + alert_pending <= '1' when alert_needed else '0'; + end if; + end process; + + busy_meta_sync_inst: entity work.meta_sync + generic map( + stages => 2 + ) + port map( + async_input => busy, + clk => clk, + sycnd_output => busy_axi_sync + ); + alert_meta_sync_inst: entity work.meta_sync + generic map( + stages => 2 + ) + port map( + async_input => alert_pending, + clk => clk, + sycnd_output => alert_pending_axi_sync + ); + dbg_chan.busy <= busy_axi_sync; dbg_chan.wstatus.usedwds <= resize(cmd_fifo_wusedwds, dbg_chan.wstatus.usedwds'length); dbg_chan.rdstatus.usedwds <= resize(resp_fifo_rusedwds, dbg_chan.rdstatus.usedwds'length); dbg_chan.rd.data <= resp_fifo_read_data; cs_active <= r.cs_asserted; - dbg_chan.alert_pending <= '1' when alert_needed else '0'; + dbg_chan.alert_pending <= alert_pending_axi_sync; -- Timer: the fastest byte transfer that can be done is 2 clocks at 66MHz (in quad mode) so we'll -- generate a strobe at that speed when enabled to provide effective rate-limiting to the design. @@ -113,8 +148,8 @@ begin showahead_mode => true ) port map( - wclk => clk, - reset => reset, + wclk => axi_clk, + reset => axi_reset, write_en => dbg_chan.wr.write, wdata => dbg_chan.wr.data, wfull => open, @@ -133,7 +168,7 @@ begin showahead_mode => true ) port map( - wclk => clk, + wclk => axi_clk, reset => reset, write_en => dbg_chan.size.write, wdata => dbg_chan.size.data, @@ -252,7 +287,7 @@ begin wdata => data_to_host.data, wfull => open, wusedwds => open, - rclk => clk, + rclk => axi_clk, rdata => resp_fifo_read_data, rdreq => resp_fifo_read_ack, rempty => resp_fifo_empty, diff --git a/hdl/ip/vhd/espi/link_layer/link_layer_top.vhd b/hdl/ip/vhd/espi/link_layer/link_layer_top.vhd index 0b71c55f..8b52f3ae 100644 --- a/hdl/ip/vhd/espi/link_layer/link_layer_top.vhd +++ b/hdl/ip/vhd/espi/link_layer/link_layer_top.vhd @@ -14,6 +14,8 @@ entity link_layer_top is port ( clk : in std_logic; reset : in std_logic; + axi_clk : in std_logic; + axi_reset : in std_logic; cs_n : in std_logic; sclk : in std_logic; @@ -46,11 +48,21 @@ architecture rtl of link_layer_top is signal dbg_data_to_host : data_channel; signal dbg_data_from_host : data_channel; signal dbg_alert_needed : boolean; - alias debug_active is dbg_chan.enabled; + signal debug_active : boolean; signal dbg_chip_sel_active : boolean; begin + -- sync from axi domain into the system domain + sync_process: process(clk, reset) + begin + if reset then + debug_active <= false; + elsif rising_edge(clk) then + debug_active <= dbg_chan.enabled; + end if; + end process; + -- The "real" link layer qspi_link_layer: entity work.qspi_link_layer port map ( @@ -73,6 +85,8 @@ begin port map ( clk => clk, reset => reset, + axi_clk => axi_clk, + axi_reset => axi_reset, response_done => response_done, aborted_due_to_bad_crc => aborted_due_to_bad_crc, cs_active => dbg_chip_sel_active, diff --git a/hdl/ip/vhd/espi/link_layer/qspi_link_layer.vhd b/hdl/ip/vhd/espi/link_layer/qspi_link_layer.vhd index 14f7bac6..b12d5482 100644 --- a/hdl/ip/vhd/espi/link_layer/qspi_link_layer.vhd +++ b/hdl/ip/vhd/espi/link_layer/qspi_link_layer.vhd @@ -42,6 +42,13 @@ entity qspi_link_layer is -- "Streaming" bytes after receipt and deserialization data_from_host : view st_source; ); + attribute mark_debug : string; + attribute mark_debug of io_oe : signal is "TRUE"; + attribute mark_debug of io_o : signal is "TRUE"; + attribute mark_debug of io : signal is "TRUE"; + attribute mark_debug of sclk : signal is "TRUE"; + attribute mark_debug of cs_n : signal is "TRUE"; + end entity; architecture rtl of qspi_link_layer is @@ -56,6 +63,8 @@ architecture rtl of qspi_link_layer is -- for a sentinel value signal tx_reg : std_logic_vector(8 downto 0); signal rx_reg : std_logic_vector(8 downto 0); + attribute mark_debug of tx_reg : signal is "TRUE"; + attribute mark_debug of rx_reg : signal is "TRUE"; signal in_turnaround : boolean; signal ta_cnts : integer range 0 to 2 := 0; signal response_phase : boolean; @@ -67,6 +76,7 @@ architecture rtl of qspi_link_layer is signal cs_cntr : natural range 0 to 3 := 0; constant cs_deassert_delay : natural := 2; + begin -- We have some fairly slow minimum delay timings for the alert pin diff --git a/hdl/ip/vhd/espi/sims/espi_tb.vhd b/hdl/ip/vhd/espi/sims/espi_tb.vhd index a71d8b21..695d3f47 100644 --- a/hdl/ip/vhd/espi/sims/espi_tb.vhd +++ b/hdl/ip/vhd/espi/sims/espi_tb.vhd @@ -109,18 +109,6 @@ begin exp_data_32 := (others => '0'); check_equal(data_32, exp_data_32, "Expected no response to bad CRC command"); - -- dbg_get_response(net, 4, response); - -- check(response.crc_ok, "CRC Check failed"); - -- expected_status := pack(status_t'(rec_reset)); - -- check_equal(response.status, expected_status, "Status did not match reset value"); - - -- -- Do it a 2nd time - -- dbg_send_get_status_cmd(net); - -- dbg_wait_for_done(net); - -- dbg_get_response(net, 4, response); - -- check(response.crc_ok, "CRC Check failed"); - -- expected_status := pack(status_t'(rec_reset)); - -- check_equal(response.status, expected_status, "Status did not match reset value"); elsif run("get_config") then get_config(net, GENERAL_CAPABILITIES_OFFSET, data_32, response_code, status, crc_ok); check(crc_ok, "CRC Check failed"); @@ -200,6 +188,11 @@ begin print("Response size: " & integer'image(gen_int)); dbg_get_response(net, 40 , response); check(response.crc_ok, "CRC Check failed"); + elsif run("dbg_ruby_boot") then + send_reset(net); + wait for 1 us; + set_config(net, CH1_CAPABILITIES_OFFSET, X"00000001", response_code, status, crc_ok); + end if; end loop; wait for 10 us; diff --git a/hdl/ip/vhd/espi/sims/espi_tb_pkg.vhd b/hdl/ip/vhd/espi/sims/espi_tb_pkg.vhd index 97e9b064..816ab0aa 100644 --- a/hdl/ip/vhd/espi/sims/espi_tb_pkg.vhd +++ b/hdl/ip/vhd/espi/sims/espi_tb_pkg.vhd @@ -60,6 +60,7 @@ package espi_tb_pkg is -- returns the queue and the number of bytes in the queue -- for additional processing in the testbench such as -- commanding the qspi VC or using the debug axi interface + impure function build_reset_cmd return cmd_t; impure function build_get_status_cmd(constant bad_crc : boolean := false) return cmd_t; impure function build_get_config_cmd( constant address : natural; @@ -161,6 +162,16 @@ package body espi_tb_pkg is return cmd; end function; + impure function build_reset_cmd return cmd_t is + variable cmd : cmd_t := (new_queue, 0); + begin + push_byte(cmd.queue, to_integer(unsigned'(X"FF"))); + cmd.num_bytes := cmd.num_bytes + 1; + push_byte(cmd.queue, to_integer(unsigned'(X"FF"))); + cmd.num_bytes := cmd.num_bytes + 1; + return cmd; + end function; + impure function build_get_config_cmd( constant address : natural; constant bad_crc : boolean := false diff --git a/hdl/ip/vhd/espi/sims/espi_th.vhd b/hdl/ip/vhd/espi/sims/espi_th.vhd index bd2410e4..67ad6e93 100644 --- a/hdl/ip/vhd/espi/sims/espi_th.vhd +++ b/hdl/ip/vhd/espi/sims/espi_th.vhd @@ -94,6 +94,8 @@ begin port map ( clk => clk, reset => reset, + axi_clk => clk, + axi_reset => reset, cs_n => ss_n(0), sclk => sclk, io => io, diff --git a/hdl/ip/vhd/espi/sims/models/espi_controller_vc_pkg.vhd b/hdl/ip/vhd/espi/sims/models/espi_controller_vc_pkg.vhd index 42947579..70177ad1 100644 --- a/hdl/ip/vhd/espi/sims/models/espi_controller_vc_pkg.vhd +++ b/hdl/ip/vhd/espi/sims/models/espi_controller_vc_pkg.vhd @@ -27,6 +27,10 @@ package espi_controller_vc_pkg is constant rx_queue : queue_t := new_queue; + procedure send_reset( + signal net : inout network_t + ); + procedure get_status( signal net : inout network_t; variable response_code : inout std_logic_vector(7 downto 0); @@ -98,6 +102,17 @@ package body espi_controller_vc_pkg is return status; end; + procedure send_reset( + signal net : inout network_t + ) is + variable msg_target : actor_t := find("espi_vc"); + variable cmd : cmd_t := (new_queue, 0); + begin + cmd := build_reset_cmd; + enqueue_tx_data_bytes(net, msg_target, cmd.num_bytes, cmd.queue); + enqueue_transaction(net, msg_target, cmd.num_bytes, 0); + end; + procedure get_status( signal net : inout network_t; variable response_code : inout std_logic_vector(7 downto 0); diff --git a/hdl/ip/vhd/espi/txn_layer/command_processor.vhd b/hdl/ip/vhd/espi/txn_layer/command_processor.vhd index 97a670a7..6c51ad3d 100644 --- a/hdl/ip/vhd/espi/txn_layer/command_processor.vhd +++ b/hdl/ip/vhd/espi/txn_layer/command_processor.vhd @@ -23,6 +23,7 @@ entity command_processor is running_crc : in std_logic_vector(7 downto 0); clear_rx_crc : out std_logic; regs_if : view bus_side; + vwire_if : view vwire_cmd_side; command_header : out espi_cmd_header; response_done : in boolean; aborted_due_to_bad_crc : out boolean; @@ -41,6 +42,8 @@ end entity; architecture rtl of command_processor is + attribute mark_debug : string; + type pkt_state_t is ( idle, opcode, @@ -49,6 +52,8 @@ architecture rtl of command_processor is parse_data, parse_get_cfg_hdr, parse_set_cfg_hdr, + parse_vwire_put, + reset_word1, crc, response ); @@ -61,13 +66,35 @@ architecture rtl of command_processor is ch_addr : std_logic_vector(31 downto 0); cfg_addr : std_logic_vector(15 downto 0); cfg_data : std_logic_vector(31 downto 0); + vwire_idx : std_logic_vector(7 downto 0); + vwire_dat : std_logic_vector(7 downto 0); + vwire_active : boolean; + vwire_wstrobe : std_logic; valid_redge : boolean; + reset_strobe : std_logic; hdr_idx : integer range 0 to 7; rem_addr_bytes : integer range 0 to 7; rem_data_bytes : integer range 0 to 2048; end record; - constant reg_reset : reg_type := (idle, false, false, rec_reset, (others => '0'), (others => '0'), (others => '0'), false, 0, 0, 0); + constant reg_reset : reg_type := ( + idle, + false, + false, + rec_reset, + (others => '0'), + (others => '0'), + (others => '0'), + (others => '0'), + (others => '0'), + false, + '0', + false, + '0', + 0, + 0, + 0 + ); type parse_info_t is record next_state : pkt_state_t; @@ -117,8 +144,15 @@ architecture rtl of command_processor is signal r, rin : reg_type; + attribute mark_debug of r : signal is "TRUE"; + begin + -- vwire interface + vwire_if.idx <= to_integer(r.vwire_idx); + vwire_if.dat <= r.vwire_dat; + vwire_if.wstrobe <= r.vwire_wstrobe; + host_to_sp_espi.data <= data_from_host.data; host_to_sp_espi.valid <= data_from_host.valid when r.cmd_header.opcode.value = opcode_put_pc and r.cmd_header.cycle_kind = message_with_data and r.state = parse_data else '0'; -- pass through the flash channel requests here @@ -148,6 +182,7 @@ begin v.crc_good := false; v.crc_bad := false; v.valid_redge := false; + v.vwire_wstrobe := '0'; -- Command parsing state machine case r.state is @@ -169,9 +204,9 @@ begin -- Opcodes with no additional data following, these -- can just go immediately to the CRC phase when opcode_get_status | - opcode_reset | opcode_get_pc | - opcode_get_flash_c => + opcode_get_flash_c | + opcode_get_vwire => v.state := crc; -- Config register opcodes, get and set when opcode_get_configuration => @@ -179,6 +214,10 @@ begin when opcode_set_configuration => v.state := parse_set_cfg_hdr; -- Opcodes with cycle type headers following + when opcode_reset => + v.state := reset_word1; + when opcode_put_vwire => + v.state := parse_vwire_put; when others => v.state := parse_common_cycle_header; end case; @@ -264,6 +303,19 @@ begin end if; end if; + when parse_vwire_put => + -- vwire put look like this assuming 1 count: + -- PUT_VWIRE => VWIRECOUNT, INDEX, DATA, CRC + if data_from_host.valid then + v.hdr_idx := v.hdr_idx + 1; + if r.hdr_idx = 1 then + v.vwire_idx := data_from_host.data; + elsif r.hdr_idx = 2 then + v.vwire_dat := data_from_host.data; + v.state := crc; + end if; + end if; + -- not much to do here. In theory, we have already indicated that the -- appropriate channel has room so we sit here until the data phase has -- finished. Muxes elsewhere should direct this datat to appropriate buffers @@ -275,6 +327,17 @@ begin if v.rem_data_bytes = 0 then v.state := crc; end if; + when reset_word1 => + v.reset_strobe := '0'; + if data_from_host.valid and data_from_host.ready then + if data_from_host.data = X"FF" then + v.reset_strobe := '1'; + end if; + end if; + if not chip_sel_active then + v.state := idle; + v.cmd_header := rec_reset; + end if; -- Yay! we made it to the last cmd byte, now we can check the CRC when crc => @@ -308,6 +371,8 @@ begin if not chip_sel_active then v.state := idle; v.cmd_header := rec_reset; + v.vwire_wstrobe := '1' when r.cmd_header.valid and r.vwire_active else '0'; + v.vwire_active := false; end if; when others => null; diff --git a/hdl/ip/vhd/espi/txn_layer/espi_base_types_pkg.vhd b/hdl/ip/vhd/espi/txn_layer/espi_base_types_pkg.vhd index 4206beb1..a4ab2932 100644 --- a/hdl/ip/vhd/espi/txn_layer/espi_base_types_pkg.vhd +++ b/hdl/ip/vhd/espi/txn_layer/espi_base_types_pkg.vhd @@ -108,6 +108,20 @@ package espi_base_types_pkg is rdata_valid : std_logic; end record; + type vwire_if_type is record + idx: integer range 0 to 255; + dat: std_logic_vector(7 downto 0); + wstrobe: std_logic; + end record; + + view vwire_regs_side of vwire_if_type is + idx: in; + dat: in; + wstrobe: in; + end view; + + alias vwire_cmd_side is vwire_regs_side'converse; + end package; diff --git a/hdl/ip/vhd/espi/txn_layer/response_processor.vhd b/hdl/ip/vhd/espi/txn_layer/response_processor.vhd index 06a5d653..805efe31 100644 --- a/hdl/ip/vhd/espi/txn_layer/response_processor.vhd +++ b/hdl/ip/vhd/espi/txn_layer/response_processor.vhd @@ -173,7 +173,14 @@ begin v.is_flash_response := false; v.state := RESPONSE_UART_HEADER; v.status := live_status; + when opcode_put_vwire => + v.state := STATUS; + v.status := live_status; when others => + -- Default hw to just return status with accept code + -- for now, but crash a simulation if we hit this + v.state := STATUS; + v.status := live_status; assert false report "Not implemented yet" severity FAILURE; diff --git a/hdl/ip/vhd/espi/txn_layer/txn_layer_top.vhd b/hdl/ip/vhd/espi/txn_layer/txn_layer_top.vhd index a1f547cb..62eafccd 100644 --- a/hdl/ip/vhd/espi/txn_layer/txn_layer_top.vhd +++ b/hdl/ip/vhd/espi/txn_layer/txn_layer_top.vhd @@ -20,8 +20,9 @@ entity txn_layer_top is reset : in std_logic; -- register layer connections - regs_if : view bus_side; + -- vwire channel connections + vwire_if : view vwire_cmd_side; -- flash channel status flash_np_free : in std_logic; flash_c_avail : in std_logic; @@ -36,6 +37,7 @@ entity txn_layer_top is pc_avail : in std_logic; np_free : in std_logic; np_avail: in std_logic; + vwire_avail : in std_logic; -- Link-layer connections is_crc_byte : out boolean; @@ -108,6 +110,7 @@ begin clk => clk, reset => reset, regs_if => regs_if, + vwire_if => vwire_if, flash_req => flash_req, host_to_sp_espi => host_to_sp_espi, running_crc => rx_running_crc, @@ -147,6 +150,7 @@ begin begin -- default to reset, override with other status bits live_status <= rec_reset; + live_status.vwire_avail <= vwire_avail; live_status.flash_c_avail <= flash_c_avail; live_status.flash_np_free <= flash_np_free; live_status.pc_avail <= pc_avail; diff --git a/hdl/ip/vhd/espi/vwire_channel/vwire_block.vhd b/hdl/ip/vhd/espi/vwire_channel/vwire_block.vhd new file mode 100644 index 00000000..4927859c --- /dev/null +++ b/hdl/ip/vhd/espi/vwire_channel/vwire_block.vhd @@ -0,0 +1,85 @@ +-- This Source Code Form is subject to the terms of the Mozilla Public +-- License, v. 2.0. If a copy of the MPL was not distributed with this +-- file, You can obtain one at https://mozilla.org/MPL/2.0/. +-- +-- Copyright 2024 Oxide Computer Company + +-- Note: Documentation can be rendered in VSCode using the TerosHDL +-- plugin: https://terostechnology.github.io/terosHDLdoc/ + +--! A verification component that acts as a qspi controller + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.numeric_std_unsigned.all; + +use work.vwire_regs_pkg.all; +use work.espi_base_types_pkg.all; + +entity vwire_block is + port ( + clk : in std_logic; + reset : in std_logic; + + espi_reset_flag: in std_logic; + + wire_tx_avail: out std_logic; + + vwire_if : view vwire_regs_side; + ); +end entity; + +architecture rtl of vwire_block is + + constant irq0 : irq0_type :=rec_reset; + constant irq1 : irq1_type :=rec_reset; + signal sys_event2 : sys_event2_type; + signal sys_event3 : sys_event3_type; + signal sys_event4 : sys_event4_type; + signal sys_event5 : sys_event5_type; + signal sys_event6 : sys_event6_type; + signal sys_event7 : sys_event7_type; + +begin + + -- For right now, since we're only supporting 1 count at a time, + -- we'd have to keep track of which of these wires need have changes + -- communicated and keep wire-tx-avail high until all of them have + -- been sent. We're not doing this right now. + + wire_tx_avail <= '0'; + + -- Write-side of the spec-defined registers + write_reg: process(clk, reset) + begin + if reset then + sys_event2 <= rec_reset; + sys_event3 <= rec_reset; + sys_event4 <= rec_reset; + sys_event5 <= rec_reset; + sys_event6 <= rec_reset; + sys_event7 <= rec_reset; + elsif rising_edge(clk) then + if vwire_if.idx = SYS_EVENT2_OFFSET and vwire_if.wstrobe = '1' then + sys_event2 <= unpack(vwire_if.dat); + end if; + if vwire_if.idx = SYS_EVENT3_OFFSET and vwire_if.wstrobe = '1' then + sys_event3 <= unpack(vwire_if.dat); + end if; + if vwire_if.idx = SYS_EVENT4_OFFSET and vwire_if.wstrobe = '1' then + sys_event4 <= unpack(vwire_if.dat); + end if; + if vwire_if.idx = SYS_EVENT5_OFFSET and vwire_if.wstrobe = '1' then + sys_event5 <= unpack(vwire_if.dat); + end if; + if vwire_if.idx = SYS_EVENT6_OFFSET and vwire_if.wstrobe = '1' then + sys_event6 <= unpack(vwire_if.dat); + end if; + if vwire_if.idx = SYS_EVENT7_OFFSET and vwire_if.wstrobe = '1' then + sys_event7 <= unpack(vwire_if.dat); + end if; + end if; + end process; + +end architecture; \ No newline at end of file diff --git a/hdl/ip/vhd/espi/vwire_channel/vwire_regs.rdl b/hdl/ip/vhd/espi/vwire_channel/vwire_regs.rdl new file mode 100644 index 00000000..3999ef14 --- /dev/null +++ b/hdl/ip/vhd/espi/vwire_channel/vwire_regs.rdl @@ -0,0 +1,300 @@ +// Copyright 2024 Oxide Computer Company +// This is SystemRDL description of the sw-accesible registers in the Gimlet +// Sequencer FPGA. + +addrmap vwire_regs { + name = "espi vwire registers"; + desc = "defined by the espi specification"; + + default regwidth = 8; + default sw = rw; + default hw = r; + + reg { + name = "IRQ0, slave to master, active high"; + + field { + desc = "Interrupt Level"; + } irq_level[7:7] = 0x00; + field { + desc = "Interrupt Line 0-127"; + } irq_line[6:0] = 0x00; + + } irq0 @0x0; + + reg { + name = "IRQ1, slave to master, active high"; + + field { + desc = "Interrupt Level"; + } irq_level[7:7] = 0x00; + field { + desc = "Interrupt Line 128-255"; + } irq_line[6:0] = 0x00; + + } irq1 @0x1; + + reg { + name = "System Event Idx 2, master to slave. Reset by eSPI reset"; + + field { + desc = "SLP_S5# Valid (bit[2])"; + } slp_s5_valid[6:6] = 0x00; + field { + desc = "SLP_S4# Valid (bit[1])"; + } slp_s4_valid[5:5] = 0x00; + field { + desc = "SLP_S3# Valid (bit[0])"; + } slp_s3_valid[4:4] = 0x00; + + field { + desc = "S5 SLeep control, active low. + Sent when the power to non-critical systems should be shut off in S5 (Soft Off) + "; + } slp_s5_l[2:2] = 0x00; + field { + desc = "S4 SLeep control, active low. + Sent when the power to non-critical systems should be shut off in S4 (Suspend to Disk). + "; + } slp_s4_l[1:1] = 0x00; + field { + desc = "S3 SLeep control, active low. + Sent when the power to non-critical systems should be shut off in S3 (Suspend to RAM). + "; + } slp_s3_l[0:0] = 0x00; + + } sys_event2 @0x2; + + reg { + name = "System Event Idx 3, master to slave. Reset by eSPI reset"; + + field { + desc = "OOB_RST_WARN Valid: This bit indicates the validity of OOB_RST_WARN virtual wire on bit[2]"; + } oob_rst_warn_valid[6:6] = 0x00; + + field { + desc = "PLTRST# Valid: This bit indicates the validity of PLTRST# virtual wire on bit[1]."; + } pltrst_valid[5:5] = 0x00; + + field { + desc = "SUS_STAT# Valid: This bit indicates the validity of SUS_STAT# virtual wire on bit[0]."; + } sus_stat_valid[4:4] = 0x00; + + field { + desc = "OOB Reset Warn: Sent by master just before the OOB processor is + about to enter reset. Upon receiving, the EC or BMC must flush and + quiesce its OOB Channel upstream request queues and assert + OOB_RST_ACK VWire upon completing all the outstanding + transactions. The master subsequently completes any outstanding + posted transactions or completions and then disables the OOB + Channel via a write to the slave's Configuration Register."; + } oob_reset_warn[2:2] = 0x00; + + field { + desc = "Platform Reset: Command to indicate Platform Reset assertion and + de-assertion. Active Low"; + } pltrst_l[1:1] = 0x00; + + field { + desc = "Suspend Status: Sent when the system will be entering a low + power state soon.. Active Low"; + } sus_stat_l[0:0] = 0x00; + } sys_event3 @0x3; + + reg { + name = "System Event Idx 4, master to slave. Reset by eSPI reset"; + + field { + desc = "PME# Valid: This bit indicates the validity of PME# virtual wire on bit[3]."; + } pme_valid[7:7] = 0x00; + + field { + desc = "WAKE# Valid: This bit indicates the validity of WAKE# virtual wire on bit[2]."; + } wake_valid[6:6] = 0x00; + + field { + desc = "OOB_RST_ACK Valid: This bit indicates the validity of OOB_RST_ACK virtual wire on bit[0]."; + } oob_rst_ack_valid[4:4] = 0x00; + + field { + desc = "CI Power Management Event: eSPI slaves generated PCI PME# + event. Used by the slave to wake the host from Sx through PCI + defined PME#. + If the event occurs while system is in S0, a SCI is generated instead. + Shared by multiple PCI devices on the platform. + Active Low + "; + } pme_l[3:3] = 0x01; + + field { + desc = "Wake#: Used by the slave to wake the Host from Sx on any event; + also general purpose event to wake on LID switch or AC insertion, + etc. It is used to generate an eSPI device specific non-PME# wake. + If the event occurs while system is in S0, a SCI is generated instead. + Active Low. Reset: inactive"; + } wake_l[2:2] = 0x01; + + field { + desc = "OOB Reset Acknowledge: Sent by slave in response to + OOB_RST_WARN virtual wire. Refer to the description of + OOB_RST_WARN for details. + Active high. Reset: inactive"; + } oob_rst_ack[0:0] = 0x00; + + } sys_event4 @0x4; + + reg { + name = "System Event Idx 5, slave to master. Reset by eSPI reset"; + + field { + desc = "SLAVE_BOOT_LOAD_STATUS Valid: This bit indicates the validity + of SLAVE_BOOT_LOAD_STATUS virtual wire on bit[3]."; + } slave_boot_load_status_valid[7:7] = 0x00; + field { + desc = "ERROR_NONFATAL Valid: This bit indicates the validity of + ERROR_NONFATAL virtual wire on bit[2]."; + } error_nonfatal_valid[6:6] = 0x00; + field { + desc = "ERROR_FATAL Valid: This bit indicates the validity of ERROR_FATAL + virtual wire on bit[1]."; + } error_fatal_valid[5:5] = 0x00; + field { + desc = "SLAVE_BOOT_LOAD_DONE Valid: This bit indicates the validity of + SLAVE_BOOT_LOAD_DONE virtual wire on bit[0]."; + } slave_boot_load_done_valid[4:4] = 0x00; + + field { + desc = "Slave Boot Load Status: Sent by EC or BMC upon completion of + Slave Boot Load from the master attached flash. + '0': The boot image is corrupted, incomplete or otherwise unusable. + '1': The boot code load was successful and that the integrity of the + image is intact, or the boot code load from master attached flash is + not required. + Note: The Slave_Boot_Load_Status must be sent in either the same + or a previous virtual wire message as the Slave_Boot_Load_Done. + Polarity: As defined above. + Reset: '0'."; + } slave_boot_load_status[3:3] = 0x00; + field { + desc = "Error Non-Fatal: Sent by slave when a non-fatal error is detected. + Note: Refer to Section 9.2 for the error conditions that Non-Fatal + Error virtual wire is signaled. + Polarity: Active high. + Reset: Inactive."; + } error_nonfatal[2:2] = 0x00; + field { + desc = "Error Fatal: Sent by slave when a fatal error is detected. + Note: Refer to Section 9.2 for the error conditions that Fatal Error + virtual wire is signaled. + Polarity: Active high. + Reset: Inactive."; + } error_fatal[1:1] = 0x00; + field { + desc = "Slave Boot Load Done: Sent when EC or BMC has completed its + boot process as indication to eSPI master to continue with the G3 to + S0 exit. eSPI master waits for the assertion of this virtual wire before + proceeding with the SLP_S5# deassertion. + Polarity: Active high. + Reset: Inactive. + "; + } slave_boot_load_done[0:0] = 0x00; + + + } sys_event5 @0x5; + + reg { + name = "System Event Idx 6, slave to master. Reset by PLTRST#"; + + field { + desc = "HOST_RST_ACK Valid: This bit indicates the validity of + HOST_RST_ACK virtual wire on bit[3]."; + } host_rst_ack_valid[7:7] = 0x00; + field { + desc = "RCIN# Valid: This bit indicates the validity of RCIN# virtual wire on + bit[2]."; + } rcin_valid[6:6] = 0x00; + field { + desc = "SMI# Valid: This bit indicates the validity of SMI# virtual wire on + bit[1]."; + } smi_valid[5:5] = 0x00; + field { + desc = "SCI# Valid: This bit indicates the validity of SCI# virtual wire on + bit[0]."; + } sci_valid[4:4] = 0x00; + + field { + desc = "Host Reset Acknowledge: Sent by slave in response to + HOST_RST_WARN virtual wire. Refer to the description of + HOST_RST_WARN for details. + Polarity: Active high. + Reset: Inactive."; + } host_reset_ack[3:3] = 0x00; + field { + desc = "Reset CPU INIT#: Sent to request CPU reset on behalf of the + keyboard controller. + Active Low. Reset: Inactive."; + } rcin_l[2:2] = 0x01; + field { + desc = "System Management Interrupt (SMI): Sent as general purpose + Polarity: Active low. + Reset: Inactive. + "; + } smi_l[1:1] = 0x01; + field { + desc = "System Controller Interrupt (SCI): Sent as general purpose alert + resulting in ACPI method being invoked by the OS. + Polarity: Active low. + Reset: Inactive. + "; + } sci_l[0:0] = 0x01; + } sys_event6 @0x6; + + reg { + name = "System Event Idx 7, slave to master. Reset by PLTRST#"; + + field { + desc = "NMIOUT# Valid: This bit indicates the validity of NMIOUT# virtual + wire on bit[2]. + "; + } nmiout_valid[6:6] = 0x00; + field { + desc = "SMIOUT# Valid: This bit indicates the validity of SMIOUT# virtual + wire on bit[1].. + "; + } smiout_valid[5:5] = 0x00; + field { + desc = "HOST_RST_WARN Valid: This bit indicates the validity of + HOST_RST_WARN virtual wire on bit[0]. + "; + } host_rst_warn_valid[4:4] = 0x00; + + field { + desc = "HOST_RST_WARN Valid: This bit indicates the validity of + HOST_RST_WARN virtual wire on bit[0]. + Polarity: Active low. + Reset: Inactive. + "; + } nmi_out_l[2:2] = 0x01; + field { + desc = "SMI Output: Sent by master as indication that SMI# event occurs. + The '0' and '1' on this virtual wire correspond to the assertion and + deassertion of the SMI# to CPU respectively. + Polarity: Active low. + Reset: Inactive. + "; + } smi_out_l[1:1] = 0x01; + field { + desc = "Host Reset Warn: Sent by master just before the Host is about to + enter reset. Upon receiving, the EC or BMC must flush and quiesce its + upstream Peripheral Channel request queues and assert + HOST_RST_ACK VWire upon completing all the outstanding + transactions. The master subsequently completes any outstanding + posted transactions or completions and then disables the Peripheral + Channel via a write to the slave's Configuration Register. + Polarity: Active High. + Reset: Inactive. + "; + } host_rst_warn[0:0] = 0x00; + + } sys_event7 @0x7; +}; \ No newline at end of file diff --git a/hdl/ip/vhd/vunit_components/qspi_controller/qspi_controller_vc.vhd b/hdl/ip/vhd/vunit_components/qspi_controller/qspi_controller_vc.vhd index 2355b7dc..b035b35c 100644 --- a/hdl/ip/vhd/vunit_components/qspi_controller/qspi_controller_vc.vhd +++ b/hdl/ip/vhd/vunit_components/qspi_controller/qspi_controller_vc.vhd @@ -151,15 +151,17 @@ begin state <= tx_phase; -- finish transmit phase wait until tx_rem_bytes = 0; - -- do the 2 cycle turn-around - state <= tar1; - wait until falling_edge(sclk); - state <= tar2; - wait until falling_edge(sclk); - -- finish the rx phase - state <= rx_phase; - wait until rx_rem_bytes = 0; - wait until falling_edge(sclk); + if rx_rem_bytes /= 0 then + -- do the 2 cycle turn-around + state <= tar1; + wait until falling_edge(sclk); + state <= tar2; + wait until falling_edge(sclk); + -- finish the rx phase + state <= rx_phase; + wait until rx_rem_bytes = 0; + wait until falling_edge(sclk); + end if; sclk_enable <= false; -- de-assert cs ss_n(0) <= '1'; diff --git a/hdl/ip/vhd/vunit_components/qspi_controller/qspi_vc_pkg.vhd b/hdl/ip/vhd/vunit_components/qspi_controller/qspi_vc_pkg.vhd index 337aa81f..9edde426 100644 --- a/hdl/ip/vhd/vunit_components/qspi_controller/qspi_vc_pkg.vhd +++ b/hdl/ip/vhd/vunit_components/qspi_controller/qspi_vc_pkg.vhd @@ -16,6 +16,7 @@ use vunit_lib.sync_pkg.all; package qspi_vc_pkg is -- Message defs + constant do_reset : msg_type_t := new_msg_type("do_reset"); constant set_period : msg_type_t := new_msg_type("set_period"); constant set_qspi_mode : msg_type_t := new_msg_type("set_qspi_mode"); constant enqueue_tx_bytes : msg_type_t := new_msg_type("enqueue_tx_bytes"); diff --git a/hdl/projects/grapefruit/BUCK b/hdl/projects/grapefruit/BUCK index a7a90e97..9bf441a4 100644 --- a/hdl/projects/grapefruit/BUCK +++ b/hdl/projects/grapefruit/BUCK @@ -89,7 +89,7 @@ vivado_bitstream( part= "xc7s100fgga484-1", constraints=glob(["*.xdc"]), pre_synth_tcl_files=glob(["*ip.tcl"]), - #post_synth_tcl_files=glob(["*ila.tcl"]), + post_synth_tcl_files=glob(["*ila.tcl"]), ) python_library( diff --git a/hdl/projects/grapefruit/fmc_ila.tcl b/hdl/projects/grapefruit/fmc_ila.tcl index 28078f2c..ea7c8fc8 100644 --- a/hdl/projects/grapefruit/fmc_ila.tcl +++ b/hdl/projects/grapefruit/fmc_ila.tcl @@ -1,5 +1,5 @@ create_debug_core u_ila_0 ila -set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] @@ -7,102 +7,99 @@ set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] -startgroup -set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ] -set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] -set_property ALL_PROBE_SAME_MU_CNT 2 [get_debug_cores u_ila_0 ] -endgroup -create_debug_core u_ila_1 ila -set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_1] -set_property C_TRIGIN_EN false [get_debug_cores u_ila_1] -set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1] -set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1] -set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1] -set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1] -set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1] -set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1] -startgroup -set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_1 ] -set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1 ] -set_property ALL_PROBE_SAME_MU_CNT 2 [get_debug_cores u_ila_1 ] -endgroup -connect_debug_port u_ila_0/clk [get_nets [list pll/inst/clk_125m ]] -connect_debug_port u_ila_1/clk [get_nets [list fmc_sp_to_fpga_clk_IBUF_BUFG ]] -set_property port_width 9 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/clk [get_nets [list pll/inst/clk_200m ]] +set_property port_width 4 [get_debug_ports u_ila_0/probe0] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {spi_nor_top_inst/link/tx_reg[0]} {spi_nor_top_inst/link/tx_reg[1]} {spi_nor_top_inst/link/tx_reg[2]} {spi_nor_top_inst/link/tx_reg[3]} {spi_nor_top_inst/link/tx_reg[4]} {spi_nor_top_inst/link/tx_reg[5]} {spi_nor_top_inst/link/tx_reg[6]} {spi_nor_top_inst/link/tx_reg[7]} {spi_nor_top_inst/link/tx_reg[8]} ]] +connect_debug_port u_ila_0/probe0 [get_nets [list {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/io[0]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/io[1]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/io[2]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/io[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 9 [get_debug_ports u_ila_0/probe1] +set_property port_width 4 [get_debug_ports u_ila_0/probe1] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {spi_nor_top_inst/link/rx_reg[0]} {spi_nor_top_inst/link/rx_reg[1]} {spi_nor_top_inst/link/rx_reg[2]} {spi_nor_top_inst/link/rx_reg[3]} {spi_nor_top_inst/link/rx_reg[4]} {spi_nor_top_inst/link/rx_reg[5]} {spi_nor_top_inst/link/rx_reg[6]} {spi_nor_top_inst/link/rx_reg[7]} {spi_nor_top_inst/link/rx_reg[8]} ]] +connect_debug_port u_ila_0/probe1 [get_nets [list {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/io_o[0]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/io_o[1]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/io_o[2]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/io_o[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 9 [get_debug_ports u_ila_0/probe2] +set_property port_width 4 [get_debug_ports u_ila_0/probe2] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[data_bytes][0]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[data_bytes][1]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[data_bytes][2]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[data_bytes][3]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[data_bytes][4]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[data_bytes][5]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[data_bytes][6]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[data_bytes][7]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[data_bytes][8]} ]] +connect_debug_port u_ila_0/probe2 [get_nets [list {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/io_oe[0]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/io_oe[1]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/io_oe[2]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/io_oe[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe3] +set_property port_width 9 [get_debug_ports u_ila_0/probe3] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][0]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][1]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][2]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][3]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][4]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][5]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][6]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][7]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][8]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][9]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][10]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][11]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][12]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][13]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][14]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][15]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][16]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][17]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][18]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][19]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][20]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][21]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][22]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][23]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][24]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][25]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][26]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][27]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][28]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][29]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][30]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[addr][31]} ]] +connect_debug_port u_ila_0/probe3 [get_nets [list {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/tx_reg[0]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/tx_reg[1]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/tx_reg[2]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/tx_reg[3]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/tx_reg[4]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/tx_reg[5]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/tx_reg[6]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/tx_reg[7]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/tx_reg[8]} ]] create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe4] +set_property port_width 9 [get_debug_ports u_ila_0/probe4] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {spi_nor_top_inst/spi_txn_mgr_inst/r[txn][data_mode][0]} {spi_nor_top_inst/spi_txn_mgr_inst/r[txn][data_mode][1]} ]] +connect_debug_port u_ila_0/probe4 [get_nets [list {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/rx_reg[0]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/rx_reg[1]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/rx_reg[2]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/rx_reg[3]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/rx_reg[4]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/rx_reg[5]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/rx_reg[6]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/rx_reg[7]} {espi_target_top_inst/link_layer_top_inst/qspi_link_layer/rx_reg[8]} ]] create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe5] +set_property port_width 16 [get_debug_ports u_ila_0/probe5] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {spi_nor_top_inst/spi_txn_mgr_inst/r[txn][data_kind][0]} {spi_nor_top_inst/spi_txn_mgr_inst/r[txn][data_kind][1]} ]] +connect_debug_port u_ila_0/probe5 [get_nets [list {espi_target_top_inst/transaction/command_processor_inst/r[cfg_addr][0]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_addr][1]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_addr][2]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_addr][3]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_addr][4]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_addr][5]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_addr][6]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_addr][7]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_addr][8]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_addr][9]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_addr][10]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_addr][11]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_addr][12]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_addr][13]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_addr][14]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_addr][15]} ]] create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe6] +set_property port_width 32 [get_debug_ports u_ila_0/probe6] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {spi_nor_top_inst/spi_txn_mgr_inst/r[txn][addr_kind][0]} {spi_nor_top_inst/spi_txn_mgr_inst/r[txn][addr_kind][1]} ]] +connect_debug_port u_ila_0/probe6 [get_nets [list {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][0]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][1]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][2]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][3]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][4]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][5]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][6]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][7]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][8]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][9]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][10]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][11]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][12]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][13]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][14]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][15]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][16]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][17]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][18]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][19]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][20]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][21]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][22]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][23]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][24]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][25]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][26]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][27]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][28]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][29]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][30]} {espi_target_top_inst/transaction/command_processor_inst/r[cfg_data][31]} ]] create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe7] +set_property port_width 32 [get_debug_ports u_ila_0/probe7] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list {spi_nor_top_inst/spi_txn_mgr_inst/r[state][0]} {spi_nor_top_inst/spi_txn_mgr_inst/r[state][1]} {spi_nor_top_inst/spi_txn_mgr_inst/r[state][2]} ]] +connect_debug_port u_ila_0/probe7 [get_nets [list {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][0]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][1]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][2]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][3]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][4]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][5]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][6]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][7]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][8]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][9]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][10]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][11]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][12]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][13]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][14]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][15]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][16]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][17]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][18]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][19]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][20]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][21]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][22]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][23]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][24]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][25]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][26]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][27]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][28]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][29]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][30]} {espi_target_top_inst/transaction/command_processor_inst/r[ch_addr][31]} ]] create_debug_port u_ila_0 probe -set_property port_width 10 [get_debug_ports u_ila_0/probe8] +set_property port_width 8 [get_debug_ports u_ila_0/probe8] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list {spi_nor_top_inst/spi_txn_mgr_inst/r[counter][0]} {spi_nor_top_inst/spi_txn_mgr_inst/r[counter][1]} {spi_nor_top_inst/spi_txn_mgr_inst/r[counter][2]} {spi_nor_top_inst/spi_txn_mgr_inst/r[counter][3]} {spi_nor_top_inst/spi_txn_mgr_inst/r[counter][4]} {spi_nor_top_inst/spi_txn_mgr_inst/r[counter][5]} {spi_nor_top_inst/spi_txn_mgr_inst/r[counter][6]} {spi_nor_top_inst/spi_txn_mgr_inst/r[counter][7]} {spi_nor_top_inst/spi_txn_mgr_inst/r[counter][8]} {spi_nor_top_inst/spi_txn_mgr_inst/r[counter][9]} ]] +connect_debug_port u_ila_0/probe8 [get_nets [list {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][opcode][value][0]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][opcode][value][1]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][opcode][value][2]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][opcode][value][3]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][opcode][value][4]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][opcode][value][5]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][opcode][value][6]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][opcode][value][7]} ]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe9] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[instr][0]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[instr][1]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[instr][2]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[instr][3]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[instr][4]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[instr][5]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[instr][6]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[instr][7]} ]] +connect_debug_port u_ila_0/probe9 [get_nets [list {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][cycle_kind][0]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][cycle_kind][1]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][cycle_kind][2]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][cycle_kind][3]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][cycle_kind][4]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][cycle_kind][5]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][cycle_kind][6]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][cycle_kind][7]} ]] create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe10] +set_property port_width 12 [get_debug_ports u_ila_0/probe10] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] -connect_debug_port u_ila_0/probe10 [get_nets [list {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[dummy_cycles][0]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[dummy_cycles][1]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[dummy_cycles][2]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[dummy_cycles][3]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[dummy_cycles][4]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[dummy_cycles][5]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[dummy_cycles][6]} {spi_nor_top_inst/spi_txn_mgr_inst/spi_cmd[dummy_cycles][7]} ]] +connect_debug_port u_ila_0/probe10 [get_nets [list {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][length][0]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][length][1]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][length][2]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][length][3]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][length][4]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][length][5]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][length][6]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][length][7]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][length][8]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][length][9]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][length][10]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][length][11]} ]] create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe11] +set_property port_width 4 [get_debug_ports u_ila_0/probe11] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] -connect_debug_port u_ila_0/probe11 [get_nets [list {spi_nor_top_inst/link/dbg_sclk_cnts[0]} {spi_nor_top_inst/link/dbg_sclk_cnts[1]} {spi_nor_top_inst/link/dbg_sclk_cnts[2]} {spi_nor_top_inst/link/dbg_sclk_cnts[3]} {spi_nor_top_inst/link/dbg_sclk_cnts[4]} {spi_nor_top_inst/link/dbg_sclk_cnts[5]} {spi_nor_top_inst/link/dbg_sclk_cnts[6]} {spi_nor_top_inst/link/dbg_sclk_cnts[7]} {spi_nor_top_inst/link/dbg_sclk_cnts[8]} {spi_nor_top_inst/link/dbg_sclk_cnts[9]} {spi_nor_top_inst/link/dbg_sclk_cnts[10]} {spi_nor_top_inst/link/dbg_sclk_cnts[11]} {spi_nor_top_inst/link/dbg_sclk_cnts[12]} {spi_nor_top_inst/link/dbg_sclk_cnts[13]} {spi_nor_top_inst/link/dbg_sclk_cnts[14]} {spi_nor_top_inst/link/dbg_sclk_cnts[15]} {spi_nor_top_inst/link/dbg_sclk_cnts[16]} {spi_nor_top_inst/link/dbg_sclk_cnts[17]} {spi_nor_top_inst/link/dbg_sclk_cnts[18]} {spi_nor_top_inst/link/dbg_sclk_cnts[19]} {spi_nor_top_inst/link/dbg_sclk_cnts[20]} {spi_nor_top_inst/link/dbg_sclk_cnts[21]} {spi_nor_top_inst/link/dbg_sclk_cnts[22]} {spi_nor_top_inst/link/dbg_sclk_cnts[23]} {spi_nor_top_inst/link/dbg_sclk_cnts[24]} {spi_nor_top_inst/link/dbg_sclk_cnts[25]} {spi_nor_top_inst/link/dbg_sclk_cnts[26]} {spi_nor_top_inst/link/dbg_sclk_cnts[27]} {spi_nor_top_inst/link/dbg_sclk_cnts[28]} {spi_nor_top_inst/link/dbg_sclk_cnts[29]} {spi_nor_top_inst/link/dbg_sclk_cnts[30]} {spi_nor_top_inst/link/dbg_sclk_cnts[31]} ]] +connect_debug_port u_ila_0/probe11 [get_nets [list {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][tag][0]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][tag][1]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][tag][2]} {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][tag][3]} ]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe12] +set_property port_width 3 [get_debug_ports u_ila_0/probe12] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] -connect_debug_port u_ila_0/probe12 [get_nets [list {spi_nor_top_inst/link/io[0]} {spi_nor_top_inst/link/io[1]} {spi_nor_top_inst/link/io[2]} {spi_nor_top_inst/link/io[3]} ]] +connect_debug_port u_ila_0/probe12 [get_nets [list {espi_target_top_inst/transaction/command_processor_inst/r[hdr_idx][0]} {espi_target_top_inst/transaction/command_processor_inst/r[hdr_idx][1]} {espi_target_top_inst/transaction/command_processor_inst/r[hdr_idx][2]} ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe13] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] -connect_debug_port u_ila_0/probe13 [get_nets [list {spi_nor_top_inst/link/io_o[0]} {spi_nor_top_inst/link/io_o[1]} {spi_nor_top_inst/link/io_o[3]} ]] +connect_debug_port u_ila_0/probe13 [get_nets [list {espi_target_top_inst/transaction/command_processor_inst/r[rem_addr_bytes][0]} {espi_target_top_inst/transaction/command_processor_inst/r[rem_addr_bytes][1]} {espi_target_top_inst/transaction/command_processor_inst/r[rem_addr_bytes][2]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe14] +set_property port_width 12 [get_debug_ports u_ila_0/probe14] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] -connect_debug_port u_ila_0/probe14 [get_nets [list {spi_nor_top_inst/spi_txn_mgr_inst/r[csn]} ]] +connect_debug_port u_ila_0/probe14 [get_nets [list {espi_target_top_inst/transaction/command_processor_inst/r[rem_data_bytes][0]} {espi_target_top_inst/transaction/command_processor_inst/r[rem_data_bytes][1]} {espi_target_top_inst/transaction/command_processor_inst/r[rem_data_bytes][2]} {espi_target_top_inst/transaction/command_processor_inst/r[rem_data_bytes][3]} {espi_target_top_inst/transaction/command_processor_inst/r[rem_data_bytes][4]} {espi_target_top_inst/transaction/command_processor_inst/r[rem_data_bytes][5]} {espi_target_top_inst/transaction/command_processor_inst/r[rem_data_bytes][6]} {espi_target_top_inst/transaction/command_processor_inst/r[rem_data_bytes][7]} {espi_target_top_inst/transaction/command_processor_inst/r[rem_data_bytes][8]} {espi_target_top_inst/transaction/command_processor_inst/r[rem_data_bytes][9]} {espi_target_top_inst/transaction/command_processor_inst/r[rem_data_bytes][10]} {espi_target_top_inst/transaction/command_processor_inst/r[rem_data_bytes][11]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe15] +set_property port_width 4 [get_debug_ports u_ila_0/probe15] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list {spi_nor_top_inst/spi_txn_mgr_inst/r[txn][uses_dummys]} ]] +connect_debug_port u_ila_0/probe15 [get_nets [list {espi_target_top_inst/transaction/command_processor_inst/r[state][0]} {espi_target_top_inst/transaction/command_processor_inst/r[state][1]} {espi_target_top_inst/transaction/command_processor_inst/r[state][2]} {espi_target_top_inst/transaction/command_processor_inst/r[state][3]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe16] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list spi_nor_top_inst/tx_byte_done ]] -set_property port_width 4 [get_debug_ports u_ila_1/probe0] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0] -connect_debug_port u_ila_1/probe0 [get_nets [list {stm32h7_fmc_target_inst/fmc_state[0]} {stm32h7_fmc_target_inst/fmc_state[1]} {stm32h7_fmc_target_inst/fmc_state[2]} {stm32h7_fmc_target_inst/fmc_state[3]} ]] -create_debug_port u_ila_1 probe -set_property port_width 26 [get_debug_ports u_ila_1/probe1] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1] -connect_debug_port u_ila_1/probe1 [get_nets [list {stm32h7_fmc_target_inst/txn[addr][0]} {stm32h7_fmc_target_inst/txn[addr][1]} {stm32h7_fmc_target_inst/txn[addr][2]} {stm32h7_fmc_target_inst/txn[addr][3]} {stm32h7_fmc_target_inst/txn[addr][4]} {stm32h7_fmc_target_inst/txn[addr][5]} {stm32h7_fmc_target_inst/txn[addr][6]} {stm32h7_fmc_target_inst/txn[addr][7]} {stm32h7_fmc_target_inst/txn[addr][8]} {stm32h7_fmc_target_inst/txn[addr][9]} {stm32h7_fmc_target_inst/txn[addr][10]} {stm32h7_fmc_target_inst/txn[addr][11]} {stm32h7_fmc_target_inst/txn[addr][12]} {stm32h7_fmc_target_inst/txn[addr][13]} {stm32h7_fmc_target_inst/txn[addr][14]} {stm32h7_fmc_target_inst/txn[addr][15]} {stm32h7_fmc_target_inst/txn[addr][16]} {stm32h7_fmc_target_inst/txn[addr][17]} {stm32h7_fmc_target_inst/txn[addr][18]} {stm32h7_fmc_target_inst/txn[addr][19]} {stm32h7_fmc_target_inst/txn[addr][20]} {stm32h7_fmc_target_inst/txn[addr][21]} {stm32h7_fmc_target_inst/txn[addr][22]} {stm32h7_fmc_target_inst/txn[addr][23]} {stm32h7_fmc_target_inst/txn[addr][24]} {stm32h7_fmc_target_inst/txn[addr][25]} ]] -create_debug_port u_ila_1 probe -set_property port_width 1 [get_debug_ports u_ila_1/probe2] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2] -connect_debug_port u_ila_1/probe2 [get_nets [list {stm32h7_fmc_target_inst/txn[read_not_write]} ]] \ No newline at end of file +connect_debug_port u_ila_0/probe16 [get_nets [list espi_target_top_inst/link_layer_top_inst/qspi_link_layer/cs_n ]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe17] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] +connect_debug_port u_ila_0/probe17 [get_nets [list {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][opcode][valid]} ]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe18] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] +connect_debug_port u_ila_0/probe18 [get_nets [list {espi_target_top_inst/transaction/command_processor_inst/r[cmd_header][valid]} ]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe19] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] +connect_debug_port u_ila_0/probe19 [get_nets [list {espi_target_top_inst/transaction/command_processor_inst/r[crc_bad]} ]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe20] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] +connect_debug_port u_ila_0/probe20 [get_nets [list {espi_target_top_inst/transaction/command_processor_inst/r[crc_good]} ]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe21] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] +connect_debug_port u_ila_0/probe21 [get_nets [list {espi_target_top_inst/transaction/command_processor_inst/r[reset_strobe]} ]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe22] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] +connect_debug_port u_ila_0/probe22 [get_nets [list {espi_target_top_inst/transaction/command_processor_inst/r[valid_redge]} ]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe23] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] +connect_debug_port u_ila_0/probe23 [get_nets [list espi_target_top_inst/link_layer_top_inst/qspi_link_layer/sclk ]] \ No newline at end of file diff --git a/hdl/projects/grapefruit/grapefruit_pins.xdc b/hdl/projects/grapefruit/grapefruit_pins.xdc index 4a96f235..2bbd7fe5 100644 --- a/hdl/projects/grapefruit/grapefruit_pins.xdc +++ b/hdl/projects/grapefruit/grapefruit_pins.xdc @@ -117,13 +117,18 @@ set_property -dict { PACKAGE_PIN W1 IOSTANDARD LVCMOS18 } [get_ports { fpga_spar set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS18 } [get_ports { fpga_spare_1v8[1] }]; set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS18 } [get_ports { fpga_spare_1v8[0] }]; set_property -dict { PACKAGE_PIN Y1 IOSTANDARD LVCMOS18 } [get_ports { espi_hpm_to_scm_reset_l }]; -set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS18 } [get_ports { espi_scm_to_hpm_alert_l }]; +# espi boot wants alert to be data[1], but it's annoying to carry that rename through the desig +# so we swapped them here +#set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS18 } [get_ports { espi_scm_to_hpm_alert_l }]; +set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS18 } [get_ports { espi_scm_to_hpm_alert_l }]; set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS18 } [get_ports { espi_hpm_to_scm_cs_l }]; set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS18 } [get_ports { espi_hpm_to_scm_clk }]; set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS18 } [get_ports { espi_hpm_to_scm_dat[3] }]; set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS18 } [get_ports { espi_hpm_to_scm_dat[2] }]; -set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS18 } [get_ports { espi_hpm_to_scm_dat[1] }]; +#set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS18 } [get_ports { espi_hpm_to_scm_dat[1] }]; +set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS18 } [get_ports { espi_hpm_to_scm_dat[1] }]; set_property -dict { PACKAGE_PIN Y3 IOSTANDARD LVCMOS18 } [get_ports { espi_hpm_to_scm_dat[0] }]; +set_property SLEW FAST [get_ports espi_hpm_to_scm_dat[*]] set_property -dict { PACKAGE_PIN AA6 IOSTANDARD LVCMOS18 } [get_ports { i3c_hpm_to_scm_dimm0_abcdef_scl }]; set_property -dict { PACKAGE_PIN AB6 IOSTANDARD LVCMOS18 } [get_ports { i3c_hpm_to_scm_dimm0_abcdef_sda }]; set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS18 } [get_ports { i3c_hpm_to_scm_dimm0_ghijkl_scl }]; diff --git a/hdl/projects/grapefruit/grapefruit_timing.xdc b/hdl/projects/grapefruit/grapefruit_timing.xdc index cf122aff..c067faa9 100644 --- a/hdl/projects/grapefruit/grapefruit_timing.xdc +++ b/hdl/projects/grapefruit/grapefruit_timing.xdc @@ -10,7 +10,7 @@ set_clock_groups -asynchronous -group {fmc_clk_pin fmc_virt_clk} -group {clk_125 # ####################### -# FMC to FPGA inputs first +# FMC Interface # ####################### # FPGA's input delays have to be low enough that they don't run into the uncertainty region due to any possible skew. @@ -67,4 +67,18 @@ set_output_delay -clock fmc_virt_clk -min 0.830 [get_ports fmc_sp_to_fpga_da[*]] set_multicycle_path -from [get_pins {stm32h7_fmc_target_inst/data_out*/C}] -to [get_ports {fmc_sp_to_fpga_da[*]}] -setup 2 set_multicycle_path -from [get_pins {stm32h7_fmc_target_inst/data_out*/C}] -to [get_ports {fmc_sp_to_fpga_da[*]}] -hold 1 set_multicycle_path -from [get_pins {stm32h7_fmc_target_inst/data_out_en_reg*/C}] -to [get_ports {fmc_sp_to_fpga_da[*]}] -setup 2 -set_multicycle_path -from [get_pins {stm32h7_fmc_target_inst/data_out_en_reg*/C}] -to [get_ports {fmc_sp_to_fpga_da[*]}] -hold 1 \ No newline at end of file +set_multicycle_path -from [get_pins {stm32h7_fmc_target_inst/data_out_en_reg*/C}] -to [get_ports {fmc_sp_to_fpga_da[*]}] -hold 1 + +# ####################### +# FMC Interface +# ####################### + +# in delay max = tco_ext to max delay ext to fpga +# in delay min = minTco_ext to min delay ext to fpga + + +# Create a virtual clock, to represent the source clock of the eSPI interface +#create_clock -name espi_virt_clk -period 50.000; # 20 MHz clock + +#set_output_delay -clock espi_virt_clk -max 3.8 [get_ports espi_hpm_to_scm_dat[*]] +#set_output_delay -clock espi_virt_clk -min 0.8 [get_ports espi_hpm_to_scm_dat[*]] diff --git a/hdl/projects/grapefruit/grapefruit_top.vhd b/hdl/projects/grapefruit/grapefruit_top.vhd index 65c47b8a..cee41b7d 100644 --- a/hdl/projects/grapefruit/grapefruit_top.vhd +++ b/hdl/projects/grapefruit/grapefruit_top.vhd @@ -235,7 +235,6 @@ architecture rtl of grapefruit_top is signal console_to_sp_tx_valid : std_logic; signal espi_io_o : std_logic_vector(3 downto 0); signal espi_io_oe : std_logic_vector(3 downto 0); - signal espi_io_post_mux_o : std_logic_vector(3 downto 0); signal ipcc_sp_to_fpga_data: std_logic; signal ipcc_fpga_to_sp_data: std_logic; signal ipcc_sp_to_fpga_cts_l: std_logic; @@ -243,18 +242,13 @@ architecture rtl of grapefruit_top is constant ipcc_dbg_en : std_logic := '0'; signal hpm_to_scm_stby_rdy_syncd : std_logic; signal sp5_owns_flash : std_logic; - signal espi_cs_l : std_logic; - signal espi_io_pins_oe : std_logic_vector(3 downto 0); - signal spi_fpga_to_flash_dat_pins_oe : std_logic_vector(3 downto 0); - signal spi_nor_passthru : std_logic; - signal spi_nor_block_cs_l : std_logic; - signal spi_nor_block_clk : std_logic; signal spi_nor_block_data_o : std_logic_vector(3 downto 0); signal spi_nor_block_data_oe : std_logic_vector(3 downto 0); - signal spi_nor_block_data_post_mux_o : std_logic_vector(3 downto 0); begin + espi_scm_to_hpm_alert_l <= 'Z'; + pll: entity work.gfruit_pll port map ( clk_50m => clk, @@ -331,7 +325,7 @@ begin clk => clk_125m, reset => reset_125m, axi_if => responders(0), - spi_nor_passthru => spi_nor_passthru + spi_nor_passthru => open ); spi_nor_top_inst: entity work.spi_nor_top @@ -339,8 +333,8 @@ begin clk => clk_125m, reset => reset_125m, axi_if => responders(1), - cs_n => spi_nor_block_cs_l, - sclk => spi_nor_block_clk, + cs_n => spi_fpga_to_flash_cs_l, + sclk => spi_fpga_to_flash_clk, io => spi_fpga_to_flash_dat, io_o => spi_nor_block_data_o, io_oe => spi_nor_block_data_oe, @@ -361,7 +355,7 @@ begin showahead_mode => true ) port map( - wclk => clk_125m, -- eSPI clock + wclk => clk_200m, -- eSPI clock reset => reset_125m, write_en => flash_cfifo_write, wdata => flash_cfifo_data, @@ -387,7 +381,7 @@ begin wdata => espi_data_fifo_wdata, wfull => open, wusedwds => open, - rclk => clk_125m, -- espi clock + rclk => clk_200m, -- espi clock rdata => flash_rfifo_data, rdreq => flash_rfifo_rdack, rempty => flash_rfifo_rempty, @@ -395,14 +389,15 @@ begin ); -- eSPI - -- ideally we'll want to be in 200MHz but we're going - -- to get it working in 125MHz first + -- ideally we'll want to be in 200MHz but we're going espi_target_top_inst: entity work.espi_target_top port map( - clk => clk_125m, - reset => reset_125m, + clk => clk_200m, + reset => reset_200m, + axi_clk => clk_125m, + axi_reset => reset_125m, axi_if => responders(2), - cs_n => espi_cs_l, + cs_n => espi_hpm_to_scm_cs_l, sclk => espi_hpm_to_scm_clk, io => espi_hpm_to_scm_dat, io_o => espi_io_o, @@ -508,46 +503,15 @@ begin tx_ready => console_from_sp_rx_ready ); - -- SPI passthru mux - -- For bring-up we're supporting a few options, regardless we want hubris to have the flash - -- when it owns the flash. - process(all) - begin - if spi_nor_passthru = '1' and sp5_owns_flash = '1' then - -- SPI NOR control pins driven from the QSPI pins from the SP5 - -- as passthru - spi_fpga_to_flash_cs_l <= espi_hpm_to_scm_cs_l; - spi_fpga_to_flash_clk <= espi_hpm_to_scm_clk; - espi_io_pins_oe <= (1 => '1', others => '0'); - spi_fpga_to_flash_dat_pins_oe <= (0 => '1', others => '0'); - espi_cs_l <= '1'; - spi_nor_block_data_post_mux_o(0) <= espi_hpm_to_scm_dat(0); - spi_nor_block_data_post_mux_o(3 downto 2) <= (others => '1'); - espi_io_post_mux_o(1) <= spi_fpga_to_flash_dat(1); - espi_io_post_mux_o(0) <= '1'; - espi_io_post_mux_o(3 downto 2) <= (others => '1'); - else - -- Not in passthru mode - -- SPI NOR control pins driven from spi-nor hw block - spi_fpga_to_flash_cs_l <= spi_nor_block_cs_l; - spi_fpga_to_flash_clk <= spi_nor_block_clk; - spi_fpga_to_flash_dat_pins_oe <= spi_nor_block_data_oe; - spi_nor_block_data_post_mux_o <= spi_nor_block_data_o; - --eSPI pins driven from the eSPI block - espi_cs_l <= espi_hpm_to_scm_cs_l; - espi_io_pins_oe <= espi_io_oe; - espi_io_post_mux_o <= espi_io_o; - end if; - end process; -- espi and spiNor tris buffer process(all) begin for i in 0 to 3 loop - espi_hpm_to_scm_dat(i) <= espi_io_post_mux_o(i) when espi_io_pins_oe(i) = '1' else 'Z'; + espi_hpm_to_scm_dat(i) <= espi_io_o(i) when espi_io_oe(i) = '1' else 'Z'; end loop; for i in 0 to 3 loop - spi_fpga_to_flash_dat(i) <= spi_nor_block_data_post_mux_o(i) when spi_fpga_to_flash_dat_pins_oe(i) = '1' else 'Z'; + spi_fpga_to_flash_dat(i) <= spi_nor_block_data_o(i) when spi_nor_block_data_oe(i) = '1' else 'Z'; end loop; end process; diff --git a/tight_setup_hold_pins.txt b/tight_setup_hold_pins.txt new file mode 100644 index 00000000..5262dbd2 --- /dev/null +++ b/tight_setup_hold_pins.txt @@ -0,0 +1,24 @@ ++=====================+=====================+=====================================================================================================================================================================+ +| Launch Setup Clock | Launch Hold Clock | Pin | ++=====================+=====================+=====================================================================================================================================================================+ +| clk_200m_gfruit_pll | clk_200m_gfruit_pll | sp_uart1/tx_fifo/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg/D | +| clk_125m_gfruit_pll | clk_125m_gfruit_pll | espi_target_top_inst/uart_channel_top_inst/to_host_tx_fifo/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/count_value_i_reg[4]/D | +| clk_125m_gfruit_pll | clk_125m_gfruit_pll | espi_target_top_inst/uart_channel_top_inst/to_host_tx_fifo/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/count_value_i_reg[3]/D | +| clk_125m_gfruit_pll | clk_125m_gfruit_pll | espi_target_top_inst/uart_channel_top_inst/to_host_tx_fifo/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/count_value_i_reg[1]/D | +| clk_125m_gfruit_pll | clk_125m_gfruit_pll | espi_target_top_inst/uart_channel_top_inst/to_host_tx_fifo/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/count_value_i_reg[2]/D | +| clk_125m_gfruit_pll | clk_125m_gfruit_pll | espi_target_top_inst/uart_channel_top_inst/to_host_tx_fifo/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg/D | +| clk_125m_gfruit_pll | clk_125m_gfruit_pll | espi_target_top_inst/uart_channel_top_inst/to_host_tx_fifo/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp2_inst/count_value_i_reg[0]/D | +| clk_125m_gfruit_pll | clk_125m_gfruit_pll | espi_target_top_inst/uart_channel_top_inst/to_host_tx_fifo/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrp_inst/count_value_i_reg[2]/D | +| clk_125m_gfruit_pll | clk_125m_gfruit_pll | espi_target_top_inst/uart_channel_top_inst/to_host_tx_fifo/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrp_inst/count_value_i_reg[3]/D | +| clk_125m_gfruit_pll | clk_125m_gfruit_pll | espi_target_top_inst/uart_channel_top_inst/to_host_tx_fifo/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrp_inst/count_value_i_reg[1]/D | +| clk_125m_gfruit_pll | clk_125m_gfruit_pll | espi_target_top_inst/uart_channel_top_inst/to_host_tx_fifo/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrp_inst/count_value_i_reg[0]/D | +| clk_125m_gfruit_pll | clk_125m_gfruit_pll | espi_target_top_inst/uart_channel_top_inst/to_host_tx_fifo/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i_reg[1]/D | +| clk_200m_gfruit_pll | clk_200m_gfruit_pll | sp_uart1/rx_fifo/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_pf_ic_rc.ram_empty_i_reg/D | +| clk_125m_gfruit_pll | clk_125m_gfruit_pll | espi_target_top_inst/uart_channel_top_inst/to_host_tx_fifo/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/wrpp1_inst/count_value_i_reg[0]/D | +| clk_125m_gfruit_pll | clk_125m_gfruit_pll | espi_target_top_inst/uart_channel_top_inst/to_host_tx_fifo/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gof.overflow_i_reg/D | +| clk_200m_gfruit_pll | clk_200m_gfruit_pll | sp_uart1/rx_fifo/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_fwft.rdpp1_inst/count_value_i_reg[0]/D | +| clk_200m_gfruit_pll | clk_200m_gfruit_pll | sp_uart1/rx_fifo/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/guf.underflow_i_reg/D | +| clk_125m_gfruit_pll | clk_125m_gfruit_pll | espi_target_top_inst/link_layer_top_inst/debug_link_layer/r_reg[cntr][3]/D | +| clk_200m_gfruit_pll | clk_200m_gfruit_pll | sp_uart1/rx_fifo/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1]/D | +| clk_200m_gfruit_pll | clk_200m_gfruit_pll | sp_uart1/rx_fifo/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[0]/D | ++---------------------+---------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ diff --git a/tools/speeker/espi_mux.py b/tools/speeker/espi_mux.py new file mode 100644 index 00000000..d588829a --- /dev/null +++ b/tools/speeker/espi_mux.py @@ -0,0 +1,40 @@ +# This Source Code Form is subject to the terms of the Mozilla Public +# License, v. 2.0. If a copy of the MPL was not distributed with this +# file, You can obtain one at https://mozilla.org/MPL/2.0/. +# +# Copyright 2024 Oxide Computer Company + +# Control ruby power from gfruit over sgpio + +target = "fe80::0c1d:62ff:fee0:308f" +port = 11114 +ifname = "eno1" + +import udp_if +import time +import argparse + +spi_cr = 0x60000100 +sp5_owns_flash = (1 << 31) + +def to_sp5(args): + con = udp_if.UDPMem(target, ifname, port) + con.write32(spi_cr, sp5_owns_flash) + +def to_sp(args): + con = udp_if.UDPMem(target, ifname, port) + con.write32(spi_cr, 0) + + +# create the top-level parser +parser = argparse.ArgumentParser(prog='espi_mux', description='espi mux control') +subparsers = parser.add_subparsers(help='sub-command help') + +format_parser = subparsers.add_parser('on', help='format help') +format_parser.set_defaults(func=to_sp5) + +format_parser = subparsers.add_parser('off', help='format help') +format_parser.set_defaults(func=to_sp) + +args = parser.parse_args() +args.func(args) \ No newline at end of file diff --git a/tools/speeker/gfruit_mux.py b/tools/speeker/gfruit_mux.py index c99a05f4..2a64a971 100644 --- a/tools/speeker/gfruit_mux.py +++ b/tools/speeker/gfruit_mux.py @@ -15,7 +15,7 @@ SGPIO_0_REG = 0x60000300 SGPIO_1_REG = 0x60000308 -ctrl_0s = [1 << 11, 1 << 8, 1 << 7, 1 << 6, 1 << 5, 1 << 4, 1 << 3, 1 << 2] +sp5_owns_flash = 1 << 31 ctrl_1s = [1 << 9, 1 << 8, 1 << 7, 1 << 6, 1 << 5]