From 3cc91f6507a7c648d4ec98f4f1b2055dfc89d8d5 Mon Sep 17 00:00:00 2001 From: Nathanael Huffman Date: Fri, 11 Oct 2024 15:04:36 -0500 Subject: [PATCH] GHA and colo runner --- .github/workflows/build.yml | 0 .github/workflows/vunit.yml | 18 +++++ .gitignore | 3 + README.md | 12 ++++ hdl/ip/vhd/espi/sims/espi_tb.vhd | 3 +- hdl/ip/vhd/ip_tests/BUCK | 15 ----- hdl/ip/vhd/memories/BUCK | 1 + hdl/ip/vhd/vunit_components/BUCK | 7 -- .../qspi_controller/qspi_vc_pkg.vhd | 4 +- .../qspi_controller/sims/qspi_vc_tb.vhd | 65 ------------------- .../qspi_controller/sims/qspi_vc_th.vhd | 43 ------------ tools/vunit-sims.bxl | 29 +++++++++ 12 files changed, 67 insertions(+), 133 deletions(-) create mode 100644 .github/workflows/build.yml create mode 100644 .github/workflows/vunit.yml delete mode 100644 hdl/ip/vhd/ip_tests/BUCK delete mode 100644 hdl/ip/vhd/vunit_components/qspi_controller/sims/qspi_vc_tb.vhd delete mode 100644 hdl/ip/vhd/vunit_components/qspi_controller/sims/qspi_vc_th.vhd create mode 100644 tools/vunit-sims.bxl diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml new file mode 100644 index 00000000..e69de29b diff --git a/.github/workflows/vunit.yml b/.github/workflows/vunit.yml new file mode 100644 index 00000000..8164c37c --- /dev/null +++ b/.github/workflows/vunit.yml @@ -0,0 +1,18 @@ +name: vunit +run-name: ${{ github.actor }} is testing out GitHub Actions +on: + [push] +jobs: + Run-sim: + runs-on: self-hosted + steps: + - run: echo "The name of your branch is ${{ github.ref }} and your repository is ${{ github.repository }}." + - name: Check out repository code + uses: actions/checkout@v4 + with: + submodules: 'true' + - name: Update pip reqs + run : python3 -m pip install --upgrade -r tools/requirements.txt --break-system-packages + - name: Run VUnit tests + run: buck2 bxl //tools/vunit-sims.bxl:vunit_sim_gen | while IFS= read -r line; do eval "$line" ; done + \ No newline at end of file diff --git a/.gitignore b/.gitignore index 67b1051d..357e55f8 100644 --- a/.gitignore +++ b/.gitignore @@ -37,5 +37,8 @@ vivado*.log # Yep, even ignore Vivado core dump logs! *.log +# VUnit test results +**/*.xml + # DrawIO cruft **/*.svg.bkp diff --git a/README.md b/README.md index d72feba9..eb8b4089 100644 --- a/README.md +++ b/README.md @@ -96,6 +96,18 @@ but if you want to see a list of all available buck2 targets you can do: `buck2 To run a simulation, pick one of the testbench targets and `buck2 run ` you may do `-- ` if you need to pass arguments into VUnit. +### running all sims or sim regressions +We can use the build system to query for vunit simulation testbenches and have built a .bxl +that does this and gives you the command line options to run each one found: + +`buck2 bxl //tools/vunit-sims.bxl:vunit_sim_gen` + +If you'd like to run a regression run like the build machine does, you can pipe that into split +and use the shell to execute each line: + +`buck2 bxl //tools/vunit-sims.bxl:vunit_sim_gen | while IFS= read -r line; do eval "$line" ; done` + + ## multitool multitool is a collection of quality of live utilities built in-tree for regular use, but whose function is small enough to not warrant a self-contained project. diff --git a/hdl/ip/vhd/espi/sims/espi_tb.vhd b/hdl/ip/vhd/espi/sims/espi_tb.vhd index 7b3dd4ed..91abd3d2 100644 --- a/hdl/ip/vhd/espi/sims/espi_tb.vhd +++ b/hdl/ip/vhd/espi/sims/espi_tb.vhd @@ -193,6 +193,7 @@ begin -- temp enable periph 0 msg responses write_bus(net, bus_handle, To_StdLogicVector(CONTROL_OFFSET, bus_handle.p_address_length), std_logic_vector'(X"00000011")); -- Send UART data which will then be looped back and rx'd + rnd.InitSeed(rnd'instance_name & to_string(now)); payload_size := rnd.RandInt(1, 64); my_queue := build_rand_byte_queue(payload_size); dbg_send_uart_data_cmd(net, my_queue); @@ -202,7 +203,7 @@ begin check(response.crc_ok, "Send UART CMD resp CRC Check failed"); dbg_get_response_size(net, gen_int); print("Payload Size: " & integer'image(payload_size) & ", Response size: " & integer'image(gen_int)); - wait for 10 * payload_size * 250 ns; -- approx uart time for payload size + wait for 10 * payload_size * 300 ns; -- approx uart time for payload size status_rec := unpack(response.status); if status_rec.pc_avail /= '1' then dbg_wait_for_alert(net); diff --git a/hdl/ip/vhd/ip_tests/BUCK b/hdl/ip/vhd/ip_tests/BUCK deleted file mode 100644 index 8537ffdd..00000000 --- a/hdl/ip/vhd/ip_tests/BUCK +++ /dev/null @@ -1,15 +0,0 @@ -load("//tools:hdl.bzl", "vhdl_unit") - -vhdl_unit( - name = "ip_regression_tb", - is_tb = True, - srcs = [], - deps = [ - "//hdl/ip/vhd/arb_mux_demux:arbiter_tb", - "//hdl/ip/vhd/fifos:fifos_tb", - "//hdl/ip/vhd/memories:memories_tb", - "//hdl/ip/vhd/synchronizers:synchronizers_tb", - "//hdl/ip/vhd/common:utilities_tb", - "//hdl/ip/vhd/fmc_if:fmc_tb", - ] -) \ No newline at end of file diff --git a/hdl/ip/vhd/memories/BUCK b/hdl/ip/vhd/memories/BUCK index 924511a5..2bd2b301 100644 --- a/hdl/ip/vhd/memories/BUCK +++ b/hdl/ip/vhd/memories/BUCK @@ -15,6 +15,7 @@ vhdl_unit( srcs = glob(["sims/*.vhd"]), deps = [ ":dual_clock_simple_dpr", + "//hdl/ip/vhd/fifos:dcfifo_xpm", "//hdl/ip/vhd/vunit_components:sim_gpio" ], visibility = ['PUBLIC'], diff --git a/hdl/ip/vhd/vunit_components/BUCK b/hdl/ip/vhd/vunit_components/BUCK index 892475e5..76c8f1b9 100644 --- a/hdl/ip/vhd/vunit_components/BUCK +++ b/hdl/ip/vhd/vunit_components/BUCK @@ -20,13 +20,6 @@ vhdl_unit( visibility = ['PUBLIC'], ) -vunit_sim( - name = "qspi_vc_tb", - srcs = glob(["qspi_controller/sims/*.vhd"]), - deps = [":qspi_controller_vc"], - visibility = ['PUBLIC'], -) - vhdl_unit( name = "basic_stream", srcs = glob(["basic_stream/*.vhd"]), diff --git a/hdl/ip/vhd/vunit_components/qspi_controller/qspi_vc_pkg.vhd b/hdl/ip/vhd/vunit_components/qspi_controller/qspi_vc_pkg.vhd index 00c55fec..b614b620 100644 --- a/hdl/ip/vhd/vunit_components/qspi_controller/qspi_vc_pkg.vhd +++ b/hdl/ip/vhd/vunit_components/qspi_controller/qspi_vc_pkg.vhd @@ -104,7 +104,7 @@ package qspi_vc_pkg is procedure wait_until_start ( signal net : inout network_t; - constant actor : actor_t; + constant actor : actor_t ); @@ -144,7 +144,7 @@ package body qspi_vc_pkg is procedure wait_until_start ( signal net : inout network_t; - constant actor : actor_t; + constant actor : actor_t ) is variable request_msg : msg_t := new_msg(ensure_start); diff --git a/hdl/ip/vhd/vunit_components/qspi_controller/sims/qspi_vc_tb.vhd b/hdl/ip/vhd/vunit_components/qspi_controller/sims/qspi_vc_tb.vhd deleted file mode 100644 index 32990fb5..00000000 --- a/hdl/ip/vhd/vunit_components/qspi_controller/sims/qspi_vc_tb.vhd +++ /dev/null @@ -1,65 +0,0 @@ --- This Source Code Form is subject to the terms of the Mozilla Public --- License, v. 2.0. If a copy of the MPL was not distributed with this --- file, You can obtain one at https://mozilla.org/MPL/2.0/. --- --- Copyright 2024 Oxide Computer Company - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library vunit_lib; - context vunit_lib.com_context; - context vunit_lib.vunit_context; -use vunit_lib.sync_pkg.all; -use work.qspi_vc_pkg.all; - -entity qspi_vc_tb is - generic ( - - runner_cfg : string - ); -end entity; - -architecture tb of qspi_vc_tb is - - constant tx_queue : queue_t := new_queue; - -begin - - th: entity work.qspi_vc_th; - - bench: process - alias sim_reset is <>; - alias ss_n is <>; - variable msg_target : actor_t; - begin - -- Always the first thing in the process, set up things for the VUnit test runner - test_runner_setup(runner, runner_cfg); - - -- Reach into the test harness, which generates and de-asserts reset and hold the - -- test cases off until we're out of reset. This runs for every test case - wait until sim_reset = '0'; - msg_target := find("espi_vc"); -- get actor for the qspi block - - while test_suite loop - if run("shift_bytes_single") then - -- set_mode(net, msg_target, QUAD); - push_byte(tx_queue, 16#A5#); - enqueue_tx_data_bytes(net, msg_target, 1, tx_queue); - enqueue_transaction(net, msg_target, 1, 1); - -- cear the chipsel - -- wait for 0 ns; - -- elsif run("shift_bytes_dual") then - -- elsif run("shift_bytes_quad") then - end if; - end loop; - wait for 4 us; - test_runner_cleanup(runner); - wait; - end process; - - -- Example total test timeout dog - test_runner_watchdog(runner, 4 us); - -end tb; diff --git a/hdl/ip/vhd/vunit_components/qspi_controller/sims/qspi_vc_th.vhd b/hdl/ip/vhd/vunit_components/qspi_controller/sims/qspi_vc_th.vhd deleted file mode 100644 index 9efdd211..00000000 --- a/hdl/ip/vhd/vunit_components/qspi_controller/sims/qspi_vc_th.vhd +++ /dev/null @@ -1,43 +0,0 @@ --- This Source Code Form is subject to the terms of the Mozilla Public --- License, v. 2.0. If a copy of the MPL was not distributed with this --- file, You can obtain one at https://mozilla.org/MPL/2.0/. --- --- Copyright 2024 Oxide Computer Company - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.qspi_vc_pkg.all; - -entity qspi_vc_th is -end entity; - -architecture th of qspi_vc_th is - - signal clk : std_logic := '0'; - signal reset : std_logic := '1'; - - signal ss_n : std_logic_vector(7 downto 0); - signal sclk : std_logic; - signal io : std_logic_vector(3 downto 0); - - constant qspi_vc : qspi_vc_t := new_qspi_vc("espi_vc"); - -begin - - -- set up a fastish clock for the sim - -- environment and release reset after a bit of time - clk <= not clk after 4 ns; - reset <= '0' after 200 ns; - - qspi_controller_vc_inst: entity work.qspi_controller_vc - generic map ( - qspi_vc => qspi_vc - ) - port map ( - ss_n => ss_n, - sclk => sclk, - io => io - ); - -end th; diff --git a/tools/vunit-sims.bxl b/tools/vunit-sims.bxl new file mode 100644 index 00000000..ea39bd1e --- /dev/null +++ b/tools/vunit-sims.bxl @@ -0,0 +1,29 @@ +# This Source Code Form is subject to the terms of the Mozilla Public +# License, v. 2.0. If a copy of the MPL was not distributed with this +# file, You can obtain one at https://mozilla.org/MPL/2.0/. +# +# Copyright 2024 Oxide Computer Company + +# This function queries the build graph and targets that are +# simulation targets and runs them +def vunit_sim(ctx): + # start with all the buck2 targets from the root + target_universe = ctx.target_universe("//...").target_set() + # Get the deps + targets = ctx.cquery().deps(target_universe) + # Filter for vhdl files in the project + vhdl_files = ctx.cquery().kind("vhdl.*", targets) + sims = ctx.cquery().attrfilter("is_tb", "True", vhdl_files) + sims = sorted(sims, key=lambda x: x.attrs_eager().standard.value()) + # Eagerly analyze targets + results = ctx.analysis(sims) + for lbl,result in results.items(): + ctx.output.print("buck2 run " + str(lbl.raw_target()) + " -- --clean -x " + lbl.name + ".xml") + + +vunit_sim_gen = bxl_main( + impl = vunit_sim, + cli_args = { + # cli args that you want to receive from the command line + }, +) \ No newline at end of file