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Use Raptor on CLEAR #1931

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Martoni opened this issue Aug 20, 2024 · 1 comment

Martoni commented Aug 20, 2024

Is there configuration and example to develop on CLEAR FPGA with Raptor ?

https://github.com/efabless/clear/

Clear is an eFPGA generated with openFPGA and included in caravel.

Contributor

alaindargelas commented Aug 20, 2024

No there isn't. If you feel like it, please contribute one.
The first step would be to create a CLEAR device in Raptor:

Raptor/etc/device.xml

Line 2 in 2c47bb0

    
           <device name="MPW1" series="Gemini" family="Internal-Gemini" package="SBG484" pin_count="44" speedgrade="1" core_voltage="0.8V">

Then check the Yosys support for the technology mapping and probably a few modifications will be needed to target that, similar to the QL support:
https://github.com/os-fpga/FOEDAG_rs/blob/55cb6d9046d4373d548d0761591022bd5d90eaed/src/Compiler/CompilerRS.cpp#L45

If you engage in this project, all PRs have to come from you/others. We, at Rapid Silicon, have no bandwidth to develop this.

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