diff --git a/FOEDAG_rs b/FOEDAG_rs
index d9444493..476265a7 160000
--- a/FOEDAG_rs
+++ b/FOEDAG_rs
@@ -1 +1 @@
-Subproject commit d9444493699dc2e5daa65945f2f3f37aea214239
+Subproject commit 476265a75643eff4015da80319c6d8d2e1a17e22
diff --git a/etc/help.txt b/etc/help.txt
index dea4e5fd..ef894cf6 100644
--- a/etc/help.txt
+++ b/etc/help.txt
@@ -109,27 +109,31 @@ Tcl commands (Available in GUI or Batch console or Batch script):
 --- Synthesis ---
 -----------------
    synth_options <option list>:
-     -effort <level>          : Optimization effort level (high, medium, low)
-       high                   : Most compute, generally impacting runtime (default)
-       medium                 : Balanced compute
-       low                    : least compute, least runtime
-     -fsm_encoding <encoding> : FSM encoding (binary, onehot)
-       binary                 : Compact encoding - using minimum of registers to cover the N states
-       onehot                 : One hot encoding - using N registers for N states (default)
-     -carry <mode>            : Carry logic inference mode (all, auto, none)
-       all                    : Infer as much as possible
-       auto                   : Infer carries based on internal heuristics (default)
-       none                   : Do not infer carries
-     -clke_strategy <strategy>: Clock enable extraction strategy for FFs (early, late)
-       early                  : Perform early extraction (default)
-       late                   : Perform late extraction
-     -fast                    : Perform the fastest synthesis. QoR can be impacted
-     -no_flatten              : Do not flatten design
-     -no_simplify             : Do not run special simplification algorithms in synthesis
-     -no_tribuf               : Do not preserve I/O tristates
-     -no_adder                : Do not infer adders
-     -inferred_io             : Automatic I/O inference (Default false for eFPGA)
-     -no_inferred_io          : No automatic I/O inference (Default true for FPGA)
+     -effort <level>            : Optimization effort level (high, medium, low)
+       high                     : Most compute, generally impacting runtime (default)
+       medium                   : Balanced compute
+       low                      : least compute, least runtime
+     -fsm_encoding <encoding>   : FSM encoding (binary, onehot)
+       binary                   : Compact encoding - using minimum of registers to cover the N states
+       onehot                   : One hot encoding - using N registers for N states (default)
+     -carry <mode>              : Carry logic inference mode (all, auto, none)
+       all                      : Infer as much as possible
+       auto                     : Infer carries based on internal heuristics (default)
+       none                     : Do not infer carries
+     -clke_strategy <strategy>  : Clock enable extraction strategy for FFs (early, late)
+       early                    : Perform early extraction (default)
+       late                     : Perform late extraction
+     -fast                      : Perform the fastest synthesis. QoR can be impacted
+     -no_flatten                : Do not flatten design
+     -no_simplify               : Do not run special simplification algorithms in synthesis
+     -no_tribuf                 : Do not preserve I/O tristates
+     -no_adder                  : Do not infer adders
+     -inferred_io               : Automatic I/O inference (Default false for eFPGA)
+     -no_inferred_io            : No automatic I/O inference (Default true for FPGA)
+     -read_init_registers <int> : Force initialization to uninitialized registers (0, 1, 2)
+       0                        : Initialize register by '0' (default)
+       1                        : Initialize register by '1'
+       2                        : Leave register unintialized
 <engineering>
      -clke_strategy <strategy>: Clock enable extraction strategy for FFs:
        early                  : Perform early extraction