Added pll and Boot clock IP

.github/workflows/main.yml

@@ -98,7 +98,6 @@ jobs:
         ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/i2c_slave/v1_0/i2c_slave_gen.py --data_width=32 --build-name=wrapper --build
         ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/priority_encoder/v1_0/priority_encoder_gen.py --width=7 --build-name=encoder --build
         ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/vexriscv_cpu/v1_0/vexriscv_cpu_gen.py --build-name=vexriscv_wrap --build-dir=./ --build
-        ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axis_width_converter/v1_0/axis_width_converter_gen.py --core_in_width=1024 --core_out_width=32 --build-name=width_converter --build
         ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_interconnect/v1_0/axi_interconnect_gen.py --data_width=32 --addr_width=64 --s_count=7 --m_count=4 --build-name=interconnect_wrapper --build
         ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axil_interconnect/v1_0/axil_interconnect_gen.py --data_width=32 --addr_width=64 --s_count=5 --m_count=2  --build-name=interconnect_wrapper --build
         ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axil_crossbar/v1_0/axil_crossbar_gen.py --data_width=32 --addr_width=64 --s_count=5 --m_count=6  --build-name=crossbar_wrapper --build
@@ -206,7 +205,6 @@ jobs:
            ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/i2c_slave/v1_0/i2c_slave_gen.py --data_width=32 --json-template --build-name=wrapper --build
            ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/priority_encoder/v1_0/priority_encoder_gen.py --width=7 --json-template --build-name=encoder --build
            ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/vexriscv_cpu/v1_0/vexriscv_cpu_gen.py --json-template --build-name=vexriscv_wrap --build-dir=./ --build
-           ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axis_width_converter/v1_0/axis_width_converter_gen.py --core_in_width=1024 --core_out_width=32 --json-template --build-name=width_converter --build
            ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_interconnect/v1_0/axi_interconnect_gen.py --data_width=32 --addr_width=64 --s_count=7 --m_count=4 --json-template --build-name=interconnect_wrapper --build
            ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axil_interconnect/v1_0/axil_interconnect_gen.py --data_width=32 --addr_width=64 --s_count=5 --m_count=2 --json-template --build-name=interconnect_wrapper --build
            ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axil_crossbar/v1_0/axil_crossbar_gen.py --data_width=32 --addr_width=64 --s_count=5 --m_count=6 --json-template --build-name=crossbar_wrapper --build

rapidsilicon/ip/boot_clock/v1_0/boot_clock_gen.py

@@ -0,0 +1,116 @@
+#!/usr/bin/env python3
+#
+# This file is Copyright (c) 2022 RapidSilicon.
+#
+# SPDX-License-Identifier: MIT
+
+import os
+import sys
+import logging
+import argparse
+
+from litex_wrapper.boot_clock_litex_wrapper import BOOT_CLOCK
+
+from migen import *
+
+from litex.build.generic_platform import *
+
+from litex.build.osfpga import OSFPGAPlatform
+
+def get_clkin_ios():
+    return [
+        ("clk",  0, Pins(1)),
+        ("rst",  0, Pins(1))
+    ]
+
+# IOs/Interfaces -----------------------------------------------------------------------------------
+
+def get_other_ios():
+    return [
+        ("O",  0, Pins(1)),
+    ]
+
+# AXI RAM Wrapper ----------------------------------------------------------------------------------
+class BOOTCLOCKWrapper(Module):
+    def __init__(self, platform, period):
+        self.clock_domains.cd_sys  = ClockDomain()
+
+
+        # Boot Clock ----------------------------------------------------------------------------------
+        self.submodules.boot_clock = boot_clock = BOOT_CLOCK(platform, period = period
+            )
+
+        # Ports ---------------------------------------------------------------------------------
+        platform.add_extension(get_other_ios())
+        self.comb += platform.request("O").eq(boot_clock.O)
+
+# Build --------------------------------------------------------------------------------------------
+def main():
+    parser = argparse.ArgumentParser(description="Boot CLock")
+
+    # Import Common Modules.
+    common_path = os.path.join(os.path.dirname(__file__), "..", "..", "..", "lib")
+    sys.path.append(common_path)
+
+    from common import IP_Builder
+
+    # Parameter Dependency dictionary
+    #                Ports     :    Dependency
+    dep_dict = {}            
+
+    # IP Builder.
+    rs_builder = IP_Builder(device="gemini", ip_name="boot_clock", language="verilog")
+
+    logging.info("===================================================")
+    logging.info("IP    : %s", rs_builder.ip_name.upper())
+    logging.info(("==================================================="))
+
+
+    # Core range value parameters.
+    core_range_param_group = parser.add_argument_group(title="Core range parameters")
+    core_range_param_group.add_argument("--period",     type=int,   default=25,     choices=range(1,1000),     help="Clock period in ns")
+
+
+    # Build Parameters.
+    build_group = parser.add_argument_group(title="Build parameters")
+    build_group.add_argument("--build",         action="store_true",            help="Build Core")
+    build_group.add_argument("--build-dir",     default="./",                   help="Build Directory")
+    build_group.add_argument("--build-name",    default="boot_clock_wrapper",      help="Build Folder Name, Build RTL File Name and Module Name")
+
+    # JSON Import/Template
+    json_group = parser.add_argument_group(title="JSON Parameters")
+    json_group.add_argument("--json",                                           help="Generate Core from JSON File")
+    json_group.add_argument("--json-template",  action="store_true",            help="Generate JSON Template")
+
+    args = parser.parse_args()
+
+    # Import JSON (Optional) -----------------------------------------------------------------------
+    if args.json:
+        args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
+
+    # Export JSON Template (Optional) --------------------------------------------------------------
+    if args.json_template:
+        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
+
+    # Create Wrapper -------------------------------------------------------------------------------
+    platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")
+    module   = BOOTCLOCKWrapper(platform,
+        period = args.period,
+    )
+
+    # Build Project --------------------------------------------------------------------------------
+    if args.build:
+        rs_builder.prepare(
+            build_dir  = args.build_dir,
+            build_name = args.build_name,
+            version    = "v1_0"
+        )
+        rs_builder.copy_files(gen_path=os.path.dirname(__file__))
+        rs_builder.generate_tcl()
+        rs_builder.generate_wrapper(
+            platform   = platform,
+            module     = module,
+        )
+
+if __name__ == "__main__":
+    main()

rapidsilicon/ip/boot_clock/v1_0/litex_wrapper/README.md

@@ -0,0 +1 @@
+Directory for Python Wrapper

rapidsilicon/ip/boot_clock/v1_0/litex_wrapper/boot_clock_litex_wrapper.py

@@ -0,0 +1,56 @@
+#
+# This file is part of RapidSilicon's IP_Catalog.
+#
+# This file is Copyright (c) 2022 RapidSilicon.
+#
+# SPDX-License-Identifier: MIT
+#
+
+import os
+import datetime
+import logging
+
+from migen import *
+
+# logging.basicConfig(level=logging.INFO)
+logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n')
+
+timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S')
+logging.info(f'Log started at {timestamp}')
+
+
+def colorer(s, color="bright"):
+    header  = {
+        "bright": "\x1b[1m",
+        "green":  "\x1b[32m",
+        "cyan":   "\x1b[36m",
+        "red":    "\x1b[31m",
+        "yellow": "\x1b[33m",
+        "underline": "\x1b[4m"}[color]
+    trailer = "\x1b[0m"
+    return header + str(s) + trailer
+
+
+class BOOT_CLOCK(Module):
+    def __init__(self, platform, period):
+        self.logger = logging.getLogger("BOOT_CLOCK")
+        self.logger.propagate = True
+
+        self.logger.info("Creating BOOT_CLOCK module.")
+        self.logger.info(f"=================== PARAMETERS ====================")
+        self.logger.info(f"PERIOD  : {colorer(period)}")
+
+        # Clock output
+        self.O = Signal()
+
+        self.specials += Instance("BOOT_CLOCK",
+            p_PERIOD=Instance.PreformattedParam(period),
+            o_O=self.O
+        )
+
+        self.add_sources(platform)
+
+    @staticmethod
+    def add_sources(platform):
+        rtl_dir = os.path.join(os.path.dirname(__file__), "../src")
+        platform.add_source(os.path.join(rtl_dir, "boot_clock.v"))

rapidsilicon/ip/boot_clock/v1_0/src/BOOT_CLOCK.v

@@ -0,0 +1,30 @@
+`timescale 1ns/1ps
+`celldefine
+//
+// BOOT_CLOCK simulation model
+// Internal BOOT_CLK connection
+//
+// Copyright (c) 2023 Rapid Silicon, Inc.  All rights reserved.
+//
+
+module BOOT_CLOCK #(
+  parameter PERIOD = 25.0 // Clock period for simulation purposes (nS)
+) (
+  output reg O = 1'b0 // Clock output
+);
+localparam HALF_PERIOD = PERIOD/2.0;
+
+
+  always
+    #HALF_PERIOD O <= ~O;
+ initial begin
+
+    if ((PERIOD < 16.0) || (PERIOD > 30.0)) begin
+       $display("BOOT_CLOCK instance %m PERIOD set to incorrect value, %f.  Values must be between 16.0 and 30.0.", PERIOD);
+    #1 $stop;
+    end
+
+  end
+
+endmodule
+`endcelldefine

rapidsilicon/ip/axis_width_converter/v1_0/LICENSE → rapidsilicon/ip/pll/v1_0/LICENSE

@@ -21,6 +21,8 @@ IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 FILES:
-rapidsilicon/ip/axis_width_converter/v1_0/axis_width_converter_gen.py
-
+rapidsilicon/ip/pll/v1_0/pll_gen.py
+rapidsilicon/ip/pll/v1_0/litex_wrapper/pll_litex_wrapper.py
+rapidsilicon/ip/pll/v1_0/src/pll.v
 ---------------------------------------------------------------------------------------
+