Mem initialization loggers

rapidsilicon/ip/ahb2axi_bridge/v1_0/ahb2axi_bridge_gen.py

@@ -6,6 +6,7 @@
 
 import os
 import sys
+import logging
 import argparse
 
 from litex_wrapper.ahb2axi_bridge_litex_wrapper import AHB2AXI4
@@ -105,6 +106,10 @@ def main():
     # IP Builder.
     rs_builder = IP_Builder(device="gemini", ip_name="ahb2axi_bridge", language="System verilog")
 
+    logging.info("===================================================")
+    logging.info("IP    : %s", rs_builder.ip_name.upper())
+    logging.info(("==================================================="))
+
     # Core fix value parameters.
     core_fix_param_group = parser.add_argument_group(title="Core fix parameters")
     core_fix_param_group.add_argument("--data_width",       type=int,       default=32,         choices=[32, 64],      help="Data Width")

rapidsilicon/ip/ahb2axi_bridge/v1_0/litex_wrapper/ahb2axi_bridge_litex_wrapper.py

@@ -8,13 +8,18 @@
 # LiteX wrapper around western digital's ahb2axi4.v
 
 import os
+import datetime
 import logging
 
 from migen import *
 
 from litex.soc.interconnect.axi import *
 
-logging.basicConfig(level=logging.INFO)
+# logging.basicConfig(level=logging.INFO)
+logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n')
+
+timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S')
+logging.info(f'Log started at {timestamp}')
 
 # AHB_2_AXI4_BRIDGE ---------------------------------------------------------------------------------------
 class AHB2AXI4(Module):
@@ -24,11 +29,11 @@ def __init__(self, platform, m_axi):
         # ---------------------        
         self.logger = logging.getLogger("AHB_2_AXI4")
 
-        self.logger.propagate = False
+        self.logger.propagate = True
 
         # Clock Domain.
-       # self.logger.info(f"CLOCK_DOMAIN     : {s_ahb.clock_domain}")
-
+        # self.logger.info(f"CLOCK_DOMAIN     : {s_ahb.clock_domain}")
+        self.logger.info(f"=================== PARAMETERS ====================")
         # Address width.
         address_width = len(m_axi.aw.addr)
         self.logger.info(f"C_AXI_ADDR_WIDTH : {address_width}")
@@ -41,6 +46,8 @@ def __init__(self, platform, m_axi):
         id_width = len(m_axi.aw.id)
         self.logger.info(f"C_AXI_ID_WIDTH   : {id_width}")
 
+        self.logger.info(f"===================================================")
+
         self.ahb_haddr               = Signal(address_width)
         self.ahb_hburst              = Signal(3)
         self.ahb_hmastlock           = Signal(1)
@@ -56,8 +63,6 @@ def __init__(self, platform, m_axi):
         self.ahb_hreadyout           = Signal(1)
         self.ahb_hresp               = Signal(1)
 
-
-
         # Module instance.
         # ----------------
         self.specials += Instance("ahb2axi4",

rapidsilicon/ip/axi2axilite_bridge/v1_0/axi2axilite_bridge_gen.py

@@ -6,6 +6,7 @@
 
 import os
 import sys
+import logging
 import argparse
 
 from litex_wrapper.axi2axilite_bridge_litex_wrapper import AXI2AXILITE
@@ -73,6 +74,10 @@ def main():
     # IP Builder.
     rs_builder = IP_Builder(device="gemini", ip_name="axi2axilite_bridge", language="verilog")
 
+    logging.info("===================================================")
+    logging.info("IP    : %s", rs_builder.ip_name.upper())
+    logging.info(("==================================================="))
+
     # Core fix value parameters.
     core_fix_param_group = parser.add_argument_group(title="Core fix parameters")
     core_fix_param_group.add_argument("--data_width",       type=int,       default=32,         choices=[8, 16, 32, 64, 128, 256],      help="Data Width")

rapidsilicon/ip/axi2axilite_bridge/v1_0/litex_wrapper/axi2axilite_bridge_litex_wrapper.py

@@ -8,13 +8,19 @@
 # LiteX wrapper around Dan Gisselquist ZipCPU/wb2axip's axi2axilite.v
 
 import os
+import datetime
 import logging
 
 from migen import *
 
 from litex.soc.interconnect.axi import *
 
-logging.basicConfig(level=logging.INFO)
+# logging.basicConfig(level=logging.INFO)
+logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n')
+
+timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S')
+logging.info(f'Log started at {timestamp}')
+
 
 # AXI_2_AXILITE_BRIDGE ---------------------------------------------------------------------------------------
 class AXI2AXILITE(Module):
@@ -24,8 +30,8 @@ def __init__(self, platform, s_axi, m_axi):
         # ---------------------        
         self.logger = logging.getLogger("AXI_2_AXILITE")
 
-        self.logger.propagate = False
-
+        self.logger.propagate = True
+        self.logger.info(f"=================== PARAMETERS ====================")
         # Clock Domain.
         self.logger.info(f"CLOCK_DOMAIN     : {s_axi.clock_domain}")
 
@@ -40,7 +46,7 @@ def __init__(self, platform, s_axi, m_axi):
         # ID width.
         id_width = len(s_axi.aw.id)
         self.logger.info(f"C_AXI_ID_WIDTH   : {id_width}")
-
+        self.logger.info(f"===================================================")
         # Module instance.
         # ----------------
         self.specials += Instance("axi2axilite",

rapidsilicon/ip/axi_async_fifo/v1_0/axi_async_fifo_gen.py

@@ -7,6 +7,7 @@
 import os
 import sys
 import json
+import logging
 import argparse
 import math
 
@@ -88,6 +89,10 @@ def main():
     # IP Builder.
     rs_builder = IP_Builder(device="gemini", ip_name="axi_async_fifo", language="verilog")
 
+    logging.info("===================================================")
+    logging.info("IP    : %s", rs_builder.ip_name.upper())
+    logging.info(("==================================================="))
+
     # Core fix value parameters.
     core_fix_param_group = parser.add_argument_group(title="Core fix parameters")
     core_fix_param_group.add_argument("--fifo_depth",          type=int,     default=4096,   choices=[8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192,16384,32768],   help="FIFO Depth.")

rapidsilicon/ip/axi_async_fifo/v1_0/litex_wrapper/axi_async_fifo_litex_wrapper.py

@@ -8,14 +8,20 @@
 # LiteX wrapper around Alex Forencich Verilog-AXI's axi_fifo.v
 
 import os
+import datetime
 import logging
 import math
 
 from migen import *
 
 from litex.soc.interconnect.axi import *
 
-logging.basicConfig(level=logging.INFO)
+# logging.basicConfig(level=logging.INFO)
+logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n')
+
+timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S')
+logging.info(f'Log started at {timestamp}')
+
 
 # AXI_FIFO ---------------------------------------------------------------------------------------
 class AXIASYNCFIFO(Module):
@@ -25,8 +31,10 @@ def __init__(self, platform, s_axi, m_axi, fifo_depth):
         # --------------
         self.logger = logging.getLogger("AXI_FIFO")
 
-        self.logger.propagate = False
+        self.logger.propagate = True
 
+        self.logger.info(f"=================== PARAMETERS ====================")
+
         data_width = len(s_axi.w.data)
         self.logger.info(f"DATA_WIDTH       : {data_width}")
 
@@ -38,6 +46,7 @@ def __init__(self, platform, s_axi, m_axi, fifo_depth):
 
         self.logger.info(f"WRITE_FIFO_DELAY : {fifo_depth}")
 
+        self.logger.info(f"===================================================")
 
         # Clock/Reset Signals
         self.m_clk                 = Signal()

rapidsilicon/ip/axi_cdma/v1_0/axi_cdma_gen.py

@@ -6,6 +6,7 @@
 
 import os
 import sys
+import logging
 import argparse
 
 from litex_wrapper.axi_cdma_litex_wrapper import AXICDMA
@@ -110,7 +111,11 @@ def main():
 
     # IP Builder.
     rs_builder = IP_Builder(device="gemini", ip_name="axi_cdma", language="verilog")
-
+
+    logging.info("===================================================")
+    logging.info("IP    : %s", rs_builder.ip_name.upper())
+    logging.info(("==================================================="))
+
     # Core fix value parameters.
     core_fix_param_group = parser.add_argument_group(title="Core fix parameters")
     core_fix_param_group.add_argument("--data_width",        type=int,      default=32,     choices=[8, 16, 32, 64, 128, 256], help="DMA Data Width.")

rapidsilicon/ip/axi_cdma/v1_0/litex_wrapper/axi_cdma_litex_wrapper.py

@@ -8,13 +8,19 @@
 # LiteX wrapper around Alex Forencich Verilog-AXI's axi_cdma.v
 
 import os
+import datetime
 import logging
 
 from migen import *
 
 from litex.soc.interconnect.axi import *
 
-logging.basicConfig(level=logging.INFO)
+# logging.basicConfig(level=logging.INFO)
+logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n')
+
+timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S')
+logging.info(f'Log started at {timestamp}')
+
 
 # AXI CDMA ---------------------------------------------------------------------------------------
 class AXICDMA(Module):
@@ -29,8 +35,10 @@ def __init__(self, platform, m_axi,
         # ---------------------        
         self.logger = logging.getLogger("AXI_CDMA")
 
-        self.logger.propagate = False
+        self.logger.propagate = True
 
+        self.logger.info(f"=================== PARAMETERS ====================")
+
         # Clock Domain.
         self.logger.info(f"Clock Domain     : {m_axi.clock_domain}")
 
@@ -52,6 +60,8 @@ def __init__(self, platform, m_axi,
         self.logger.info(f"TAG_WIDTH        : {tag_width}")
         self.logger.info(f"ENABLE_UNALIGNED : {enable_unaligned}")
 
+        self.logger.info(f"===================================================")
+
         # Non-Stnadard IOs
         self.s_axis_desc_read_addr      = Signal(address_width)
         self.s_axis_desc_write_addr     = Signal(address_width)

rapidsilicon/ip/axi_cdma/v2_0/axi_cdma_gen.py

@@ -6,6 +6,7 @@
 
 import os
 import sys
+import logging
 import argparse
 
 from litex_wrapper.axi_cdma_litex_wrapper import AXICDMA
@@ -18,7 +19,6 @@
 
 from litex.soc.interconnect.axi import AXIInterface, AXILiteInterface
 
-
 # IOs / Interface ----------------------------------------------------------------------------------
 def get_clkin_ios():
     return [
@@ -27,8 +27,6 @@ def get_clkin_ios():
         ("o_int", 0, Pins(1))
         ]
 
-
-
 # AXI-CDMA Wrapper --------------------------------------------------------------------------------
 class AXICDMAWrapper(Module):
     def __init__(self, platform, id_width, axi_addr_width, axi_data_width, axil_addr_width, axil_data_width):
@@ -45,13 +43,10 @@ def __init__(self, platform, id_width, axi_addr_width, axi_data_width, axil_addr
             data_width         = axi_data_width,
             address_width      = axi_addr_width
         )
-
 
-
         platform.add_extension(axi.get_ios("m_axi"))
         self.comb += axi.connect_to_pads(platform.request("m_axi"), mode="master")
-
-
+
         # AXI-LITE 
         axil = AXILiteInterface(
             address_width      = axil_addr_width,
@@ -60,15 +55,10 @@ def __init__(self, platform, id_width, axi_addr_width, axi_data_width, axil_addr
         platform.add_extension(axil.get_ios("s_axil"))
         self.comb += axil.connect_to_pads(platform.request("s_axil"), mode="slave")
 
-
         # AXI_CDMA
         self.submodules.cdma = cdma = AXICDMA(platform, axi,axil)
-
         self.comb += platform.request("o_int").eq(cdma.o_int)
 
-
-
-
 # Build --------------------------------------------------------------------------------------------
 def main():
     parser = argparse.ArgumentParser(description="AXI CDMA CORE")
@@ -85,20 +75,22 @@ def main():
 
     # IP Builder.
     rs_builder = IP_Builder(device="gemini", ip_name="axi_cdma", language="verilog")
-
+
+    logging.info("===================================================")
+    logging.info("IP    : %s", rs_builder.ip_name.upper())
+    logging.info(("==================================================="))
+
     # Core fix value parameters.
     core_fix_param_group = parser.add_argument_group(title="Core fix parameters")
     core_fix_param_group.add_argument("--axi_data_width",        type=int,      default=32,     choices=[8, 16, 32, 64, 128, 256], help="CDMA AXI4 full Data Width.")
     core_fix_param_group.add_argument("--axi_addr_width",        type=int,      default=32,     choices=[8, 16, 32, 64, 128, 256], help="CDMA AXI4 full addr Width.")
     core_fix_param_group.add_argument("--axil_data_width",       type=int,      default=32,     choices=[32],                      help="CDMA AXI4 lite Data Width.")
     core_fix_param_group.add_argument("--axil_addr_width",       type=int,      default=5,      choices=range(1, 65),              help="CDMA AXI4 lite addr Width.")
 
-
     # Core range value parameters.
     core_range_param_group = parser.add_argument_group(title="Core range parameters")
     core_range_param_group.add_argument("--id_width",          type=int,    default=8,      choices=range(1, 33),    help="CDMA ID Width.")
 
-
     # Build Parameters.
     build_group = parser.add_argument_group(title="Build parameters")
     build_group.add_argument("--build",         action="store_true",            help="Build Core")

rapidsilicon/ip/axi_cdma/v2_0/litex_wrapper/axi_cdma_litex_wrapper.py

@@ -8,13 +8,18 @@
 # LiteX wrapper around ZipCPU Verilog-AXI's axicdma.v
 
 import os
+import datetime
 import logging
 
 from migen import *
 
 from litex.soc.interconnect.axi import *
 
-logging.basicConfig(level=logging.INFO)
+# logging.basicConfig(level=logging.INFO)
+logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n')
+
+timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S')
+logging.info(f'Log started at {timestamp}')
 
 # AXI CDMA ---------------------------------------------------------------------------------------
 class AXICDMA(Module):
@@ -24,8 +29,9 @@ def __init__(self, platform, axi, axil):
         # ---------------------        
         self.logger = logging.getLogger("AXI_CDMA")
 
-        self.logger.propagate = False
-
+        self.logger.propagate = True
+
+        self.logger.info(f"=================== PARAMETERS ====================")
         # Clock Domain.
         self.logger.info(f"Clock Domain     : {axi.clock_domain}")
 
@@ -43,10 +49,10 @@ def __init__(self, platform, axi, axil):
         id_width = len(axi.aw.id)
         self.logger.info(f"AXI_ID_WIDTH     : {id_width}")
 
-
+        self.logger.info(f"===================================================")
+
         self.o_int   = Signal()
 
-
         # Module instance.
         # ----------------
         self.specials += Instance("axi_cdma",