diff --git a/rapidsilicon/ip/ahb2axi_bridge/v1_0/ahb2axi_bridge_gen.py b/rapidsilicon/ip/ahb2axi_bridge/v1_0/ahb2axi_bridge_gen.py index eaef9b23..ba78b740 100755 --- a/rapidsilicon/ip/ahb2axi_bridge/v1_0/ahb2axi_bridge_gen.py +++ b/rapidsilicon/ip/ahb2axi_bridge/v1_0/ahb2axi_bridge_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.ahb2axi_bridge_litex_wrapper import AHB2AXI4 @@ -105,6 +106,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="ahb2axi_bridge", language="System verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", type=int, default=32, choices=[32, 64], help="Data Width") diff --git a/rapidsilicon/ip/ahb2axi_bridge/v1_0/litex_wrapper/__pycache__/ahb2axi4_bridge_litex_wrapper.cpython-38.pyc b/rapidsilicon/ip/ahb2axi_bridge/v1_0/litex_wrapper/__pycache__/ahb2axi4_bridge_litex_wrapper.cpython-38.pyc deleted file mode 100644 index 2e793b52..00000000 Binary files a/rapidsilicon/ip/ahb2axi_bridge/v1_0/litex_wrapper/__pycache__/ahb2axi4_bridge_litex_wrapper.cpython-38.pyc and /dev/null differ diff --git a/rapidsilicon/ip/ahb2axi_bridge/v1_0/litex_wrapper/__pycache__/ahb2axi_bridge_litex_wrapper.cpython-38.pyc b/rapidsilicon/ip/ahb2axi_bridge/v1_0/litex_wrapper/__pycache__/ahb2axi_bridge_litex_wrapper.cpython-38.pyc deleted file mode 100644 index aadb7d4f..00000000 Binary files a/rapidsilicon/ip/ahb2axi_bridge/v1_0/litex_wrapper/__pycache__/ahb2axi_bridge_litex_wrapper.cpython-38.pyc and /dev/null differ diff --git a/rapidsilicon/ip/ahb2axi_bridge/v1_0/litex_wrapper/ahb2axi_bridge_litex_wrapper.py b/rapidsilicon/ip/ahb2axi_bridge/v1_0/litex_wrapper/ahb2axi_bridge_litex_wrapper.py index f49a6ef4..169d2eb8 100644 --- a/rapidsilicon/ip/ahb2axi_bridge/v1_0/litex_wrapper/ahb2axi_bridge_litex_wrapper.py +++ b/rapidsilicon/ip/ahb2axi_bridge/v1_0/litex_wrapper/ahb2axi_bridge_litex_wrapper.py @@ -8,13 +8,18 @@ # LiteX wrapper around western digital's ahb2axi4.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # AHB_2_AXI4_BRIDGE --------------------------------------------------------------------------------------- class AHB2AXI4(Module): @@ -24,11 +29,11 @@ def __init__(self, platform, m_axi): # --------------------- self.logger = logging.getLogger("AHB_2_AXI4") - self.logger.propagate = False + self.logger.propagate = True # Clock Domain. - # self.logger.info(f"CLOCK_DOMAIN : {s_ahb.clock_domain}") - + # self.logger.info(f"CLOCK_DOMAIN : {s_ahb.clock_domain}") + self.logger.info(f"=================== PARAMETERS ====================") # Address width. address_width = len(m_axi.aw.addr) self.logger.info(f"C_AXI_ADDR_WIDTH : {address_width}") @@ -41,6 +46,8 @@ def __init__(self, platform, m_axi): id_width = len(m_axi.aw.id) self.logger.info(f"C_AXI_ID_WIDTH : {id_width}") + self.logger.info(f"===================================================") + self.ahb_haddr = Signal(address_width) self.ahb_hburst = Signal(3) self.ahb_hmastlock = Signal(1) @@ -56,8 +63,6 @@ def __init__(self, platform, m_axi): self.ahb_hreadyout = Signal(1) self.ahb_hresp = Signal(1) - - # Module instance. # ---------------- self.specials += Instance("ahb2axi4", diff --git a/rapidsilicon/ip/axi2axilite_bridge/v1_0/axi2axilite_bridge_gen.py b/rapidsilicon/ip/axi2axilite_bridge/v1_0/axi2axilite_bridge_gen.py index 13d0391f..3fccca40 100755 --- a/rapidsilicon/ip/axi2axilite_bridge/v1_0/axi2axilite_bridge_gen.py +++ b/rapidsilicon/ip/axi2axilite_bridge/v1_0/axi2axilite_bridge_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axi2axilite_bridge_litex_wrapper import AXI2AXILITE @@ -73,6 +74,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axi2axilite_bridge", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", type=int, default=32, choices=[8, 16, 32, 64, 128, 256], help="Data Width") diff --git a/rapidsilicon/ip/axi2axilite_bridge/v1_0/litex_wrapper/__pycache__/axi2axilite_bridge_litex_wrapper.cpython-36.pyc b/rapidsilicon/ip/axi2axilite_bridge/v1_0/litex_wrapper/__pycache__/axi2axilite_bridge_litex_wrapper.cpython-36.pyc deleted file mode 100644 index 23b47d4f..00000000 Binary files a/rapidsilicon/ip/axi2axilite_bridge/v1_0/litex_wrapper/__pycache__/axi2axilite_bridge_litex_wrapper.cpython-36.pyc and /dev/null differ diff --git a/rapidsilicon/ip/axi2axilite_bridge/v1_0/litex_wrapper/axi2axilite_bridge_litex_wrapper.py b/rapidsilicon/ip/axi2axilite_bridge/v1_0/litex_wrapper/axi2axilite_bridge_litex_wrapper.py index 19491687..2e322518 100644 --- a/rapidsilicon/ip/axi2axilite_bridge/v1_0/litex_wrapper/axi2axilite_bridge_litex_wrapper.py +++ b/rapidsilicon/ip/axi2axilite_bridge/v1_0/litex_wrapper/axi2axilite_bridge_litex_wrapper.py @@ -8,13 +8,19 @@ # LiteX wrapper around Dan Gisselquist ZipCPU/wb2axip's axi2axilite.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') + # AXI_2_AXILITE_BRIDGE --------------------------------------------------------------------------------------- class AXI2AXILITE(Module): @@ -24,8 +30,8 @@ def __init__(self, platform, s_axi, m_axi): # --------------------- self.logger = logging.getLogger("AXI_2_AXILITE") - self.logger.propagate = False - + self.logger.propagate = True + self.logger.info(f"=================== PARAMETERS ====================") # Clock Domain. self.logger.info(f"CLOCK_DOMAIN : {s_axi.clock_domain}") @@ -40,7 +46,7 @@ def __init__(self, platform, s_axi, m_axi): # ID width. id_width = len(s_axi.aw.id) self.logger.info(f"C_AXI_ID_WIDTH : {id_width}") - + self.logger.info(f"===================================================") # Module instance. # ---------------- self.specials += Instance("axi2axilite", diff --git a/rapidsilicon/ip/axi_async_fifo/v1_0/axi_async_fifo_gen.py b/rapidsilicon/ip/axi_async_fifo/v1_0/axi_async_fifo_gen.py index ca4f83d8..3773990e 100755 --- a/rapidsilicon/ip/axi_async_fifo/v1_0/axi_async_fifo_gen.py +++ b/rapidsilicon/ip/axi_async_fifo/v1_0/axi_async_fifo_gen.py @@ -7,6 +7,7 @@ import os import sys import json +import logging import argparse import math @@ -88,6 +89,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axi_async_fifo", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--fifo_depth", type=int, default=4096, choices=[8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192,16384,32768], help="FIFO Depth.") diff --git a/rapidsilicon/ip/axi_async_fifo/v1_0/litex_wrapper/axi_async_fifo_litex_wrapper.py b/rapidsilicon/ip/axi_async_fifo/v1_0/litex_wrapper/axi_async_fifo_litex_wrapper.py index c1975432..4a3419c2 100644 --- a/rapidsilicon/ip/axi_async_fifo/v1_0/litex_wrapper/axi_async_fifo_litex_wrapper.py +++ b/rapidsilicon/ip/axi_async_fifo/v1_0/litex_wrapper/axi_async_fifo_litex_wrapper.py @@ -8,6 +8,7 @@ # LiteX wrapper around Alex Forencich Verilog-AXI's axi_fifo.v import os +import datetime import logging import math @@ -15,7 +16,12 @@ from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') + # AXI_FIFO --------------------------------------------------------------------------------------- class AXIASYNCFIFO(Module): @@ -25,8 +31,10 @@ def __init__(self, platform, s_axi, m_axi, fifo_depth): # -------------- self.logger = logging.getLogger("AXI_FIFO") - self.logger.propagate = False + self.logger.propagate = True + self.logger.info(f"=================== PARAMETERS ====================") + data_width = len(s_axi.w.data) self.logger.info(f"DATA_WIDTH : {data_width}") @@ -38,6 +46,7 @@ def __init__(self, platform, s_axi, m_axi, fifo_depth): self.logger.info(f"WRITE_FIFO_DELAY : {fifo_depth}") + self.logger.info(f"===================================================") # Clock/Reset Signals self.m_clk = Signal() diff --git a/rapidsilicon/ip/axi_cdma/v1_0/axi_cdma_gen.py b/rapidsilicon/ip/axi_cdma/v1_0/axi_cdma_gen.py index 97164209..4800c96a 100755 --- a/rapidsilicon/ip/axi_cdma/v1_0/axi_cdma_gen.py +++ b/rapidsilicon/ip/axi_cdma/v1_0/axi_cdma_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axi_cdma_litex_wrapper import AXICDMA @@ -110,7 +111,11 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axi_cdma", language="verilog") - + + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", type=int, default=32, choices=[8, 16, 32, 64, 128, 256], help="DMA Data Width.") diff --git a/rapidsilicon/ip/axi_cdma/v1_0/litex_wrapper/axi_cdma_litex_wrapper.py b/rapidsilicon/ip/axi_cdma/v1_0/litex_wrapper/axi_cdma_litex_wrapper.py index 7bbcc1da..d897c3cd 100644 --- a/rapidsilicon/ip/axi_cdma/v1_0/litex_wrapper/axi_cdma_litex_wrapper.py +++ b/rapidsilicon/ip/axi_cdma/v1_0/litex_wrapper/axi_cdma_litex_wrapper.py @@ -8,13 +8,19 @@ # LiteX wrapper around Alex Forencich Verilog-AXI's axi_cdma.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') + # AXI CDMA --------------------------------------------------------------------------------------- class AXICDMA(Module): @@ -29,8 +35,10 @@ def __init__(self, platform, m_axi, # --------------------- self.logger = logging.getLogger("AXI_CDMA") - self.logger.propagate = False + self.logger.propagate = True + self.logger.info(f"=================== PARAMETERS ====================") + # Clock Domain. self.logger.info(f"Clock Domain : {m_axi.clock_domain}") @@ -52,6 +60,8 @@ def __init__(self, platform, m_axi, self.logger.info(f"TAG_WIDTH : {tag_width}") self.logger.info(f"ENABLE_UNALIGNED : {enable_unaligned}") + self.logger.info(f"===================================================") + # Non-Stnadard IOs self.s_axis_desc_read_addr = Signal(address_width) self.s_axis_desc_write_addr = Signal(address_width) diff --git a/rapidsilicon/ip/axi_cdma/v2_0/axi_cdma_gen.py b/rapidsilicon/ip/axi_cdma/v2_0/axi_cdma_gen.py index 124148ad..ff2b3eba 100755 --- a/rapidsilicon/ip/axi_cdma/v2_0/axi_cdma_gen.py +++ b/rapidsilicon/ip/axi_cdma/v2_0/axi_cdma_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axi_cdma_litex_wrapper import AXICDMA @@ -18,7 +19,6 @@ from litex.soc.interconnect.axi import AXIInterface, AXILiteInterface - # IOs / Interface ---------------------------------------------------------------------------------- def get_clkin_ios(): return [ @@ -27,8 +27,6 @@ def get_clkin_ios(): ("o_int", 0, Pins(1)) ] - - # AXI-CDMA Wrapper -------------------------------------------------------------------------------- class AXICDMAWrapper(Module): def __init__(self, platform, id_width, axi_addr_width, axi_data_width, axil_addr_width, axil_data_width): @@ -45,13 +43,10 @@ def __init__(self, platform, id_width, axi_addr_width, axi_data_width, axil_addr data_width = axi_data_width, address_width = axi_addr_width ) - - platform.add_extension(axi.get_ios("m_axi")) self.comb += axi.connect_to_pads(platform.request("m_axi"), mode="master") - - + # AXI-LITE axil = AXILiteInterface( address_width = axil_addr_width, @@ -60,15 +55,10 @@ def __init__(self, platform, id_width, axi_addr_width, axi_data_width, axil_addr platform.add_extension(axil.get_ios("s_axil")) self.comb += axil.connect_to_pads(platform.request("s_axil"), mode="slave") - # AXI_CDMA self.submodules.cdma = cdma = AXICDMA(platform, axi,axil) - self.comb += platform.request("o_int").eq(cdma.o_int) - - - # Build -------------------------------------------------------------------------------------------- def main(): parser = argparse.ArgumentParser(description="AXI CDMA CORE") @@ -85,7 +75,11 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axi_cdma", language="verilog") - + + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--axi_data_width", type=int, default=32, choices=[8, 16, 32, 64, 128, 256], help="CDMA AXI4 full Data Width.") @@ -93,12 +87,10 @@ def main(): core_fix_param_group.add_argument("--axil_data_width", type=int, default=32, choices=[32], help="CDMA AXI4 lite Data Width.") core_fix_param_group.add_argument("--axil_addr_width", type=int, default=5, choices=range(1, 65), help="CDMA AXI4 lite addr Width.") - # Core range value parameters. core_range_param_group = parser.add_argument_group(title="Core range parameters") core_range_param_group.add_argument("--id_width", type=int, default=8, choices=range(1, 33), help="CDMA ID Width.") - # Build Parameters. build_group = parser.add_argument_group(title="Build parameters") build_group.add_argument("--build", action="store_true", help="Build Core") diff --git a/rapidsilicon/ip/axi_cdma/v2_0/litex_wrapper/__pycache__/axi_cdma_litex_wrapper.cpython-36.pyc b/rapidsilicon/ip/axi_cdma/v2_0/litex_wrapper/__pycache__/axi_cdma_litex_wrapper.cpython-36.pyc deleted file mode 100644 index 9e7c9bde..00000000 Binary files a/rapidsilicon/ip/axi_cdma/v2_0/litex_wrapper/__pycache__/axi_cdma_litex_wrapper.cpython-36.pyc and /dev/null differ diff --git a/rapidsilicon/ip/axi_cdma/v2_0/litex_wrapper/axi_cdma_litex_wrapper.py b/rapidsilicon/ip/axi_cdma/v2_0/litex_wrapper/axi_cdma_litex_wrapper.py index 5f0872f0..73e44547 100644 --- a/rapidsilicon/ip/axi_cdma/v2_0/litex_wrapper/axi_cdma_litex_wrapper.py +++ b/rapidsilicon/ip/axi_cdma/v2_0/litex_wrapper/axi_cdma_litex_wrapper.py @@ -8,13 +8,18 @@ # LiteX wrapper around ZipCPU Verilog-AXI's axicdma.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # AXI CDMA --------------------------------------------------------------------------------------- class AXICDMA(Module): @@ -24,8 +29,9 @@ def __init__(self, platform, axi, axil): # --------------------- self.logger = logging.getLogger("AXI_CDMA") - self.logger.propagate = False - + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") # Clock Domain. self.logger.info(f"Clock Domain : {axi.clock_domain}") @@ -43,10 +49,10 @@ def __init__(self, platform, axi, axil): id_width = len(axi.aw.id) self.logger.info(f"AXI_ID_WIDTH : {id_width}") - + self.logger.info(f"===================================================") + self.o_int = Signal() - # Module instance. # ---------------- self.specials += Instance("axi_cdma", diff --git a/rapidsilicon/ip/axi_crossbar/v1_0/axi_crossbar_gen.py b/rapidsilicon/ip/axi_crossbar/v1_0/axi_crossbar_gen.py index f15ea5d4..f9d1f87d 100755 --- a/rapidsilicon/ip/axi_crossbar/v1_0/axi_crossbar_gen.py +++ b/rapidsilicon/ip/axi_crossbar/v1_0/axi_crossbar_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse import math @@ -106,6 +107,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axi_crossbar", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", type=int, default=32, choices=[8, 16, 32, 64, 128, 256], help="AXI Data Width.") diff --git a/rapidsilicon/ip/axi_crossbar/v1_0/litex_wrapper/axi_crossbar_litex_wrapper.py b/rapidsilicon/ip/axi_crossbar/v1_0/litex_wrapper/axi_crossbar_litex_wrapper.py index c3e83259..faa5578d 100644 --- a/rapidsilicon/ip/axi_crossbar/v1_0/litex_wrapper/axi_crossbar_litex_wrapper.py +++ b/rapidsilicon/ip/axi_crossbar/v1_0/litex_wrapper/axi_crossbar_litex_wrapper.py @@ -8,13 +8,19 @@ # LiteX wrapper around Alex Forencich Verilog-AXI's axi_crossbar.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') + # AXI CROSSBAR --------------------------------------------------------------------------------- class AXICROSSBAR(Module): @@ -23,8 +29,10 @@ def __init__(self, platform, s_axi, m_axi, s_count, m_count, aw_user_en, w_user_ self.logger = logging.getLogger("AXI_CROSSBAR") - self.logger.propagate = False - + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") + # AXI Inputs (slave interfaces). s_count = len(s_axi) self.logger.info(f"S_COUNT : {s_count}") @@ -69,6 +77,7 @@ def __init__(self, platform, s_axi, m_axi, s_count, m_count, aw_user_en, w_user_ r_user_width = len(s_axi[0].r.user) self.logger.info(f"RUSER_WIDTH : {r_user_width}") + self.logger.info(f"===================================================") # Module instance. # ---------------- self.specials += Instance("axi_crossbar", diff --git a/rapidsilicon/ip/axi_crossbar/v2_0/axi_crossbar_gen.py b/rapidsilicon/ip/axi_crossbar/v2_0/axi_crossbar_gen.py index 78a44a39..8b754fe2 100755 --- a/rapidsilicon/ip/axi_crossbar/v2_0/axi_crossbar_gen.py +++ b/rapidsilicon/ip/axi_crossbar/v2_0/axi_crossbar_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse import math @@ -132,16 +133,18 @@ def main(): 'ar_user_width' : 'ar_user_en', 'r_user_width' : 'r_user_en', } - - # IP Builder. + # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axi_crossbar", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", type=int, default=32, choices=[8, 16, 32, 64, 128, 256], help="AXI Data Width.") core_fix_param_group.add_argument("--addr_width", type=int, default=32, choices=[32, 64], help="AXI Address Width.") - # Core bool value parameters. core_bool_param_group = parser.add_argument_group(title="Core bool parameters") core_bool_param_group.add_argument("--aw_user_en", type=bool, default=True, help="AW-Channel User Enable.") @@ -151,7 +154,6 @@ def main(): core_bool_param_group.add_argument("--r_user_en", type=bool, default=False, help="R-Channel User Enable.") core_bool_param_group.add_argument("--bram", type=bool, default=True, help="Memory type") - # Core range value parameters. core_range_param_group = parser.add_argument_group(title="Core range parameters") core_range_param_group.add_argument("--m_count", type=int, default=4, choices=range(1,5), help="Crossbar Master Interfaces.") @@ -163,8 +165,6 @@ def main(): core_range_param_group.add_argument("--ar_user_width", type=int, default=1, choices=range(1, 1025), help="AR-Channel User Width.") core_range_param_group.add_argument("--r_user_width", type=int, default=1, choices=range(1, 1025), help="R-Channel User Width.") - - # Build Parameters. build_group = parser.add_argument_group(title="Build parameters") build_group.add_argument("--build", action="store_true", help="Build Core") diff --git a/rapidsilicon/ip/axi_crossbar/v2_0/litex_wrapper/axi_crossbar_litex_wrapper.py b/rapidsilicon/ip/axi_crossbar/v2_0/litex_wrapper/axi_crossbar_litex_wrapper.py index 3e452a91..93527e72 100644 --- a/rapidsilicon/ip/axi_crossbar/v2_0/litex_wrapper/axi_crossbar_litex_wrapper.py +++ b/rapidsilicon/ip/axi_crossbar/v2_0/litex_wrapper/axi_crossbar_litex_wrapper.py @@ -8,13 +8,19 @@ # LiteX wrapper around Alex Forencich Verilog-AXI's axi_crossbar.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') + # AXI CROSSBAR --------------------------------------------------------------------------------- class AXICROSSBAR(Module): @@ -121,8 +127,8 @@ def __init__(self, platform, s_axi, m_axi, s_count, m_count, aw_user_en, w_user_ self.logger = logging.getLogger("AXI_CROSSBAR") - self.logger.propagate = False - + self.logger.propagate = True + self.logger.info(f"=================== PARAMETERS ====================") # AXI Inputs (slave interfaces). s_count = len(s_axi) self.logger.info(f"S_COUNT : {s_count}") @@ -170,7 +176,7 @@ def __init__(self, platform, s_axi, m_axi, s_count, m_count, aw_user_en, w_user_ # R User width. r_user_width = len(s_axi[0].r.user) self.logger.info(f"RUSER_WIDTH : {r_user_width}") - + self.logger.info(f"===================================================") # Module instance. # ---------------- self.specials += Instance("axi_crossbar", diff --git a/rapidsilicon/ip/axi_dma/v1_0/axi_dma_gen.py b/rapidsilicon/ip/axi_dma/v1_0/axi_dma_gen.py index e9c5631f..8006f7cb 100755 --- a/rapidsilicon/ip/axi_dma/v1_0/axi_dma_gen.py +++ b/rapidsilicon/ip/axi_dma/v1_0/axi_dma_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axi_dma_litex_wrapper import AXIDMA @@ -189,6 +190,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axi_dma", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--axi_data_width", type=int, default=32, choices=[8, 16, 32, 64, 128, 256], help="DMA Data Width.") diff --git a/rapidsilicon/ip/axi_dma/v1_0/litex_wrapper/axi_dma_litex_wrapper.py b/rapidsilicon/ip/axi_dma/v1_0/litex_wrapper/axi_dma_litex_wrapper.py index b057ac9a..5c9af05b 100644 --- a/rapidsilicon/ip/axi_dma/v1_0/litex_wrapper/axi_dma_litex_wrapper.py +++ b/rapidsilicon/ip/axi_dma/v1_0/litex_wrapper/axi_dma_litex_wrapper.py @@ -8,13 +8,19 @@ # LiteX wrapper around Alex Forencich Verilog-AXI's axi_dma.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') + # AXI DMA --------------------------------------------------------------------------------------- class AXIDMA(Module): @@ -34,8 +40,8 @@ def __init__(self, platform, m_axi, m_axis, s_axis, # --------------------- self.logger = logging.getLogger("AXI_DMA") - self.logger.propagate = False - + self.logger.propagate = True + self.logger.info(f"=================== PARAMETERS ====================") self.logger.info(f"Clock Domain : {m_axi.clock_domain}") address_width = len(m_axi.aw.addr) @@ -68,7 +74,7 @@ def __init__(self, platform, m_axi, m_axis, s_axis, self.logger.info(f"TAG_WIDTH : {tag_width}") self.logger.info(f"ENABLE_SG : {enable_sg}") self.logger.info(f"ENABLE_UNALIGNED : {enable_unaligned}") - + self.logger.info(f"===================================================") # Non-Stnadard IOs self.s_axis_read_desc_addr = Signal(address_width) self.s_axis_read_desc_len = Signal(len_width) diff --git a/rapidsilicon/ip/axi_dpram/v1_0/axi_dpram_gen.py b/rapidsilicon/ip/axi_dpram/v1_0/axi_dpram_gen.py index e4f32036..5572d20a 100755 --- a/rapidsilicon/ip/axi_dpram/v1_0/axi_dpram_gen.py +++ b/rapidsilicon/ip/axi_dpram/v1_0/axi_dpram_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axi_dp_ram_litex_wrapper import AXIDPRAM @@ -92,6 +93,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axi_dpram", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", type=int, default=32, choices=[8, 16, 32, 64, 128, 256], help="DPRAM Data Width.") diff --git a/rapidsilicon/ip/axi_dpram/v1_0/litex_wrapper/axi_dp_ram_litex_wrapper.py b/rapidsilicon/ip/axi_dpram/v1_0/litex_wrapper/axi_dp_ram_litex_wrapper.py index 70bf459d..b25bdd88 100644 --- a/rapidsilicon/ip/axi_dpram/v1_0/litex_wrapper/axi_dp_ram_litex_wrapper.py +++ b/rapidsilicon/ip/axi_dpram/v1_0/litex_wrapper/axi_dp_ram_litex_wrapper.py @@ -8,16 +8,20 @@ # LiteX wrapper around Alex Forencich Verilog-AXI's axi_dp_ram.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') -# AXI DP RAM --------------------------------------------------------------------------------------- +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') +# AXI DP-RAM --------------------------------------------------------------------------------------- class AXIDPRAM(Module): def __init__(self, platform, s_axi_a, s_axi_b, size=0x1000, a_pipeline_output = 0, @@ -25,13 +29,12 @@ def __init__(self, platform, s_axi_a, s_axi_b, size=0x1000, b_pipeline_output = 0, b_interleave = 0, ): - # Get Parameters. # --------------------- self.logger = logging.getLogger("AXI_DPRAM") - self.logger.propagate = False - + self.logger.propagate = True + self.logger.info(f"=================== PARAMETERS ====================") # Clock Domain. self.logger.info(f"Clock Domain A : {s_axi_a.clock_domain}") self.logger.info(f"Clock Domain B : {s_axi_b.clock_domain}") @@ -56,7 +59,8 @@ def __init__(self, platform, s_axi_a, s_axi_b, size=0x1000, self.logger.info(f"A Interleave R/W : {a_interleave}") self.logger.info(f"B Pipeline Output: {b_pipeline_output}") self.logger.info(f"B Interleave R/W : {b_interleave}") - + self.logger.info(f"===================================================") + # Clock/Reset Signals self.a_clk= Signal() self.a_rst= Signal() diff --git a/rapidsilicon/ip/axi_fifo/v1_0/axi_fifo_gen.py b/rapidsilicon/ip/axi_fifo/v1_0/axi_fifo_gen.py index 963b9ad5..54216c9c 100755 --- a/rapidsilicon/ip/axi_fifo/v1_0/axi_fifo_gen.py +++ b/rapidsilicon/ip/axi_fifo/v1_0/axi_fifo_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axi_fifo_litex_wrapper import AXIFIFO @@ -99,6 +100,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axi_fifo", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", type=int, default=32, choices=[32, 64, 128, 256, 512, 1024], help="FIFO Data Width.") diff --git a/rapidsilicon/ip/axi_fifo/v1_0/litex_wrapper/axi_fifo_litex_wrapper.py b/rapidsilicon/ip/axi_fifo/v1_0/litex_wrapper/axi_fifo_litex_wrapper.py index 80763287..c2a7b1c9 100644 --- a/rapidsilicon/ip/axi_fifo/v1_0/litex_wrapper/axi_fifo_litex_wrapper.py +++ b/rapidsilicon/ip/axi_fifo/v1_0/litex_wrapper/axi_fifo_litex_wrapper.py @@ -8,13 +8,19 @@ # LiteX wrapper around Alex Forencich Verilog-AXI's axi_fifo.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') + # AXI_FIFO --------------------------------------------------------------------------------------- class AXIFIFO(Module): @@ -34,8 +40,8 @@ def __init__(self, platform, s_axi, m_axi, # -------------- self.logger = logging.getLogger("AXI_FIFO") - self.logger.propagate = False - + self.logger.propagate = True + self.logger.info(f"=================== PARAMETERS ====================") clock_domain = s_axi.clock_domain self.logger.info(f"Clock Domain : {clock_domain}") @@ -72,7 +78,9 @@ def __init__(self, platform, s_axi, m_axi, self.logger.info(f"READ_FIFO_DEPTH : {read_fifo_depth}") self.logger.info(f"WRITE_FIFO_DELAY : {write_fifo_delay}") self.logger.info(f"READ_FIFO_DELAY : {read_fifo_delay}") - + + self.logger.info(f"===================================================") + # Module instance. # ---------------- self.specials += Instance("axi_fifo", diff --git a/rapidsilicon/ip/axi_interconnect/v1_0/axi_interconnect_gen.py b/rapidsilicon/ip/axi_interconnect/v1_0/axi_interconnect_gen.py index 7585fb36..8328d44b 100755 --- a/rapidsilicon/ip/axi_interconnect/v1_0/axi_interconnect_gen.py +++ b/rapidsilicon/ip/axi_interconnect/v1_0/axi_interconnect_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axi_interconnect_litex_wrapper import AXIINTERCONNECT @@ -101,6 +102,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axi_interconnect", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", type=int, default=32, choices=[8, 16, 32, 64, 128, 256], help="AXI Data Width.") diff --git a/rapidsilicon/ip/axi_interconnect/v1_0/litex_wrapper/axi_interconnect_litex_wrapper.py b/rapidsilicon/ip/axi_interconnect/v1_0/litex_wrapper/axi_interconnect_litex_wrapper.py index 365cc9b5..ce898b03 100644 --- a/rapidsilicon/ip/axi_interconnect/v1_0/litex_wrapper/axi_interconnect_litex_wrapper.py +++ b/rapidsilicon/ip/axi_interconnect/v1_0/litex_wrapper/axi_interconnect_litex_wrapper.py @@ -8,13 +8,19 @@ # LiteX wrapper around Alex Forencich Verilog-AXI's axi_interconnect.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') + # AXI Interconnect --------------------------------------------------------------------------------- class AXIINTERCONNECT(Module): @@ -23,8 +29,10 @@ def __init__(self, platform, s_axi, m_axi, s_count, m_count, aw_user_en, w_user_ self.logger = logging.getLogger("AXI_INTERCONNECT") - self.logger.propagate = False + self.logger.propagate = True + self.logger.info(f"=================== PARAMETERS ====================") + # AXI Inputs (slave interfaces). s_count = len(s_axi) self.logger.info(f"S_COUNT : {s_count}") @@ -68,7 +76,9 @@ def __init__(self, platform, s_axi, m_axi, s_count, m_count, aw_user_en, w_user_ # R User width. r_user_width = len(s_axi[0].r.user) self.logger.info(f"RUSER_WIDTH : {r_user_width}") - + + self.logger.info(f"===================================================") + # Module instance. # ---------------- self.specials += Instance("axi_interconnect", diff --git a/rapidsilicon/ip/axi_ram/v1_0/axi_ram_gen.py b/rapidsilicon/ip/axi_ram/v1_0/axi_ram_gen.py index b5437a3e..6a9d27c4 100755 --- a/rapidsilicon/ip/axi_ram/v1_0/axi_ram_gen.py +++ b/rapidsilicon/ip/axi_ram/v1_0/axi_ram_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axi_ram_litex_wrapper import AXIRAM @@ -68,6 +69,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axi_ram", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", type=int, default=32, choices=[8, 16, 32, 64], help="RAM Data Width") diff --git a/rapidsilicon/ip/axi_ram/v1_0/litex_wrapper/axi_ram_litex_wrapper.py b/rapidsilicon/ip/axi_ram/v1_0/litex_wrapper/axi_ram_litex_wrapper.py index 07cbd0a4..cc17460c 100644 --- a/rapidsilicon/ip/axi_ram/v1_0/litex_wrapper/axi_ram_litex_wrapper.py +++ b/rapidsilicon/ip/axi_ram/v1_0/litex_wrapper/axi_ram_litex_wrapper.py @@ -8,16 +8,20 @@ # LiteX wrapper around Alex Forencich Verilog-AXI's axi_ram.v. import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') -# Helpers ------------------------------------------------------------------------------------------ +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') +# Helpers ------------------------------------------------------------------------------------------ class Open(Signal): pass def colorer(s, color="bright"): @@ -40,8 +44,8 @@ def __init__(self, platform, s_axi, size=1024, pipeline_output=False): # --------------------- self.logger = logging.getLogger("AXI_RAM") - self.logger.propagate = False - + self.logger.propagate = True + self.logger.info(f"=================== PARAMETERS ====================") # Clock Domain. clock_domain = s_axi.clock_domain self.logger.info(f"Clock Domain : {colorer(clock_domain)}") @@ -64,6 +68,7 @@ def __init__(self, platform, s_axi, size=1024, pipeline_output=False): # Pipeline Output self.logger.info(f"PIPELINE_OUTPUT : {colorer(pipeline_output)}") + self.logger.info(f"===================================================") # Module instance. # ---------------- diff --git a/rapidsilicon/ip/axi_register/v1_0/axi_register_gen.py b/rapidsilicon/ip/axi_register/v1_0/axi_register_gen.py index bea4b9cb..994261f5 100755 --- a/rapidsilicon/ip/axi_register/v1_0/axi_register_gen.py +++ b/rapidsilicon/ip/axi_register/v1_0/axi_register_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axi_register_litex_wrapper import AXIREGISTER @@ -102,6 +103,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axi_register", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core string parameters. core_string_param_group = parser.add_argument_group(title="Core string parameters") core_string_param_group.add_argument("--aw_reg_type", type=str, default="Simple_Buffer", choices=["Bypass", "Simple_Buffer", "Skid_Buffer"], help="Type of Register") diff --git a/rapidsilicon/ip/axi_register/v1_0/litex_wrapper/axi_register_litex_wrapper.py b/rapidsilicon/ip/axi_register/v1_0/litex_wrapper/axi_register_litex_wrapper.py index 8745f9f2..b7607167 100644 --- a/rapidsilicon/ip/axi_register/v1_0/litex_wrapper/axi_register_litex_wrapper.py +++ b/rapidsilicon/ip/axi_register/v1_0/litex_wrapper/axi_register_litex_wrapper.py @@ -8,15 +8,20 @@ # LiteX wrapper around Alex Forencich Verilog-AXI's axi_register.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') -# AXI DP RAM --------------------------------------------------------------------------------------- +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') + +# AXI Register --------------------------------------------------------------------------------------- class AXIREGISTER(Module): def __init__(self, platform, s_axi, m_axi, size=1024, aw_reg_type = 1, @@ -30,9 +35,8 @@ def __init__(self, platform, s_axi, m_axi, size=1024, # --------------------- self.logger = logging.getLogger("AXI_REGISTER") - self.logger.propagate = False - - + self.logger.propagate = True + self.logger.info(f"=================== PARAMETERS ====================") # Clock Domain. self.logger.info(f"Clock Domain : {s_axi.clock_domain}") @@ -73,7 +77,7 @@ def __init__(self, platform, s_axi, m_axi, size=1024, self.logger.info(f"B_REG_TYPE : {b_reg_type}") self.logger.info(f"AR_REG_TYPE : {ar_reg_type}") self.logger.info(f"R_REG_TYPE : {r_reg_type}") - + self.logger.info(f"===================================================") # Module instance. # ---------------- self.specials += Instance("axi_register", diff --git a/rapidsilicon/ip/axil_crossbar/v1_0/axil_crossbar_gen.py b/rapidsilicon/ip/axil_crossbar/v1_0/axil_crossbar_gen.py index 84a698f3..3561fc8c 100755 --- a/rapidsilicon/ip/axil_crossbar/v1_0/axil_crossbar_gen.py +++ b/rapidsilicon/ip/axil_crossbar/v1_0/axil_crossbar_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axil_crossbar_litex_wrapper import AXILITECROSSBAR @@ -85,6 +86,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axil_crossbar", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", default=32, choices=[32, 64], type=int, help="Crossbar Data Width.") diff --git a/rapidsilicon/ip/axil_crossbar/v1_0/litex_wrapper/axil_crossbar_litex_wrapper.py b/rapidsilicon/ip/axil_crossbar/v1_0/litex_wrapper/axil_crossbar_litex_wrapper.py index d52515df..0d501761 100644 --- a/rapidsilicon/ip/axil_crossbar/v1_0/litex_wrapper/axil_crossbar_litex_wrapper.py +++ b/rapidsilicon/ip/axil_crossbar/v1_0/litex_wrapper/axil_crossbar_litex_wrapper.py @@ -8,14 +8,18 @@ # LiteX wrapper around Alex Forencich Verilog-AXI's axil_crossbar.v. import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # AXI LITE CROSSBAR ------------------------------------------------------------------------------------------ class AXILITECROSSBAR(Module): @@ -23,8 +27,8 @@ def __init__(self, platform, s_axil, m_axil, s_count, m_count): self.logger = logging.getLogger("AXI_LITE_CROSSBAR") - self.logger.propagate = False - + self.logger.propagate = True + self.logger.info(f"=================== PARAMETERS ====================") # Clock Domain. clock_domain = s_axil[0].clock_domain self.logger.info(f"CLOCK_DOMAIN : {clock_domain}") @@ -44,7 +48,7 @@ def __init__(self, platform, s_axil, m_axil, s_count, m_count): # Address width. addr_width = len(s_axil[0].aw.addr) self.logger.info(f"ADDR_WIDTH : {addr_width}") - + self.logger.info(f"===================================================") # Module instance. # --------------- self.specials += Instance("axil_crossbar", diff --git a/rapidsilicon/ip/axil_crossbar/v2_0/axil_crossbar_gen.py b/rapidsilicon/ip/axil_crossbar/v2_0/axil_crossbar_gen.py index 37af5c3d..fc8a257d 100755 --- a/rapidsilicon/ip/axil_crossbar/v2_0/axil_crossbar_gen.py +++ b/rapidsilicon/ip/axil_crossbar/v2_0/axil_crossbar_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axil_crossbar_litex_wrapper import AXILITECROSSBAR @@ -114,12 +115,15 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axil_crossbar", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", type=int, default=32, choices=[32, 64], help="Crossbar Data Width.") core_fix_param_group.add_argument("--addr_width", type=int, default=32, choices=[32, 64, 128, 256], help="Crossbar Address Width.") - # Core bool value parameters. core_bool_param_group = parser.add_argument_group(title="Core bool parameters") core_bool_param_group.add_argument("--bram", type=bool, default=True, help="Memory type") diff --git a/rapidsilicon/ip/axil_crossbar/v2_0/litex_wrapper/axil_crossbar_litex_wrapper.py b/rapidsilicon/ip/axil_crossbar/v2_0/litex_wrapper/axil_crossbar_litex_wrapper.py index 5ea0b9db..eb843807 100644 --- a/rapidsilicon/ip/axil_crossbar/v2_0/litex_wrapper/axil_crossbar_litex_wrapper.py +++ b/rapidsilicon/ip/axil_crossbar/v2_0/litex_wrapper/axil_crossbar_litex_wrapper.py @@ -8,14 +8,18 @@ # LiteX wrapper around Alex Forencich Verilog-AXI's axil_crossbar.v. import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # AXI LITE CROSSBAR ------------------------------------------------------------------------------------------ class AXILITECROSSBAR(Module): @@ -74,8 +78,8 @@ def __init__(self, platform, s_axil, m_axil, s_count, m_count,bram): self.logger = logging.getLogger("AXI_LITE_CROSSBAR") - self.logger.propagate = False - + self.logger.propagate = True + self.logger.info(f"=================== PARAMETERS ====================") # Clock Domain. clock_domain = s_axil[0].clock_domain self.logger.info(f"CLOCK_DOMAIN : {clock_domain}") @@ -95,11 +99,10 @@ def __init__(self, platform, s_axil, m_axil, s_count, m_count,bram): # Address width. addr_width = len(s_axil[0].aw.addr) self.logger.info(f"ADDR_WIDTH : {addr_width}") - + self.logger.info(f"===================================================") # Module instance. # ---------------- - self.specials += Instance("axil_crossbar", # Parameters. # ----------- diff --git a/rapidsilicon/ip/axil_eio/v1_0/axil_eio_gen.py b/rapidsilicon/ip/axil_eio/v1_0/axil_eio_gen.py index ea05a377..bf6c13c8 100755 --- a/rapidsilicon/ip/axil_eio/v1_0/axil_eio_gen.py +++ b/rapidsilicon/ip/axil_eio/v1_0/axil_eio_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axil_eio_litex_wrapper import AXILEIO @@ -81,6 +82,10 @@ def main(): # IP Builder rs_builder = IP_Builder(device="gemini", ip_name="axil_eio", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fixed values parameters core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", type=int, default=32, choices=[32, 64], help="AXI Data Width.") diff --git a/rapidsilicon/ip/axil_eio/v1_0/litex_wrapper/axil_eio_litex_wrapper.py b/rapidsilicon/ip/axil_eio/v1_0/litex_wrapper/axil_eio_litex_wrapper.py index 3c767205..63b43f63 100755 --- a/rapidsilicon/ip/axil_eio/v1_0/litex_wrapper/axil_eio_litex_wrapper.py +++ b/rapidsilicon/ip/axil_eio/v1_0/litex_wrapper/axil_eio_litex_wrapper.py @@ -8,13 +8,18 @@ # LiteX wrapper around eio_top.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # AXIL_EIO --------------------------------------------------------------------------------- class AXILEIO(Module): @@ -29,8 +34,8 @@ def __init__(self, self.logger = logging.getLogger("AXIL_EIO") - self.logger.propagate = False - + self.logger.propagate = True + self.logger.info(f"=================== PARAMETERS ====================") # Clock Domain. clock_domain = s_axil.clock_domain self.logger.info(f"CLOCK_DOMAIN : {clock_domain}") @@ -42,7 +47,7 @@ def __init__(self, # Data width. data_width = len(s_axil.w.data) self.logger.info(f"DATA_WIDTH : {data_width}") - + self.logger.info(f"===================================================") self.probe_in = Signal(input_probe_width) self.probe_out = Signal(output_probe_width) diff --git a/rapidsilicon/ip/axil_ethernet/v1_0/axil_ethernet_gen.py b/rapidsilicon/ip/axil_ethernet/v1_0/axil_ethernet_gen.py index 947238b1..72cf05fb 100755 --- a/rapidsilicon/ip/axil_ethernet/v1_0/axil_ethernet_gen.py +++ b/rapidsilicon/ip/axil_ethernet/v1_0/axil_ethernet_gen.py @@ -47,7 +47,6 @@ ] # Core --------------------------------------------------------------------------------------------- - def LiteEthCore(platform, phy="mii", bus_endianness="big", ntxslots=2, nrxslots=2): core_config = { "phy" : getattr(liteeth_phys, f"LiteEthPHY{phy.upper()}"), diff --git a/rapidsilicon/ip/axil_gpio/v1_0/axil_gpio_gen.py b/rapidsilicon/ip/axil_gpio/v1_0/axil_gpio_gen.py index 2221268b..a1c959b7 100755 --- a/rapidsilicon/ip/axil_gpio/v1_0/axil_gpio_gen.py +++ b/rapidsilicon/ip/axil_gpio/v1_0/axil_gpio_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axil_gpio_litex_wrapper import AXILITEGPIO @@ -75,6 +76,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axil_gpio", language="sverilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", type=int, default=32, choices=[32,64], help="GPIO Data Width.") diff --git a/rapidsilicon/ip/axil_gpio/v1_0/litex_wrapper/axil_gpio_litex_wrapper.py b/rapidsilicon/ip/axil_gpio/v1_0/litex_wrapper/axil_gpio_litex_wrapper.py index 3abe70a8..bcf32d5b 100644 --- a/rapidsilicon/ip/axil_gpio/v1_0/litex_wrapper/axil_gpio_litex_wrapper.py +++ b/rapidsilicon/ip/axil_gpio/v1_0/litex_wrapper/axil_gpio_litex_wrapper.py @@ -8,13 +8,18 @@ # LiteX wrapper around Smartfox Data Solutions Inc. axi4lite_gpio's axi4lite_gpio.sv import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') class AXILITEGPIO(Module): def __init__(self, platform, s_axil): @@ -23,8 +28,8 @@ def __init__(self, platform, s_axil): # -------------- self.logger = logging.getLogger("AXI_LITE_GPIO") - self.logger.propagate = False - + self.logger.propagate = True + self.logger.info(f"=================== PARAMETERS ====================") # Clock Domain. clock_domain = s_axil.clock_domain self.logger.info(f"Clock Domain : {clock_domain}") @@ -36,7 +41,7 @@ def __init__(self, platform, s_axil): # Address width. address_width = len(s_axil.aw.addr) self.logger.info(f"Address Width : {address_width}") - + self.logger.info(f"===================================================") # GPIO self.gpin = Signal(data_width) self.gpout = Signal(data_width) diff --git a/rapidsilicon/ip/axil_interconnect/v1_0/axil_interconnect_gen.py b/rapidsilicon/ip/axil_interconnect/v1_0/axil_interconnect_gen.py index d7d31f29..88e096d3 100755 --- a/rapidsilicon/ip/axil_interconnect/v1_0/axil_interconnect_gen.py +++ b/rapidsilicon/ip/axil_interconnect/v1_0/axil_interconnect_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axil_interconnect_litex_wrapper import AXILITEINTERCONNECT @@ -87,6 +88,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axil_interconnect", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", type=int, default=32, choices=[32, 64], help="Interconnect Data Width.") diff --git a/rapidsilicon/ip/axil_interconnect/v1_0/litex_wrapper/axil_interconnect_litex_wrapper.py b/rapidsilicon/ip/axil_interconnect/v1_0/litex_wrapper/axil_interconnect_litex_wrapper.py index 3fc3877d..0c984a18 100644 --- a/rapidsilicon/ip/axil_interconnect/v1_0/litex_wrapper/axil_interconnect_litex_wrapper.py +++ b/rapidsilicon/ip/axil_interconnect/v1_0/litex_wrapper/axil_interconnect_litex_wrapper.py @@ -8,14 +8,18 @@ # LiteX wrapper around Alex Forencich Verilog-AXI's axil_interconnect.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # AXI LITE INTERCONNECT ------------------------------------------------------------------------------------------ class AXILITEINTERCONNECT(Module): @@ -25,8 +29,10 @@ def __init__(self, platform, s_axil, m_axil, s_count, m_count): # --------------------- self.logger = logging.getLogger("AXI_LITE_INTERCONNECT") - self.logger.propagate = False - + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") + # Clock Domain. clock_domain = s_axil[0].clock_domain self.logger.info(f"CLOCK_DOMAIN : {clock_domain}") @@ -46,6 +52,8 @@ def __init__(self, platform, s_axil, m_axil, s_count, m_count): # Address width. addr_width = len(s_axil[0].aw.addr) self.logger.info(f"ADDR_WIDTH : {addr_width}") + + self.logger.info(f"===================================================") # Module instance. # ---------------- diff --git a/rapidsilicon/ip/axil_ocla/v1_0/axil_ocla_gen.py b/rapidsilicon/ip/axil_ocla/v1_0/axil_ocla_gen.py index f02a1aeb..0f36b273 100644 --- a/rapidsilicon/ip/axil_ocla/v1_0/axil_ocla_gen.py +++ b/rapidsilicon/ip/axil_ocla/v1_0/axil_ocla_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import json import argparse @@ -102,6 +103,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axil_ocla", language="sverilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="OCLA IP Core fix parameters") core_fix_param_group.add_argument("--mem_depth", type=int, default=32, choices=[32, 64, 128, 256, 512, 1024], help="OCLA Trace Memory Depth.") diff --git a/rapidsilicon/ip/axil_ocla/v1_0/litex_wrapper/axil_ocla_litex_wrapper.py b/rapidsilicon/ip/axil_ocla/v1_0/litex_wrapper/axil_ocla_litex_wrapper.py index 8e67a64b..a9d4ff3b 100644 --- a/rapidsilicon/ip/axil_ocla/v1_0/litex_wrapper/axil_ocla_litex_wrapper.py +++ b/rapidsilicon/ip/axil_ocla/v1_0/litex_wrapper/axil_ocla_litex_wrapper.py @@ -8,15 +8,18 @@ # LiteX wrapper around RS OCLA IP CORE ocla.v import os -import logging - -from datetime import datetime +import datetime +import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # AXI LITE OCLA ------------------------------------------------------------------------------------- class AXILITEOCLA(Module): @@ -30,26 +33,26 @@ def __init__(self, platform, self.logger = logging.getLogger("AXI_LITE_OCLA") - self.logger.propagate = False - + self.logger.propagate = True + self.logger.info(f"=================== PARAMETERS ====================") # Clock Domain clock_domain = s_axil.clock_domain - self.logger.info(f"CLOCK_DOMAIN : {clock_domain}") + self.logger.info(f"CLOCK_DOMAIN : {clock_domain}") # Address width. address_width = len(s_axil.aw.addr) - self.logger.info(f"ADDRESS_WIDTH : {address_width}") + self.logger.info(f"ADDRESS_WIDTH : {address_width}") # Read Data width. data_width = len(s_axil.r.data) - self.logger.info(f"DATA_WIDTH : {data_width}") + self.logger.info(f"DATA_WIDTH : {data_width}") # OCLA features. self.logger.info(f"NO_OF_PROBES : {nprobes}") self.logger.info(f"NO_OF_TRIGGER_INPUTS : {trigger_inputs}") self.logger.info(f"PROBE_WIDHT : {probe_widht}") self.logger.info(f"MEM_DEPTH : {mem_depth}") - + self.logger.info(f"===================================================") # OCLA Signals if(trigger_inputs_en == True): diff --git a/rapidsilicon/ip/axil_uart16550/v1_0/axil_uart16550_gen.py b/rapidsilicon/ip/axil_uart16550/v1_0/axil_uart16550_gen.py index e25f98d4..9676c005 100755 --- a/rapidsilicon/ip/axil_uart16550/v1_0/axil_uart16550_gen.py +++ b/rapidsilicon/ip/axil_uart16550/v1_0/axil_uart16550_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axil_uart16550_litex_wrapper import AXILITEUART @@ -95,6 +96,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axil_uart16550", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--addr_width", type=int, default=16, choices=[8, 16, 32], help="UART Address Width.") diff --git a/rapidsilicon/ip/axil_uart16550/v1_0/litex_wrapper/axil_uart16550_litex_wrapper.py b/rapidsilicon/ip/axil_uart16550/v1_0/litex_wrapper/axil_uart16550_litex_wrapper.py index 8672e0cf..7436244a 100644 --- a/rapidsilicon/ip/axil_uart16550/v1_0/litex_wrapper/axil_uart16550_litex_wrapper.py +++ b/rapidsilicon/ip/axil_uart16550/v1_0/litex_wrapper/axil_uart16550_litex_wrapper.py @@ -8,13 +8,18 @@ # LiteX wrapper around Freecores uart16650's axi4lite_uart_top.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # AXI LITE UART ------------------------------------------------------------------------------------- class AXILITEUART(Module): @@ -22,7 +27,9 @@ def __init__(self, platform, s_axil, address_width, data_width): self.logger = logging.getLogger("AXI_LITE_UART") - self.logger.propagate = False + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") # Clock Domain clock_domain = s_axil.clock_domain @@ -36,6 +43,7 @@ def __init__(self, platform, s_axil, address_width, data_width): data_width = len(s_axil.r.data) self.logger.info(f"DATA_WIDTH : {data_width}") + self.logger.info(f"===================================================") # UART Signals self.int_o = Signal() self.srx_pad_i = Signal() diff --git a/rapidsilicon/ip/axis_adapter/v1_0/axis_adapter_gen.py b/rapidsilicon/ip/axis_adapter/v1_0/axis_adapter_gen.py index 08103cc3..5304bb86 100755 --- a/rapidsilicon/ip/axis_adapter/v1_0/axis_adapter_gen.py +++ b/rapidsilicon/ip/axis_adapter/v1_0/axis_adapter_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axis_adapter_litex_wrapper import AXISADAPTER @@ -88,7 +89,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axis_adapter", language="verilog") - + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--s_data_width", type=int, default=8, choices=[8, 16, 32, 64, 128, 256, 512, 1024], help="Slave Data Width.") diff --git a/rapidsilicon/ip/axis_adapter/v1_0/litex_wrapper/axis_adapter_litex_wrapper.py b/rapidsilicon/ip/axis_adapter/v1_0/litex_wrapper/axis_adapter_litex_wrapper.py index a9e4cb2b..72786884 100644 --- a/rapidsilicon/ip/axis_adapter/v1_0/litex_wrapper/axis_adapter_litex_wrapper.py +++ b/rapidsilicon/ip/axis_adapter/v1_0/litex_wrapper/axis_adapter_litex_wrapper.py @@ -8,13 +8,18 @@ # LiteX wrapper around Alex Forencich Verilog-AXIS's axis_adapter.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # AXIS_ADAPTER --------------------------------------------------------------------------------------- class AXISADAPTER(Module): @@ -22,8 +27,10 @@ def __init__(self, platform, s_axis, m_axis, id_en , dest_en, user_en): self.logger = logging.getLogger("AXIS_ADAPTER") - self.logger.propagate = False - + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") + # Data Width s_data_width = len(s_axis.data) self.logger.info(f"S_DATA_WIDTH : {s_data_width}") @@ -46,6 +53,7 @@ def __init__(self, platform, s_axis, m_axis, id_en , dest_en, user_en): user_width = len(s_axis.user) self.logger.info(f"USER_WIDTH : {user_width}") + self.logger.info(f"===================================================") # Module instance. # ---------------- self.specials += Instance("axis_adapter", diff --git a/rapidsilicon/ip/axis_async_fifo/v1_0/axis_async_fifo_gen.py b/rapidsilicon/ip/axis_async_fifo/v1_0/axis_async_fifo_gen.py index cb922b8e..f5f40a33 100755 --- a/rapidsilicon/ip/axis_async_fifo/v1_0/axis_async_fifo_gen.py +++ b/rapidsilicon/ip/axis_async_fifo/v1_0/axis_async_fifo_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axis_async_fifo_litex_wrapper import AXISASYNCFIFO @@ -140,6 +141,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axis_async_fifo", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--depth", type=int, default=4096, choices=[8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768], help="FIFO Depth.") diff --git a/rapidsilicon/ip/axis_async_fifo/v1_0/litex_wrapper/axis_async_fifo_litex_wrapper.py b/rapidsilicon/ip/axis_async_fifo/v1_0/litex_wrapper/axis_async_fifo_litex_wrapper.py index 86d0ae4e..82ba4f5c 100644 --- a/rapidsilicon/ip/axis_async_fifo/v1_0/litex_wrapper/axis_async_fifo_litex_wrapper.py +++ b/rapidsilicon/ip/axis_async_fifo/v1_0/litex_wrapper/axis_async_fifo_litex_wrapper.py @@ -8,13 +8,18 @@ # LiteX wrapper around Alex Forencich Verilog-AXIS's axis_async_fifo.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # AXIS_ASYNC_FIFO --------------------------------------------------------------------------------------- class AXISASYNCFIFO(Module): @@ -35,7 +40,9 @@ def __init__(self, platform, s_axis, m_axis, self.logger = logging.getLogger("AXI_STREAM_ASYNCHRONUS_FIFO") - self.logger.propagate = False + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") # Depth self.logger.info(f"DEPTH : {depth}") @@ -69,6 +76,8 @@ def __init__(self, platform, s_axis, m_axis, self.logger.info(f"DROP_BAD_FRAME : {drop_bad_frame}") self.logger.info(f"DROP_WHEN_FULL : {drop_when_full}") + self.logger.info(f"===================================================") + # Status Signals self.s_status_overflow = Signal() self.s_status_bad_frame = Signal() diff --git a/rapidsilicon/ip/axis_broadcast/v1_0/axis_broadcast_gen.py b/rapidsilicon/ip/axis_broadcast/v1_0/axis_broadcast_gen.py index 490e7ffd..fe32d5a5 100755 --- a/rapidsilicon/ip/axis_broadcast/v1_0/axis_broadcast_gen.py +++ b/rapidsilicon/ip/axis_broadcast/v1_0/axis_broadcast_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axis_broadcast_litex_wrapper import AXISBROADCAST @@ -89,11 +90,14 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axis_broadcast", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", type=int, default=8, choices=[8, 16, 32, 64, 128, 256, 512, 1024], help="BROADCAST AXIS interface Data Width.") - # Core bool value parameters. core_bool_param_group = parser.add_argument_group(title="Core bool parameters") core_bool_param_group.add_argument("--last_en", type=bool, default=True, help="BROADCAST AXIS tlast signal width.") diff --git a/rapidsilicon/ip/axis_broadcast/v1_0/litex_wrapper/axis_broadcast_litex_wrapper.py b/rapidsilicon/ip/axis_broadcast/v1_0/litex_wrapper/axis_broadcast_litex_wrapper.py index 87ac55b8..515e299a 100644 --- a/rapidsilicon/ip/axis_broadcast/v1_0/litex_wrapper/axis_broadcast_litex_wrapper.py +++ b/rapidsilicon/ip/axis_broadcast/v1_0/litex_wrapper/axis_broadcast_litex_wrapper.py @@ -8,13 +8,18 @@ # LiteX wrapper around Alex Forencich Verilog-AXIS's axis_broadcast.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # AXIS_BROADCAST --------------------------------------------------------------------------------------- class AXISBROADCAST(Module): @@ -22,7 +27,9 @@ def __init__(self, platform, s_axis, m_axis, m_count, last_en, id_en, dest_en, u self.logger = logging.getLogger("AXIS_BROADCAST") - self.logger.propagate = False + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") # Master Interfaces m_count = len(m_axis) @@ -48,6 +55,8 @@ def __init__(self, platform, s_axis, m_axis, m_count, last_en, id_en, dest_en, u user_width = len(s_axis.user) self.logger.info(f"USER_WIDTH : {user_width}") + self.logger.info(f"===================================================") + # Module instance. # ---------------- self.specials += Instance("axis_broadcast", diff --git a/rapidsilicon/ip/axis_fifo/v1_0/axis_fifo_gen.py b/rapidsilicon/ip/axis_fifo/v1_0/axis_fifo_gen.py index de555f13..da9f6697 100755 --- a/rapidsilicon/ip/axis_fifo/v1_0/axis_fifo_gen.py +++ b/rapidsilicon/ip/axis_fifo/v1_0/axis_fifo_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axis_fifo_litex_wrapper import AXISTREAMFIFO @@ -113,11 +114,14 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axis_fifo", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") - core_fix_param_group.add_argument("--depth", type=int, default=4096, choices=[8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768], help="FIFO Depth.") - core_fix_param_group.add_argument("--data_width", type=int, default=8, choices=[8, 16, 32, 64, 128, 256, 512, 1024], help="FIFO Data Width.") - + core_fix_param_group.add_argument("--depth", type=int, default=4096, choices=[8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768], help="FIFO Depth.") + core_fix_param_group.add_argument("--data_width", type=int, default=8, choices=[8, 16, 32, 64, 128, 256, 512, 1024], help="FIFO Data Width.") # Core bool value parameters. core_bool_param_group = parser.add_argument_group(title="Core bool parameters") @@ -134,7 +138,7 @@ def main(): core_range_param_group.add_argument("--id_width", type=int, default=8, choices=range(1, 17), help="FIFO ID Width.") core_range_param_group.add_argument("--dest_width", type=int, default=8, choices=range(1, 9), help="FIFO Destination Width.") core_range_param_group.add_argument("--user_width", type=int, default=1, choices=range(1, 1025), help="FIFO User Width.") - core_range_param_group.add_argument("--pip_out", type=int, default=1, choices=range(1, 33), help="FIFO Pipeline Output registers.") + core_range_param_group.add_argument("--pip_out", type=int, default=1, choices=range(1, 33), help="FIFO Pipeline Output registers.") # Build Parameters. build_group = parser.add_argument_group(title="Build parameters") diff --git a/rapidsilicon/ip/axis_fifo/v1_0/litex_wrapper/axis_fifo_litex_wrapper.py b/rapidsilicon/ip/axis_fifo/v1_0/litex_wrapper/axis_fifo_litex_wrapper.py index 0fc69c6a..9e682779 100644 --- a/rapidsilicon/ip/axis_fifo/v1_0/litex_wrapper/axis_fifo_litex_wrapper.py +++ b/rapidsilicon/ip/axis_fifo/v1_0/litex_wrapper/axis_fifo_litex_wrapper.py @@ -8,13 +8,18 @@ # LiteX wrapper around Alex Forencich Verilog-AXIS's axis_fifo.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # AXIS_FIFO --------------------------------------------------------------------------------------- class AXISTREAMFIFO(Module): @@ -31,8 +36,10 @@ def __init__(self, platform, s_axis, m_axis, ): self.logger = logging.getLogger("AXI_STREAM_FIFO") - self.logger.propagate = False - + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") + # Depth self.logger.info(f"DEPTH : {depth}") @@ -62,6 +69,8 @@ def __init__(self, platform, s_axis, m_axis, self.logger.info(f"DROP_BAD_FRAME : {drop_bad_frame}") self.logger.info(f"DROP_WHEN_FULL : {drop_when_full}") + self.logger.info(f"===================================================") + # Status Signals self.status_overflow = Signal() self.status_bad_frame = Signal() diff --git a/rapidsilicon/ip/axis_interconnect/v1_0/axis_interconnect_gen.py b/rapidsilicon/ip/axis_interconnect/v1_0/axis_interconnect_gen.py index fde18922..93d65b82 100755 --- a/rapidsilicon/ip/axis_interconnect/v1_0/axis_interconnect_gen.py +++ b/rapidsilicon/ip/axis_interconnect/v1_0/axis_interconnect_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse import math @@ -110,6 +111,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axis_interconnect", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", type=int, default=8, choices=[8, 16, 32, 64, 128, 256, 512, 1024], help="Data Width.") diff --git a/rapidsilicon/ip/axis_interconnect/v1_0/litex_wrapper/axis_interconnect_litex_wrapper.py b/rapidsilicon/ip/axis_interconnect/v1_0/litex_wrapper/axis_interconnect_litex_wrapper.py index 8a77f35c..d0b63dd7 100644 --- a/rapidsilicon/ip/axis_interconnect/v1_0/litex_wrapper/axis_interconnect_litex_wrapper.py +++ b/rapidsilicon/ip/axis_interconnect/v1_0/litex_wrapper/axis_interconnect_litex_wrapper.py @@ -8,13 +8,18 @@ # LiteX wrapper around Alex Forencich Verilog-AXIS's axis_crosspoint.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # AXIS_INTERCONNECT --------------------------------------------------------------------------------------- class AXISTREAMINTERCONNECT(Module): @@ -22,7 +27,9 @@ def __init__(self, platform, s_axis, m_axis, m_count, s_count, last_en, id_en, d self.logger = logging.getLogger("AXI_STREAM_INTERCONNECT") - self.logger.propagate = False + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") # Clock Domain. clock_domain = s_axis[0].clock_domain @@ -55,6 +62,8 @@ def __init__(self, platform, s_axis, m_axis, m_count, s_count, last_en, id_en, d self.logger.info(f"USER_ENABLE : {user_en}") user_width = len(s_axis[0].user) self.logger.info(f"USER_WIDTH : {user_width}") + + self.logger.info(f"===================================================") # Control Signal self.select = [Signal(select_width) for m_count in range(m_count)] diff --git a/rapidsilicon/ip/axis_pipeline_register/v1_0/axis_pipeline_register_gen.py b/rapidsilicon/ip/axis_pipeline_register/v1_0/axis_pipeline_register_gen.py index a4c8a4c3..cfb1e48a 100755 --- a/rapidsilicon/ip/axis_pipeline_register/v1_0/axis_pipeline_register_gen.py +++ b/rapidsilicon/ip/axis_pipeline_register/v1_0/axis_pipeline_register_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axis_pipeline_register_litex_wrapper import AXISPIPELINEREGISTER @@ -97,6 +98,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axis_pipeline_register", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core string value parameters. core_string_param_group = parser.add_argument_group(title="Core string parameters") core_string_param_group.add_argument("--reg_type", type=str, default="Bypass", choices=["Bypass", "Simple_Buffer", "Skid_Buffer"], help="Register Type; bypass, simple buffer, skid buffer") diff --git a/rapidsilicon/ip/axis_pipeline_register/v1_0/litex_wrapper/axis_pipeline_register_litex_wrapper.py b/rapidsilicon/ip/axis_pipeline_register/v1_0/litex_wrapper/axis_pipeline_register_litex_wrapper.py index 67cd7b5d..de46813c 100644 --- a/rapidsilicon/ip/axis_pipeline_register/v1_0/litex_wrapper/axis_pipeline_register_litex_wrapper.py +++ b/rapidsilicon/ip/axis_pipeline_register/v1_0/litex_wrapper/axis_pipeline_register_litex_wrapper.py @@ -8,13 +8,18 @@ # LiteX wrapper around Alex Forencich Verilog-AXIS's axis_pipeline_register.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # AXIS_PIPELINE_REGISTER --------------------------------------------------------------------------------------- class AXISPIPELINEREGISTER(Module): @@ -22,7 +27,9 @@ def __init__(self, platform, s_axis, m_axis, last_en, id_en, dest_en, user_en, r self.logger = logging.getLogger("AXIS_PIPELINE_REGISTER") - self.logger.propagate = False + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") # Data data_width = len(s_axis.data) @@ -48,6 +55,8 @@ def __init__(self, platform, s_axis, m_axis, last_en, id_en, dest_en, user_en, r self.logger.info(f"REG_TYPE : {reg_type}") self.logger.info(f"LENGTH : {length}") + self.logger.info(f"===================================================") + # Module instance. # ---------------- self.specials += Instance("axis_pipeline_register", diff --git a/rapidsilicon/ip/axis_ram_switch/v1_0/axis_ram_switch_gen.py b/rapidsilicon/ip/axis_ram_switch/v1_0/axis_ram_switch_gen.py index b155f5a3..540957b1 100755 --- a/rapidsilicon/ip/axis_ram_switch/v1_0/axis_ram_switch_gen.py +++ b/rapidsilicon/ip/axis_ram_switch/v1_0/axis_ram_switch_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse import math @@ -193,6 +194,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axis_ram_switch", language="verilog") + + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) # Core fix value parameters core_fix_param_group = parser.add_argument_group(title="Core fix parameters") diff --git a/rapidsilicon/ip/axis_ram_switch/v1_0/litex_wrapper/axis_ram_switch_litex_wrapper.py b/rapidsilicon/ip/axis_ram_switch/v1_0/litex_wrapper/axis_ram_switch_litex_wrapper.py index 23195e64..2311f998 100644 --- a/rapidsilicon/ip/axis_ram_switch/v1_0/litex_wrapper/axis_ram_switch_litex_wrapper.py +++ b/rapidsilicon/ip/axis_ram_switch/v1_0/litex_wrapper/axis_ram_switch_litex_wrapper.py @@ -8,13 +8,18 @@ # LiteX wrapper around Alex Forencich Verilog-AXIS's axis_ram_switch.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # AXIS_RAM_SWITCH --------------------------------------------------------------------------------------- class AXISTREAMRAMSWITCH(Module): @@ -31,7 +36,9 @@ def __init__(self, platform, s_axis, m_axis, ): self.logger = logging.getLogger("AXI_STREAM_RAM_SWITCH") - self.logger.propagate = False + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") # Data Width data_width = len(s_axis[0].data) @@ -53,7 +60,9 @@ def __init__(self, platform, s_axis, m_axis, # Destination Width self.logger.info(f"M_DEST_WIDTH : {m_dest_width}") - + + self.logger.info(f"===================================================") + # Status Signals self.status_overflow = Signal() self.status_bad_frame = Signal() diff --git a/rapidsilicon/ip/axis_switch/v1_0/axis_switch_gen.py b/rapidsilicon/ip/axis_switch/v1_0/axis_switch_gen.py index 1deae233..a2c1e46d 100755 --- a/rapidsilicon/ip/axis_switch/v1_0/axis_switch_gen.py +++ b/rapidsilicon/ip/axis_switch/v1_0/axis_switch_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse import math @@ -167,6 +168,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axis_switch", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", type=int, default=8, choices=[8, 16, 32, 64, 128, 256, 512, 1024], help="SWITCH Data Width.") diff --git a/rapidsilicon/ip/axis_switch/v1_0/litex_wrapper/axis_switch_litex_wrapper.py b/rapidsilicon/ip/axis_switch/v1_0/litex_wrapper/axis_switch_litex_wrapper.py index 439ab6ba..2015b5f5 100644 --- a/rapidsilicon/ip/axis_switch/v1_0/litex_wrapper/axis_switch_litex_wrapper.py +++ b/rapidsilicon/ip/axis_switch/v1_0/litex_wrapper/axis_switch_litex_wrapper.py @@ -8,13 +8,18 @@ # LiteX wrapper around Alex Forencich Verilog-AXIS's axis_switch.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # AXIS_SWITCH --------------------------------------------------------------------------------------- class AXISTREAMSWITCH(Module): @@ -27,7 +32,9 @@ def __init__(self, platform, s_axis, m_axis, m_connect ): self.logger = logging.getLogger("AXI_STREAM_SWITCH") - self.logger.propagate = False + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") # Data Width data_width = len(s_axis[0].data) @@ -41,6 +48,8 @@ def __init__(self, platform, s_axis, m_axis, # Destination Width self.logger.info(f"M_DEST_WIDTH : {m_dest_width}") + self.logger.info(f"===================================================") + # Module Instance. # ---------------- self.specials += Instance("axis_switch", diff --git a/rapidsilicon/ip/axis_uart/v1_0/axis_uart_gen.py b/rapidsilicon/ip/axis_uart/v1_0/axis_uart_gen.py index 9c346abe..b525be80 100755 --- a/rapidsilicon/ip/axis_uart/v1_0/axis_uart_gen.py +++ b/rapidsilicon/ip/axis_uart/v1_0/axis_uart_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.axis_uart_litex_wrapper import AXISTREAMUART @@ -100,12 +101,14 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axis_uart", language="verilog") - + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", type=int, default=8, choices=[8, 16, 32, 64, 128, 256, 512, 1024], help="UART Data Width.") - # Build Parameters. build_group = parser.add_argument_group(title="Build parameters") build_group.add_argument("--build", action="store_true", help="Build Core") diff --git a/rapidsilicon/ip/axis_uart/v1_0/litex_wrapper/axis_uart_litex_wrapper.py b/rapidsilicon/ip/axis_uart/v1_0/litex_wrapper/axis_uart_litex_wrapper.py index f1e25a4f..4634ca19 100644 --- a/rapidsilicon/ip/axis_uart/v1_0/litex_wrapper/axis_uart_litex_wrapper.py +++ b/rapidsilicon/ip/axis_uart/v1_0/litex_wrapper/axis_uart_litex_wrapper.py @@ -8,14 +8,18 @@ # LiteX wrapper around Alex Forencich verilog-uart's uart.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') -logging.basicConfig(level=logging.INFO) +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # AXIS-UART --------------------------------------------------------------------------------------- class AXISTREAMUART(Module): @@ -23,12 +27,16 @@ def __init__(self, platform, s_axis, m_axis, data_width=5): self.logger = logging.getLogger("AXI_STREAM_UART") - self.logger.propagate = False + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") # Data width. data_width = len(s_axis.data) self.logger.info(f"DATA_WIDTH : {data_width}") + self.logger.info(f"===================================================") + # Uart Signals self.rxd = Signal(1) self.txd = Signal(1) diff --git a/rapidsilicon/ip/axis_width_converter/v1_0/axis_width_converter_gen.py b/rapidsilicon/ip/axis_width_converter/v1_0/axis_width_converter_gen.py index 3fb642ec..4a40d8aa 100755 --- a/rapidsilicon/ip/axis_width_converter/v1_0/axis_width_converter_gen.py +++ b/rapidsilicon/ip/axis_width_converter/v1_0/axis_width_converter_gen.py @@ -66,7 +66,7 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="axis_width_converter", language="verilog") - + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--core_in_width", type=int, default=128, choices=[8, 16, 32, 64, 128, 256, 512, 1024], help="AXI-ST Input Data-width.") diff --git a/rapidsilicon/ip/dsp_generator/v1_0/dsp_generator_gen.py b/rapidsilicon/ip/dsp_generator/v1_0/dsp_generator_gen.py index d8479efd..f151d99c 100755 --- a/rapidsilicon/ip/dsp_generator/v1_0/dsp_generator_gen.py +++ b/rapidsilicon/ip/dsp_generator/v1_0/dsp_generator_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from pathlib import Path from migen import * @@ -156,11 +157,15 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="dsp_generator", language="verilog") + + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) # Core string parameters. core_string_param_group = parser.add_argument_group(title="Core string parameters") core_string_param_group.add_argument("--equation", type=str, default="AxB", choices=["AxB","AxB+CxD","AxB+CxD+ExF+GxH"], help="Select Equation") - core_string_param_group.add_argument("--feature", type=str, default="Base", choices=["Base", "Enhanced", "Pipeline"], help="Select Feature") + core_string_param_group.add_argument("--feature", type=str, default="Base", choices=["Base", "Enhanced", "Pipeline"], help="Select Feature") # Core range value parameters. core_range_param_group = parser.add_argument_group(title="Core range parameters") @@ -177,7 +182,7 @@ def main(): core_bool_param_group = parser.add_argument_group(title="Core bool parameters") core_bool_param_group.add_argument("--reg_in", type=bool, default=False, help="Registered Inputs") core_bool_param_group.add_argument("--reg_out", type=bool, default=False, help="Registered Outputs") - core_bool_param_group.add_argument("--unsigned", type=bool, default=True, help="Unsigned Input") + core_bool_param_group.add_argument("--unsigned", type=bool, default=True, help="Unsigned Input") # Build Parameters. build_group = parser.add_argument_group(title="Build parameters") diff --git a/rapidsilicon/ip/dsp_generator/v1_0/litex_wrapper/dsp_litex_generator.py b/rapidsilicon/ip/dsp_generator/v1_0/litex_wrapper/dsp_litex_generator.py index e722da66..c29de571 100644 --- a/rapidsilicon/ip/dsp_generator/v1_0/litex_wrapper/dsp_litex_generator.py +++ b/rapidsilicon/ip/dsp_generator/v1_0/litex_wrapper/dsp_litex_generator.py @@ -5,13 +5,18 @@ # # SPDX-License-Identifier: MIT +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # RS_DSP_MULT --------------------------------------------------------------------------------------- class RS_DSP_MULT(Module): @@ -21,7 +26,9 @@ def __init__(self, a_width, b_width, equation, reg_in, reg_out, unsigned ): # --------------------- self.logger = logging.getLogger("\tRS_DSP_MULT") - self.logger.propagate = False + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") # Input A. self.logger.info(f"INPUT_A : {a_width}") @@ -36,10 +43,13 @@ def __init__(self, a_width, b_width, equation, reg_in, reg_out, unsigned ): self.logger.info(f"REG_OUT : {reg_out}") # Unsigned Input A. - self.logger.info(f"unsigned : {unsigned}") + self.logger.info(f"UNSIGNED : {unsigned}") # Equation. - self.logger.info(f"equation : {equation}") + self.logger.info(f"EQUATION : {equation}") + + self.logger.info(f"===================================================") + if (unsigned == 0): self.a = Signal(bits_sign=(a_width, True)) self.b = Signal(bits_sign=(b_width, True)) diff --git a/rapidsilicon/ip/fifo_generator/v1_0/fifo_generator_gen.py b/rapidsilicon/ip/fifo_generator/v1_0/fifo_generator_gen.py index fc64d999..8104f761 100755 --- a/rapidsilicon/ip/fifo_generator/v1_0/fifo_generator_gen.py +++ b/rapidsilicon/ip/fifo_generator/v1_0/fifo_generator_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from pathlib import Path import math @@ -25,8 +26,8 @@ def get_clkin_ios(data_width): return [ ("clk", 0, Pins(1)), ("rst", 0, Pins(1)), - ("wrt_clock", 0, Pins(1)), - ("rd_clock", 0, Pins(1)), + ("wrt_clock", 0, Pins(1)), + ("rd_clock", 0, Pins(1)), ("din", 0, Pins(data_width)), ("dout", 0, Pins(data_width)), ("wr_en", 0, Pins(1)), @@ -90,6 +91,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="fifo_generator", language="verilog") + + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) # Core range value parameters. core_range_param_group = parser.add_argument_group(title="Core range parameters") diff --git a/rapidsilicon/ip/fifo_generator/v1_0/litex_wrapper/fifo_litex_generator.py b/rapidsilicon/ip/fifo_generator/v1_0/litex_wrapper/fifo_litex_generator.py index 7cbc8354..08964f74 100644 --- a/rapidsilicon/ip/fifo_generator/v1_0/litex_wrapper/fifo_litex_generator.py +++ b/rapidsilicon/ip/fifo_generator/v1_0/litex_wrapper/fifo_litex_generator.py @@ -7,6 +7,7 @@ # import os +import datetime import logging import math from migen.genlib.fifo import SyncFIFO, AsyncFIFOBuffered @@ -14,8 +15,11 @@ from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') def divide_n_bit_number(number): # Convert the number to a binary string @@ -32,19 +36,23 @@ def divide_n_bit_number(number): class FIFO(Module): def __init__(self, data_width, synchronous, full_threshold, empty_threshold, depth, first_word_fall_through, empty_value, full_value, BRAM): self.logger = logging.getLogger("FIFO") - self.logger.propagate = False + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") # Data Width self.logger.info(f"DATA_WIDTH : {data_width}") # User Width - self.logger.info(f"Synchronous : {synchronous}") + self.logger.info(f"SYNCHRONOUS : {synchronous}") - self.logger.info(f"FULL THRESHOLD : {full_value}") + self.logger.info(f"FULL THRESHOLD : {full_value}") # Destination Width - self.logger.info(f"EMPTY THRESHOLD : {empty_value}") + self.logger.info(f"EMPTY THRESHOLD : {empty_value}") + + self.logger.info(f"===================================================") SYNCHRONOUS = { "TRUE" : True, diff --git a/rapidsilicon/ip/i2c_master/v1_0/i2c_master_gen.py b/rapidsilicon/ip/i2c_master/v1_0/i2c_master_gen.py index 891d3202..0ae83175 100755 --- a/rapidsilicon/ip/i2c_master/v1_0/i2c_master_gen.py +++ b/rapidsilicon/ip/i2c_master/v1_0/i2c_master_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.i2c_master_litex_wrapper import I2CMASTER @@ -94,6 +95,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="i2c_master", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core bool value parameters. core_bool_param_group = parser.add_argument_group(title="Core bool parameters") core_bool_param_group.add_argument("--default_prescale", type=bool, default=True, help="I2C Default Prescale.") diff --git a/rapidsilicon/ip/i2c_master/v1_0/litex_wrapper/i2c_master_litex_wrapper.py b/rapidsilicon/ip/i2c_master/v1_0/litex_wrapper/i2c_master_litex_wrapper.py index d1dbd972..3675f011 100644 --- a/rapidsilicon/ip/i2c_master/v1_0/litex_wrapper/i2c_master_litex_wrapper.py +++ b/rapidsilicon/ip/i2c_master/v1_0/litex_wrapper/i2c_master_litex_wrapper.py @@ -8,13 +8,18 @@ # LiteX wrapper around Alex Forencich verilog-i2c's i2c_master_axil.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # I2C_MASTER ------------------------------------------------------------------------------------- class I2CMASTER(Module): @@ -22,7 +27,9 @@ def __init__(self, platform, s_axil, default_prescale, fixed_prescale, cmd_fifo, self.logger = logging.getLogger("I2C_MASTER") - self.logger.propagate = False + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") # DEFAULT_PRESCALE self.logger.info(f"DEFAULT_PRESCALE : {default_prescale}") @@ -48,6 +55,8 @@ def __init__(self, platform, s_axil, default_prescale, fixed_prescale, cmd_fifo, # READ_FIFO_ADDR_WIDTH self.logger.info(f"READ_FIFO_ADDR_WIDTH : {read_addr_width}") + self.logger.info(f"===================================================") + # I2C interface self.i2c_scl_i = Signal() self.i2c_scl_o = Signal() diff --git a/rapidsilicon/ip/i2c_slave/v1_0/i2c_slave_gen.py b/rapidsilicon/ip/i2c_slave/v1_0/i2c_slave_gen.py index 410e1469..c90859f4 100755 --- a/rapidsilicon/ip/i2c_slave/v1_0/i2c_slave_gen.py +++ b/rapidsilicon/ip/i2c_slave/v1_0/i2c_slave_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.i2c_slave_litex_wrapper import I2CSLAVE @@ -106,6 +107,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="i2c_slave", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", type=int, default=32, choices=[32, 64], help="I2C_slave Data Width.") diff --git a/rapidsilicon/ip/i2c_slave/v1_0/litex_wrapper/i2c_slave_litex_wrapper.py b/rapidsilicon/ip/i2c_slave/v1_0/litex_wrapper/i2c_slave_litex_wrapper.py index 20834133..a69d7a40 100644 --- a/rapidsilicon/ip/i2c_slave/v1_0/litex_wrapper/i2c_slave_litex_wrapper.py +++ b/rapidsilicon/ip/i2c_slave/v1_0/litex_wrapper/i2c_slave_litex_wrapper.py @@ -8,13 +8,18 @@ # LiteX wrapper around Alex Forencich verilog-i2c's i2c_slave_axil_master.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # I2C_SLAVE ------------------------------------------------------------------------------------- class I2CSLAVE(Module): @@ -22,7 +27,9 @@ def __init__(self, platform, m_axil, filter_len): self.logger = logging.getLogger("I2C_SLAVE") - self.logger.propagate = False + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") # DATA_WIDTH data_width = len(m_axil.w.data) @@ -35,6 +42,8 @@ def __init__(self, platform, m_axil, filter_len): # FILTER_LENGTH self.logger.info(f"FILTER_LENGTH : {filter_len}") + self.logger.info(f"===================================================") + # I2C interface self.i2c_scl_i = Signal() self.i2c_scl_o = Signal() diff --git a/rapidsilicon/ip/jtag_to_axi/v1_0/jtag_to_axi_gen.py b/rapidsilicon/ip/jtag_to_axi/v1_0/jtag_to_axi_gen.py index 9c5e515f..435c2102 100755 --- a/rapidsilicon/ip/jtag_to_axi/v1_0/jtag_to_axi_gen.py +++ b/rapidsilicon/ip/jtag_to_axi/v1_0/jtag_to_axi_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.jtag_to_axi_litex_wrapper import JTAGAXI @@ -45,9 +46,8 @@ def __init__(self, platform, data_width, addr_width, s_id_width, aw_user_width, self.clock_domains.cd_sys = ClockDomain() self.comb += self.cd_sys.clk.eq(platform.request("ACLK")) self.comb += self.cd_sys.rst.eq(platform.request("ARESET")) - + m_id_width = s_id_width - m_axis = [] m_axi = AXIInterface(data_width = data_width , address_width = addr_width, id_width = m_id_width, aw_user_width = aw_user_width, @@ -85,6 +85,10 @@ def main(): # IP Builder rs_builder = IP_Builder(device="gemini", ip_name="jtag_to_axi", language="sverilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fixed values parameters core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--data_width", type=int, default=32, choices=[32, 64], help="AXI Data Width.") diff --git a/rapidsilicon/ip/jtag_to_axi/v1_0/litex_wrapper/jtag_to_axi_litex_wrapper.py b/rapidsilicon/ip/jtag_to_axi/v1_0/litex_wrapper/jtag_to_axi_litex_wrapper.py index f0333406..4173a12f 100755 --- a/rapidsilicon/ip/jtag_to_axi/v1_0/litex_wrapper/jtag_to_axi_litex_wrapper.py +++ b/rapidsilicon/ip/jtag_to_axi/v1_0/litex_wrapper/jtag_to_axi_litex_wrapper.py @@ -8,13 +8,18 @@ # LiteX wrapper around jtag_to_axi_top.v import os +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # JTAG_AXILIT --------------------------------------------------------------------------------- class JTAGAXI(Module): @@ -22,7 +27,9 @@ def __init__(self, platform, m_axi): self.logger = logging.getLogger("JTAG_TO_AXI") - self.logger.propagate = False + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") # Clock Domain. clock_domain = m_axi[0].clock_domain @@ -60,6 +67,8 @@ def __init__(self, platform, m_axi): r_user_width = len(m_axi[0].r.user) self.logger.info(f"RUSER_WIDTH : {r_user_width}") + self.logger.info(f"===================================================") + self.JTAG_TCK = Signal(1) self.JTAG_TMS = Signal(1) self.JTAG_TDI = Signal(1) diff --git a/rapidsilicon/ip/on_chip_memory/v1_0/litex_wrapper/on_chip_memory_litex_wrapper.py b/rapidsilicon/ip/on_chip_memory/v1_0/litex_wrapper/on_chip_memory_litex_wrapper.py index ebbf3208..7faac3b1 100644 --- a/rapidsilicon/ip/on_chip_memory/v1_0/litex_wrapper/on_chip_memory_litex_wrapper.py +++ b/rapidsilicon/ip/on_chip_memory/v1_0/litex_wrapper/on_chip_memory_litex_wrapper.py @@ -8,13 +8,18 @@ # LiteX wrapper around on chip memory. import math +import datetime import logging from migen import * from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # On Chip Memory ------------------------------------------------------------------------------------------ class OCM(Module): @@ -25,17 +30,35 @@ def memory_converter(self, file_path, file_extension): with open(file_path, "r") as f: file_content = f.readlines() line_count = 0 + self.logger.info(f"========== MEMORY INITIALIZATION STARTED ==========") + logging.info("Reading Memory File") + if (file_extension == ".hex"): + logging.info("Found (.hex) File") + logging.info("Processing") + elif (file_extension == ".bin"): + logging.info("Found (.bin) File") + logging.info("Processing") + else: + logging.error("Memory Initialization Failed. Invalid File Format") + for line in file_content: line_count += 1 if (file_extension == ".hex"): mem_file_data = int(line.strip(), 16) binary = format(mem_file_data, 'b') # hexadecimal to binary conversion + binary_data.append(binary) + self.binary_data = binary_data + self.line_count = line_count elif (file_extension == ".bin"): mem_file_data = int(line.strip(), 2) # binary(0b10101) to binary(10101) conversion binary = format(mem_file_data, 'b') - binary_data.append(binary) - self.binary_data = binary_data - self.line_count = line_count + binary_data.append(binary) + self.binary_data = binary_data + self.line_count = line_count + else: + exit + self.binary_data = 0 + self.line_count = 0 return binary_data def memory_init(self, file_path, file_extension): @@ -45,11 +68,12 @@ def memory_init(self, file_path, file_extension): result = [] # Empty File Path - if file_path == "": + if (file_path == "") or (self.line_count == 0): return "x" # If File Path Exists if self.write_depth in [1024, 2048, 4096, 8192, 16384, 32768]: + # 1K Memory Initialization if (self.write_depth == 1024): if (len(self.binary_data) > self.write_depth): @@ -95,6 +119,8 @@ def memory_init(self, file_path, file_extension): sram[data2] = "".join(sram[sram2][::-1]) # inverting indexing of list sram[sram_result] = sram[data1] + sram[data2] result.append(sram[sram_result]) + logging.info("Memory Initialized Successfully !!!") + self.logger.info(f"===================================================") return result # 2K Memory Initialization @@ -143,6 +169,8 @@ def memory_init(self, file_path, file_extension): sram[data2] = "".join(sram[sram2][::-1]) sram[sram_result] = sram[data2] + sram[data1] result.append(sram[sram_result]) + logging.info("Memory Initialized Successfully !!!") + self.logger.info(f"===================================================") return result # 4K Memory Initialization @@ -190,6 +218,8 @@ def memory_init(self, file_path, file_extension): sram[data2] = "".join(sram[sram2][::-1]) sram[sram_result] = sram[data2] + sram[data1] result.append(sram[sram_result]) + logging.info("Memory Initialized Successfully !!!") + self.logger.info(f"===================================================") return result # 8K Memory @@ -239,6 +269,8 @@ def memory_init(self, file_path, file_extension): sram[data2] = "".join(sram[sram2][::-1]) sram[sram_result] = sram[data2] + sram[data1] result.append(sram[sram_result]) + logging.info("Memory Initialized Successfully !!!") + self.logger.info(f"===================================================") return result # 16K Memory @@ -287,6 +319,8 @@ def memory_init(self, file_path, file_extension): sram[data2] = "".join(sram[sram2][::-1]) sram[sram_result] = sram[data2] + sram[data1] result.append(sram[sram_result]) + logging.info("Memory Initialized Successfully !!!") + self.logger.info(f"===================================================") return result # 32K Memory @@ -326,11 +360,14 @@ def memory_init(self, file_path, file_extension): sram[data2] = "".join(sram[sram2][::-1]) sram[sram_result] = sram[data2] + sram[data1] result.append(sram[sram_result]) + logging.info("Memory Initialized Successfully !!!") + self.logger.info(f"===================================================") return result # Other Memory Size Initialization else: lines = self.line_count + for i in range(lines): if self.data_width % 36 == 0: valid_data_width = self.data_width @@ -375,6 +412,8 @@ def memory_init(self, file_path, file_extension): sram[data2] = "".join(sram[sram2][::-1]) # inverting indexing of SRAM2 sram[sram_result] = sram[data1] + sram[data2] result.append(sram[sram_result]) + logging.info("Memory Initialized Successfully !!!") + self.logger.info(f"===================================================") return result def __init__(self, platform, data_width, memory_type, common_clk, write_depth, bram, file_path, file_extension): @@ -386,15 +425,19 @@ def __init__(self, platform, data_width, memory_type, common_clk, write_depth, b # --------------------- self.logger = logging.getLogger("\tON CHIP MEMORY") - self.logger.propagate = False + self.logger.propagate = True - self.logger.info(f"\tMEMORY TYPE : {memory_type}") + self.logger.info(f"=================== PARAMETERS ====================") - self.logger.info(f"\tDEPTH : {write_depth}") + self.logger.info(f"MEMORY_TYPE : {memory_type}") - self.logger.info(f"\tDATA WIDTH : {data_width}") + self.logger.info(f"DATA_WIDTH : {data_width}") - self.logger.info(f"\tCOMMON CLK : {common_clk}") + self.logger.info(f"WRITE_DEPTH : {write_depth}") + + self.logger.info(f"COMMON_CLK : {common_clk}") + + self.logger.info(f"BRAM : {bram}") self.addr_A = Signal(math.ceil(math.log2(write_depth))) self.addr_B = Signal(math.ceil(math.log2(write_depth))) @@ -449,6 +492,12 @@ def __init__(self, platform, data_width, memory_type, common_clk, write_depth, b n = math.ceil(n) self.m = m self.n = n + + if (bram == 1): + self.logger.info(f"NUMBER OF BRAMS : {m*n}") + + self.logger.info(f"===================================================") + msb = math.ceil(math.log2(write_depth)) # Internal Addresses self.address_A = Signal(msb) @@ -838,7 +887,7 @@ def __init__(self, platform, data_width, memory_type, common_clk, write_depth, b mode_bits = Instance.PreformattedParam("81'b{:d}".format(mode)) for j in range(m): - if (file_path == ""): + if (file_path == "") or (self.line_count == 0): value = 'x' else: if write_depth in [1024, 2048, 4096, 8192, 16384, 32768]: diff --git a/rapidsilicon/ip/on_chip_memory/v1_0/on_chip_memory_gen.py b/rapidsilicon/ip/on_chip_memory/v1_0/on_chip_memory_gen.py index cb33f29d..596cfb41 100755 --- a/rapidsilicon/ip/on_chip_memory/v1_0/on_chip_memory_gen.py +++ b/rapidsilicon/ip/on_chip_memory/v1_0/on_chip_memory_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse from litex_wrapper.on_chip_memory_litex_wrapper import * @@ -111,7 +112,11 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="on_chip_memory", language="verilog") - + + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core string value parameters. core_string_param_group = parser.add_argument_group(title="Core string parameters") core_string_param_group.add_argument("--memory_type", type=str, default="Single_Port", choices=["Single_Port", "Simple_Dual_Port", "True_Dual_Port"], help="RAM Type") @@ -134,7 +139,7 @@ def main(): build_group = parser.add_argument_group(title="Build parameters") build_group.add_argument("--build", action="store_true", help="Build Core") build_group.add_argument("--build-dir", default="./", help="Build Directory") - build_group.add_argument("--build-name", default="on_chip_memory_wrapper", help="Build Folder Name, Build RTL File Name and Module Name") + build_group.add_argument("--build-name", default="on_chip_memory", help="Build Folder Name, Build RTL File Name and Module Name") # JSON Import/Template json_group = parser.add_argument_group(title="JSON Parameters") diff --git a/rapidsilicon/ip/priority_encoder/v1_0/litex_wrapper/priority_encoder_litex_wrapper.py b/rapidsilicon/ip/priority_encoder/v1_0/litex_wrapper/priority_encoder_litex_wrapper.py index db33f372..80280b5e 100644 --- a/rapidsilicon/ip/priority_encoder/v1_0/litex_wrapper/priority_encoder_litex_wrapper.py +++ b/rapidsilicon/ip/priority_encoder/v1_0/litex_wrapper/priority_encoder_litex_wrapper.py @@ -8,6 +8,7 @@ # LiteX wrapper around Alex Forencich verilog-axi's priority_encoder.v import os +import datetime import math import logging @@ -15,7 +16,11 @@ from litex.soc.interconnect.axi import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # PRIORITY_ENCODER --------------------------------------------------------------------------------------- class PRIORITYENCODER(Module): @@ -24,12 +29,16 @@ def __init__(self, platform, width, lsb_high_priority): # Logger self.logger = logging.getLogger("PRIORITY_ENCODER") - self.logger.propagate = False + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") self.logger.info(f"WIDTH : {width}") self.logger.info(f"LSB_HIGH_PRIORITY : {lsb_high_priority}") + self.logger.info(f"===================================================") + self.input_unencoded = Signal(width) self.output_valid = Signal() self.output_encoded = Signal(math.ceil(math.log2(width))) diff --git a/rapidsilicon/ip/priority_encoder/v1_0/priority_encoder_gen.py b/rapidsilicon/ip/priority_encoder/v1_0/priority_encoder_gen.py index 3130844c..135fb55d 100755 --- a/rapidsilicon/ip/priority_encoder/v1_0/priority_encoder_gen.py +++ b/rapidsilicon/ip/priority_encoder/v1_0/priority_encoder_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse import math @@ -52,7 +53,6 @@ def __init__(self, platform, width, lsb_high_priority): self.comb += platform.request("output_encoded").eq(priority_encoder.output_encoded) self.comb += platform.request("output_unencoded").eq(priority_encoder.output_unencoded) - # Build -------------------------------------------------------------------------------------------- def main(): parser = argparse.ArgumentParser(description="PRIORITY_ENCODER") @@ -70,6 +70,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="priority_encoder", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core bool value parameters. core_bool_param_group = parser.add_argument_group(title="Core bool parameters") core_bool_param_group.add_argument("--lsb_high_priority", type=bool, default=False, help="LSB High Priority.") diff --git a/rapidsilicon/ip/reset_release/v1_0/litex_wrapper/reset_release_litex_wrapper.py b/rapidsilicon/ip/reset_release/v1_0/litex_wrapper/reset_release_litex_wrapper.py index 87df8b45..fa376ae7 100644 --- a/rapidsilicon/ip/reset_release/v1_0/litex_wrapper/reset_release_litex_wrapper.py +++ b/rapidsilicon/ip/reset_release/v1_0/litex_wrapper/reset_release_litex_wrapper.py @@ -9,11 +9,16 @@ import os import math +import datetime import logging from migen import * -logging.basicConfig(level=logging.INFO) +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') # RESET RELEASE --------------------------------------------------------------------------------------- class RESETRELEASE(Module): @@ -22,13 +27,17 @@ def __init__(self, platform, EXT_RESET_WIDTH, INTERCONNECTS, BUS_RESET, PERIPHER # Logger self.logger = logging.getLogger("RESET_RELEASE") - self.logger.propagate = False + self.logger.propagate = True + + self.logger.info(f"=================== PARAMETERS ====================") + + self.logger.info(f"EXTERNAL RESET WINDOW : {EXT_RESET_WIDTH}") + self.logger.info(f"INTERCONNECTS : {INTERCONNECTS}") + self.logger.info(f"BUS_RESET : {BUS_RESET}") + self.logger.info(f"PERIPHERAL_RESET : {PERIPHERAL_RESET}") + self.logger.info(f"PERIPHERAL_ARESETN : {PERIPHERAL_ARESETN}") - self.logger.info(f"External reset window : {EXT_RESET_WIDTH}") - self.logger.info(f"INTERCONNECTS : {INTERCONNECTS}") - self.logger.info(f"BUS_RESET : {BUS_RESET}") - self.logger.info(f"PERIPHERAL_RESET : {PERIPHERAL_RESET}") - self.logger.info(f"PERIPHERAL_ARESETN : {PERIPHERAL_ARESETN}") + self.logger.info(f"===================================================") self.slow_clk = Signal() self.ext_rst = Signal() diff --git a/rapidsilicon/ip/reset_release/v1_0/reset_release_gen.py b/rapidsilicon/ip/reset_release/v1_0/reset_release_gen.py index 0532b7f0..42a051ca 100755 --- a/rapidsilicon/ip/reset_release/v1_0/reset_release_gen.py +++ b/rapidsilicon/ip/reset_release/v1_0/reset_release_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse import math @@ -17,7 +18,6 @@ from litex.build.osfpga import OSFPGAPlatform - # IOs/Interfaces ----------------------------------------------------------------------------------- def get_clkin_ios(): return [ @@ -85,6 +85,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="reset_release", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core fix value parameters. core_fix_param_group = parser.add_argument_group(title="Core fix parameters") core_fix_param_group.add_argument("--ext_reset_width", type=int, default=5, choices=[4,5,6,7,8,9,10], help="External reset window.") @@ -93,7 +97,6 @@ def main(): core_fix_param_group.add_argument("--bus_reset", type=int, default=1, choices=[1,2,3,4,5,6,7,8,9,10], help="Number of bus reserts.") core_fix_param_group.add_argument("--peripheral_reset", type=int, default=1, choices=[1,2,3,4,5,6,7,8,9,10], help="Number of peripheral resets.") - # Build Parameters. build_group = parser.add_argument_group(title="Build parameters") build_group.add_argument("--build", action="store_true", help="Build Core") diff --git a/rapidsilicon/ip/vexriscv_cpu/v1_0/litex_wrapper/vexriscv_cpu_litex_wrapper.py b/rapidsilicon/ip/vexriscv_cpu/v1_0/litex_wrapper/vexriscv_cpu_litex_wrapper.py index d0b20958..41b946ba 100644 --- a/rapidsilicon/ip/vexriscv_cpu/v1_0/litex_wrapper/vexriscv_cpu_litex_wrapper.py +++ b/rapidsilicon/ip/vexriscv_cpu/v1_0/litex_wrapper/vexriscv_cpu_litex_wrapper.py @@ -8,9 +8,17 @@ # LiteX wrapper around SpinalHDL VexRiscv import os +import datetime +import logging from migen import * +# logging.basicConfig(level=logging.INFO) +logging.basicConfig(filename="IP.log",filemode="w", level=logging.INFO, format='%(levelname)s: %(message)s\n') + +timestamp = datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') +logging.info(f'Log started at {timestamp}') + ## ----------------VexRiscv Configuration without Cache and MMU---------------------------------------- class vexriscv_nocache_nommu(Module): @@ -55,9 +63,6 @@ def __init__(self, platform, dbus): self.ibus_r_resp = Signal(2) self.ibus_r_last = Signal() - - - # CPU Instance. self.specials += Instance("vexriscv_uncached_nommu", # Clk / Rst. diff --git a/rapidsilicon/ip/vexriscv_cpu/v1_0/vexriscv_cpu_gen.py b/rapidsilicon/ip/vexriscv_cpu/v1_0/vexriscv_cpu_gen.py index 7d598005..6336a40d 100755 --- a/rapidsilicon/ip/vexriscv_cpu/v1_0/vexriscv_cpu_gen.py +++ b/rapidsilicon/ip/vexriscv_cpu/v1_0/vexriscv_cpu_gen.py @@ -6,6 +6,7 @@ import os import sys +import logging import argparse import shutil from pathlib import Path @@ -259,6 +260,10 @@ def main(): # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="vexriscv_cpu", language="verilog") + logging.info("===================================================") + logging.info("IP : %s", rs_builder.ip_name.upper()) + logging.info(("===================================================")) + # Core string parameters. core_string_param_group = parser.add_argument_group(title="Core string parameters") core_string_param_group.add_argument("--variant", type=str, default="Cacheless", choices=["Cacheless", "Cache_MMU", "Cache_MMU_PLIC_CLINT"], help="Select Variant")