added version, type, id registers

rapidsilicon/ip/i2c_master/v1_0/src/i2c_master_axil.v

@@ -62,7 +62,7 @@ module i2c_master_axil #
     output wire [1:0]  s_axil_bresp,
     output wire        s_axil_bvalid,
     input  wire        s_axil_bready,
-    input  wire [3:0]  s_axil_araddr,
+    input  wire [4:0]  s_axil_araddr,
     input  wire [2:0]  s_axil_arprot,
     input  wire        s_axil_arvalid,
     output wire        s_axil_arready,
@@ -299,6 +299,14 @@ I/O pin.  This would prevent devices from stretching the clock period.
 
 */
 
+// Adding Registers for the IP TYPE, VERSION and ID in memory map
+
+reg [31:0] IP_TYPE_REG  = IP_TYPE;
+reg [31:0] IP_VERSION_REG = IP_VERSION;
+reg [31:0] IP_ID_REG = IP_ID;
+
+// --------------------------------------------------------------
+
 reg s_axil_awready_reg = 1'b0, s_axil_awready_next;
 reg s_axil_wready_reg = 1'b0, s_axil_wready_next;
 reg s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
@@ -603,7 +611,7 @@ always @* begin
         s_axil_rvalid_next = 1'b1;
         s_axil_rdata_next = 32'd0;
 
-        case ({s_axil_araddr[3:2], 2'b00})
+        case ({s_axil_araddr[4:2], 2'b00})
             4'h0: begin
                 // status
                 s_axil_rdata_next[0]  = busy_int;
@@ -647,6 +655,18 @@ always @* begin
                 // prescale
                 s_axil_rdata_next = prescale_reg;
             end
+            5'h10: begin
+                // ip type register
+                s_axil_rdata_next = IP_TYPE_REG;
+            end
+            5'h14: begin
+                // ip version register
+                s_axil_rdata_next = IP_VERSION_REG;
+            end
+            5'h18: begin
+                // ip id register
+                s_axil_rdata_next = IP_ID_REG;
+            end
         endcase
     end
 end