Updated json generation mechanism

os-fpga · Oct 2, 2023 · b2257ed · b2257ed
1 parent 6db388e
commit b2257ed
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Showing 3 changed files with 31 additions and 7 deletions.
diff --git a/rapidsilicon/ip/axi_async_fifo/v1_0/axi_async_fifo_gen.py b/rapidsilicon/ip/axi_async_fifo/v1_0/axi_async_fifo_gen.py
@@ -121,21 +121,22 @@ def main():
 
 
     summary =  { 
-    "AXI Data width programmed": 32,
-    "AXI ID width programmed": 4,
+    "AXI Data width programmed": args.data_width,
+    "AXI ID width programmed": args.id_width,
     "Memory Type selected": "Single Dual Port",
-    "Number of Brams 36k utilized": 5
   }
 
 
 
     # Import JSON (Optional) -----------------------------------------------------------------------
     if args.json:
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
+        rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version    = "v1_0")
 
     # Export JSON Template (Optional) --------------------------------------------------------------
 
     # Create Wrapper -------------------------------------------------------------------------------
+
     platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")
     module   = AXIASYNCFIFOWrapper(platform,
         data_width   = args.data_width,
@@ -162,7 +163,6 @@ def main():
     if args.json_template:
         rs_builder.export_json_template(parser=parser, dep_dict=dep_dict , summary=summary)
     #Exporting Details.json
-        rs_builder.import_ip_details_json(json_filename=args.json, build_dir=args.build_dir ,details=details)
 
 
 

diff --git a/rapidsilicon/ip/on_chip_memory/v1_0/on_chip_memory_gen.py b/rapidsilicon/ip/on_chip_memory/v1_0/on_chip_memory_gen.py
@@ -139,9 +139,12 @@ def main():
 
     args = parser.parse_args()
 
+
     # Import JSON (Optional) -----------------------------------------------------------------------
     fabric_mem = 4194432
     if args.json:
+            #Exporting Details.json
+
         args_1 = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
         for key, value in vars(args).items():
             if args_1.data_width <= 128 and args_1.data_width > 64 :
@@ -169,9 +172,28 @@ def main():
                 parser._actions[3].default = 1024
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
 
+        rs_builder.import_ip_details_json(json_filename=args.json, build_dir=args.build_dir ,details=details , build_name = args.build_name, version= "v1_0")
+
+
+
+    details =  {   "IP details": {
+    'Name' : 'axi_asynchronus_fifo',
+    'Version' : 'V1_0',
+    'Interface' : 'AXI',
+    'Description' : 'The AXI Async FIFO is an AXI full compliant customize-able asynchronous FIFO. It can be used to store and retrieve ordered data at different clock domains, while using optimal resources.'}}
+
+
+    summary =  { 
+    "AXI Data width programmed": args.data_width,
+    "Write depth selected": args.write_depth,
+    "Memory Type selected": args.memory_type,
+  }
+    if args.common_clk:
+        summary["common clock has been selected"] = args.common_clk
+
     # Export JSON Template (Optional) --------------------------------------------------------------
     if args.json_template:
-        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
+        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict , summary=summary)
 
     # Create Wrapper -------------------------------------------------------------------------------
     platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")

diff --git a/rapidsilicon/lib/common.py b/rapidsilicon/lib/common.py
@@ -192,8 +192,10 @@ def import_args_from_json(self, parser, json_filename):
             args = parser.parse_args(namespace=t_args)
         return args
 
-    def import_ip_details_json(self, json_filename, build_dir,details):
-        new_json_filename   = os.path.join(build_dir, "details.json")
+    def import_ip_details_json(self, build_dir,details, build_name, version ):
+        self.build_name         = build_name
+        self.build_path         = os.path.join(build_dir, "rapidsilicon", "ip", self.ip_name, version, build_name)
+        new_json_filename       = os.path.join(self.build_path, "details.json")
         with open(new_json_filename, "w") as f:
             json.dump(details, f, indent=4, default=None,)