Merge branch 'main' into mem_initialization_loggers

os-fpga · Aug 28, 2023 · a6a37e9 · a6a37e9
2 parents a2e4e13 + ef5d6b5
commit a6a37e9
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diff --git a/rapidsilicon/ip/axil_ocla/v1_0/litex_wrapper/axil_ocla_litex_wrapper.py b/rapidsilicon/ip/axil_ocla/v1_0/litex_wrapper/axil_ocla_litex_wrapper.py
@@ -68,6 +68,7 @@ def __init__(self, platform,
             # -----------  
             p_IP_TYPE                 = Instance.PreformattedParam("IP_TYPE"),
             p_IP_ID                   = Instance.PreformattedParam("IP_ID"),
+            p_IP_VERSION              = Instance.PreformattedParam("IP_VERSION"),
             p_NO_OF_PROBES            = Instance.PreformattedParam(nprobes),
             p_NO_OF_TRIGGER_INPUTS    = Instance.PreformattedParam(trigger_inputs),
             p_PROBE_WIDHT             = Instance.PreformattedParam(probe_widht),