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axi_async fifo changes
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bilalahmed-RS committed Oct 2, 2023
1 parent 2c33423 commit 84624a6
Showing 1 changed file with 24 additions and 44 deletions.
68 changes: 24 additions & 44 deletions rapidsilicon/ip/axi_async_fifo/v1_0/axi_async_fifo_gen.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,12 +7,9 @@
import os
import sys
import json
import logging
import argparse
import math

from datetime import datetime

from litex_wrapper.axi_async_fifo_litex_wrapper import AXIASYNCFIFO

from migen import *
Expand Down Expand Up @@ -91,10 +88,6 @@ def main():
# IP Builder.
rs_builder = IP_Builder(device="gemini", ip_name="axi_async_fifo", language="verilog")

logging.info("===================================================")
logging.info("IP : %s", rs_builder.ip_name.upper())
logging.info(("==================================================="))

# Core fix value parameters.
core_fix_param_group = parser.add_argument_group(title="Core fix parameters")
core_fix_param_group.add_argument("--fifo_depth", type=int, default=4096, choices=[8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192,16384,32768], help="FIFO Depth.")
Expand All @@ -119,17 +112,31 @@ def main():

args = parser.parse_args()


details = { "IP details": {
'Name' : 'axi_asynchronus_fifo',
'Version' : 'V1_0',
'Interface' : 'AXI',
'Description' : 'The AXI Async FIFO is an AXI full compliant customize-able asynchronous FIFO. It can be used to store and retrieve ordered data at different clock domains, while using optimal resources.'}}


summary = {
"AXI Data width programmed": args.data_width,
"AXI ID width programmed": args.id_width,
"Memory Type selected": "Single Dual Port",
}



# Import JSON (Optional) -----------------------------------------------------------------------
if args.json:
args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version = "v1_0")

# Export JSON Template (Optional) --------------------------------------------------------------
if args.json_template:
rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)



# Create Wrapper -------------------------------------------------------------------------------

platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")
module = AXIASYNCFIFOWrapper(platform,
data_width = args.data_width,
Expand All @@ -152,39 +159,12 @@ def main():
platform = platform,
module = module,
)

# IP_ID Parameter
now = datetime.now()
my_year = now.year - 2022
year = (bin(my_year)[2:]).zfill(7) # 7-bits # Removing '0b' prefix = [2:]
month = (bin(now.month)[2:]).zfill(4) # 4-bits
day = (bin(now.day)[2:]).zfill(5) # 5-bits
mod_hour = now.hour % 12 # 12 hours Format
hour = (bin(mod_hour)[2:]).zfill(4) # 4-bits
minute = (bin(now.minute)[2:]).zfill(6) # 6-bits
second = (bin(now.second)[2:]).zfill(6) # 6-bits

# Concatenation for IP_ID Parameter
ip_id = ("{}{}{}{}{}{}").format(year, day, month, hour, minute, second)
ip_id = ("32'h{}").format(hex(int(ip_id,2))[2:])

# IP_VERSION parameter
# Base _ Major _ Minor
ip_version = "00000000_00000000_0000000000000001"
ip_version = ("32'h{}").format(hex(int(ip_version, 2))[2:])

wrapper = os.path.join(args.build_dir, "rapidsilicon", "ip", "axi_async_fifo", "v1_0", args.build_name, "src",args.build_name+".v")
new_lines = []
with open (wrapper, "r") as file:
lines = file.readlines()
for i, line in enumerate(lines):
if ("module {}".format(args.build_name)) in line:
new_lines.append("module {} #(\n\tparameter IP_TYPE \t\t= \"ASYNCFFO\",\n\tparameter IP_VERSION \t= {}, \n\tparameter IP_ID \t\t= {}\n)\n(".format(args.build_name, ip_version, ip_id))
else:
new_lines.append(line)

with open(os.path.join(wrapper), "w") as file:
file.writelines(new_lines)

if args.json_template:
rs_builder.export_json_template(parser=parser, dep_dict=dep_dict , summary=summary)
#Exporting Details.json



if __name__ == "__main__":
main()

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