Merge branch 'backend' of github.com:RapidSilicon/IP_Catalog into bac…

…kend
os-fpga · Oct 6, 2023 · 2eeaa88 · 2eeaa88
2 parents 9c21857 + 32020f3
commit 2eeaa88
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Showing 9 changed files with 192 additions and 49 deletions.
diff --git a/rapidsilicon/ip/axi_cdma/v1_0/axi_cdma_gen.py b/rapidsilicon/ip/axi_cdma/v1_0/axi_cdma_gen.py
@@ -122,17 +122,19 @@ def main():
     core_fix_param_group = parser.add_argument_group(title="Core fix parameters")
     core_fix_param_group.add_argument("--data_width",        type=int,      default=32,     choices=[8, 16, 32, 64, 128, 256], help="DMA Data Width.")
 
-    # Core bool value parameters.
-    core_bool_param_group = parser.add_argument_group(title="Core bool parameters")
-    core_bool_param_group.add_argument("--enable_unaligned",  type=bool,    default=True,    help="Support for unaligned transfers.")
-
-    # Core range value parameters.
+     # Core range value parameters.
     core_range_param_group = parser.add_argument_group(title="Core range parameters")
     core_range_param_group.add_argument("--addr_width",        type=int,    default=16,     choices=range(8, 17),    help="DMA Address Width.")
     core_range_param_group.add_argument("--id_width",          type=int,    default=8,      choices=range(1, 33),    help="DMA ID Width.")
     core_range_param_group.add_argument("--axi_max_burst_len", type=int,    default=16,     choices=range(1,257),    help="DMA AXI burst length.")
     core_range_param_group.add_argument("--len_width",         type=int,    default=20,     choices=range(1,21),     help="DMA AXI Width of length field.")
     core_range_param_group.add_argument("--tag_width",         type=int,    default=8,      choices=range(1,9),      help="DMA Width of tag field.")
+
+    # Core bool value parameters.
+    core_bool_param_group = parser.add_argument_group(title="Core bool parameters")
+    core_bool_param_group.add_argument("--enable_unaligned",  type=bool,    default=True,    help="Support for unaligned transfers.")
+
+
 
     # Build Parameters.
     build_group = parser.add_argument_group(title="Build parameters")
@@ -147,13 +149,31 @@ def main():
 
     args = parser.parse_args()
 
+    details =  {   "IP details": {
+    'Name' : 'CDMA',
+    'Version' : 'V1_0',
+    'Interface' : 'AXI4 ',
+    'Description' : 'Central DMA (CDMA) is a type of Direct Memory Access (DMA) that provides high-bandwidth Direct Memory Access (DMA) between a memory-mapped source address and a memory-mapped destination address using the AXI4 protocol'}
+    }
+
+    summary =  { 
+    # "DATA WIDTH": args.data_width,
+    "DATA WIDTH":args.data_width,
+    "ADDR WIDTH": args.addr_width,
+    "BURST LENGTH": args.axi_max_burst_len,
+    "TAG WIDTH": args.tag_width,
+    # "PIPELINE OUTPUT": args.pip_out
+    }
+
     # Import JSON (Optional) -----------------------------------------------------------------------
     if args.json:
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
+        rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version = "v1_0")
+
 
     # Export JSON Template (Optional) --------------------------------------------------------------
     if args.json_template:
-        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
+        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)
 
     # Create Wrapper -------------------------------------------------------------------------------
     platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")

diff --git a/rapidsilicon/ip/axi_cdma/v2_0/axi_cdma_gen.py b/rapidsilicon/ip/axi_cdma/v2_0/axi_cdma_gen.py
@@ -105,14 +105,30 @@ def main():
     json_group.add_argument("--json-template",  action="store_true",     help="Generate JSON Template")
 
     args = parser.parse_args()
-
+    details =  {   "IP details": {
+    'Name' : 'CDMA',
+    'Version' : 'V2_0',
+    'Interface' : 'AXI4-Lite/AXI4 FULL ',
+    'Description' : 'Central DMA (CDMA) is a type of Direct Memory Access (DMA) that provides high-bandwidth Direct Memory Access (DMA) between a memory-mapped source address and a memory-mapped destination address using the AXI4 protocol'}
+    }
+
+    summary =  { 
+    # "DATA WIDTH": args.data_width,
+    "AXI4 DATA WIDTH":args.axi_data_width,
+    "AXI4 DDR WIDTH": args.axi_addr_width,
+    "AXI4-LITE DATA WIDTH":args.axil_data_width,
+    "AXI4-LITE ADDR WIDTH": args.axil_addr_width,
+    # "PIPELINE OUTPUT": args.pip_out
+    }
     # Import JSON (Optional) -----------------------------------------------------------------------
     if args.json:
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
+        rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version = "v2_0")
+
 
     # Export JSON Template (Optional) --------------------------------------------------------------
     if args.json_template:
-        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
+        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)
 
     # Create Wrapper -------------------------------------------------------------------------------
     platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")

diff --git a/rapidsilicon/ip/axi_crossbar/v1_0/axi_crossbar_gen.py b/rapidsilicon/ip/axi_crossbar/v1_0/axi_crossbar_gen.py
@@ -118,15 +118,7 @@ def main():
     core_fix_param_group.add_argument("--data_width",    type=int,      default=32,     choices=[8, 16, 32, 64, 128, 256],  help="AXI Data Width.")
     core_fix_param_group.add_argument("--addr_width",    type=int,      default=32,     choices=[32, 64],                   help="AXI Address Width.")
 
-    # Core bool value parameters.
-    core_bool_param_group = parser.add_argument_group(title="Core bool parameters")
-    core_bool_param_group.add_argument("--aw_user_en",    type=bool,    default=True,      help="AW-Channel User Enable.")
-    core_bool_param_group.add_argument("--w_user_en",     type=bool,    default=False,     help="W-Channel User Enable.")
-    core_bool_param_group.add_argument("--b_user_en",     type=bool,    default=False,     help="B-Channel User Enable.")
-    core_bool_param_group.add_argument("--ar_user_en",    type=bool,    default=True,      help="AR-Channel User Enable.")
-    core_bool_param_group.add_argument("--r_user_en",     type=bool,    default=False,     help="R-Channel User Enable.")
-
-    # Core range value parameters.
+     # Core range value parameters.
     core_range_param_group = parser.add_argument_group(title="Core range parameters")
     core_range_param_group.add_argument("--m_count",            type=int,       default=4,      choices=range(2,17),         help="Crossbar Master Interfaces.")
     core_range_param_group.add_argument("--s_count",            type=int,       default=4,      choices=range(1,17),         help="Crossbar SLAVE Interfaces.")
@@ -137,6 +129,15 @@ def main():
     core_range_param_group.add_argument("--ar_user_width",      type=int,       default=1,      choices=range(1, 1025),      help="AR-Channel User Width.")
     core_range_param_group.add_argument("--r_user_width",       type=int,       default=1,      choices=range(1, 1025),      help="R-Channel User Width.")
 
+    # Core bool value parameters.
+    core_bool_param_group = parser.add_argument_group(title="Core bool parameters")
+    core_bool_param_group.add_argument("--aw_user_en",    type=bool,    default=True,      help="AW-Channel User Enable.")
+    core_bool_param_group.add_argument("--w_user_en",     type=bool,    default=False,     help="W-Channel User Enable.")
+    core_bool_param_group.add_argument("--b_user_en",     type=bool,    default=False,     help="B-Channel User Enable.")
+    core_bool_param_group.add_argument("--ar_user_en",    type=bool,    default=True,      help="AR-Channel User Enable.")
+    core_bool_param_group.add_argument("--r_user_en",     type=bool,    default=False,     help="R-Channel User Enable.")
+
+
     # Build Parameters.
     build_group = parser.add_argument_group(title="Build parameters")
     build_group.add_argument("--build",         action="store_true",                help="Build Core")
@@ -149,14 +150,27 @@ def main():
     json_group.add_argument("--json-template",  action="store_true",            help="Generate JSON Template")
 
     args = parser.parse_args()
-
+    details =  {   "IP details": {
+    'Name' : 'AXI Crossbar',
+    'Version' : 'V1_0',
+    'Interface' : 'AXI4 ',
+    'Description' : 'The AXI4 Full Crossbar is AXI4 compliance IP core that connects one or more AXI memory mapped master devices to more memory mapped slave devices. Supports all burst types.Fully nonblocking with completely separate read and write paths; ID-based transaction ordering protection logic; and per-port address decode and decode error handling.'}
+    }
     # Import JSON (Optional) -----------------------------------------------------------------------
     if args.json:
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
-
+        rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version = "v1_0")
+
+    summary =  { 
+    # "DATA WIDTH": args.data_width,
+    "MASTER COUNT":args.m_count,
+    "SLAVE COUNT": args.s_count,
+    # "PIPELINE OUTPUT": args.pip_out
+    }
     # Export JSON Template (Optional) --------------------------------------------------------------
     if args.json_template:
-        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
+        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)
+
 
     # Create Wrapper -------------------------------------------------------------------------------
     platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")

diff --git a/rapidsilicon/ip/axi_crossbar/v2_0/axi_crossbar_gen.py b/rapidsilicon/ip/axi_crossbar/v2_0/axi_crossbar_gen.py
@@ -147,15 +147,6 @@ def main():
     core_fix_param_group.add_argument("--data_width",    type=int,      default=32,     choices=[8, 16, 32, 64, 128, 256],    help="AXI Data Width.")
     core_fix_param_group.add_argument("--addr_width",    type=int,      default=32,     choices=[32, 64],                     help="AXI Address Width.")
 
-    # Core bool value parameters.
-    core_bool_param_group = parser.add_argument_group(title="Core bool parameters")
-    core_bool_param_group.add_argument("--aw_user_en",    type=bool,    default=True,      help="AW-Channel User Enable.")
-    core_bool_param_group.add_argument("--w_user_en",     type=bool,    default=False,     help="W-Channel User Enable.")
-    core_bool_param_group.add_argument("--b_user_en",     type=bool,    default=False,     help="B-Channel User Enable.")
-    core_bool_param_group.add_argument("--ar_user_en",    type=bool,    default=True,      help="AR-Channel User Enable.")
-    core_bool_param_group.add_argument("--r_user_en",     type=bool,    default=False,     help="R-Channel User Enable.")  
-    core_bool_param_group.add_argument("--bram",          type=bool,    default=True,      help="Memory type")       
-
     # Core range value parameters.
     core_range_param_group = parser.add_argument_group(title="Core range parameters")
     core_range_param_group.add_argument("--m_count",            type=int,       default=4,      choices=range(1,5),          help="Crossbar Master Interfaces.")
@@ -167,6 +158,15 @@ def main():
     core_range_param_group.add_argument("--ar_user_width",      type=int,       default=1,      choices=range(1, 1025),      help="AR-Channel User Width.")
     core_range_param_group.add_argument("--r_user_width",       type=int,       default=1,      choices=range(1, 1025),      help="R-Channel User Width.")
 
+    # Core bool value parameters.
+    core_bool_param_group = parser.add_argument_group(title="Core bool parameters")
+    core_bool_param_group.add_argument("--aw_user_en",    type=bool,    default=True,      help="AW-Channel User Enable.")
+    core_bool_param_group.add_argument("--w_user_en",     type=bool,    default=False,     help="W-Channel User Enable.")
+    core_bool_param_group.add_argument("--b_user_en",     type=bool,    default=False,     help="B-Channel User Enable.")
+    core_bool_param_group.add_argument("--ar_user_en",    type=bool,    default=True,      help="AR-Channel User Enable.")
+    core_bool_param_group.add_argument("--r_user_en",     type=bool,    default=False,     help="R-Channel User Enable.")  
+    core_bool_param_group.add_argument("--bram",          type=bool,    default=True,      help="Memory type")       
+
     # Build Parameters.
     build_group = parser.add_argument_group(title="Build parameters")
     build_group.add_argument("--build",         action="store_true",                help="Build Core")
@@ -180,13 +180,28 @@ def main():
 
     args = parser.parse_args()
 
+    details =  {   "IP details": {
+    'Name' : 'AXI Crossbar',
+    'Version' : 'V2_0',
+    'Interface' : 'AXI4 ',
+    'Description' : 'The AXI4 Full Crossbar is AXI4 compliance IP core that connects one or more AXI memory mapped master devices to more memory mapped slave devices. It support different clock for each interface. Supports all burst types.Fully nonblocking with completely separate read and write paths; ID-based transaction ordering protection logic; and per-port address decode and decode error handling.'}
+    }
+
     # Import JSON (Optional) -----------------------------------------------------------------------
     if args.json:
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
+        rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version = "v2_0")
+
+    summary =  { 
+    # "DATA WIDTH": args.data_width,
+    "MASTER COUNT":args.m_count,
+    "SLAVE COUNT": args.s_count,
+    # "PIPELINE OUTPUT": args.pip_out
+    }
 
     # Export JSON Template (Optional) --------------------------------------------------------------
     if args.json_template:
-        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
+        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)
 
     # Create Wrapper -------------------------------------------------------------------------------
     platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")

diff --git a/rapidsilicon/ip/axil_crossbar/v1_0/axil_crossbar_gen.py b/rapidsilicon/ip/axil_crossbar/v1_0/axil_crossbar_gen.py
@@ -114,14 +114,28 @@ def main():
     json_group.add_argument("--json-template",  action="store_true",            help="Generate JSON Template")
 
     args = parser.parse_args()
+    details =  {   "IP details": {
+    'Name' : 'AXI Crossbar Lite',
+    'Version' : 'V1_0',
+    'Interface' : 'AXI4 Lite ',
+    'Description' : 'The AXI4 Lite Crossbar is AXI4 compliance IP core that connects one or more AXI memory mapped master devices to more memory mapped slave devices. Supports all burst types.  Fully nonblocking with completely separate read and write paths; FIFO-based transaction ordering protection logic; and per-port address decode, and decode error handling'}
+    }
 
     # Import JSON (Optional) -----------------------------------------------------------------------
     if args.json:
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
-
+        rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version = "v1_0")
+
+    summary =  { 
+    # "DATA WIDTH": args.data_width,
+    "MASTER COUNT":args.m_count,
+    "SLAVE COUNT": args.s_count,
+    # "PIPELINE OUTPUT": args.pip_out
+    }
     # Export JSON Template (Optional) --------------------------------------------------------------
     if args.json_template:
-        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
+        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)
+
 
     # Create Wrapper -------------------------------------------------------------------------------
     platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")

diff --git a/rapidsilicon/ip/axil_crossbar/v2_0/axil_crossbar_gen.py b/rapidsilicon/ip/axil_crossbar/v2_0/axil_crossbar_gen.py
@@ -126,14 +126,14 @@ def main():
     core_fix_param_group.add_argument("--data_width",    type=int,      default=32,     choices=[32, 64],  help="Crossbar Data Width.")
     core_fix_param_group.add_argument("--addr_width",    type=int,      default=32,     choices=[32, 64, 128, 256],         help="Crossbar Address Width.")
 
-    # Core bool value parameters.
-    core_bool_param_group = parser.add_argument_group(title="Core bool parameters")
-    core_bool_param_group.add_argument("--bram",     type=bool,     default=True,      help="Memory type")
-
     # Core range value parameters.
     core_range_param_group = parser.add_argument_group(title="Core range parameters")
     core_range_param_group.add_argument("--m_count",     type=int,      default=4,       choices=range(1,5),               help="Crossbar Master Interfaces.")
     core_range_param_group.add_argument("--s_count",     type=int,      default=4,       choices=range(1,5),               help="Crossbar Slave Interfaces.")
+
+    # Core bool value parameters.
+    core_bool_param_group = parser.add_argument_group(title="Core bool parameters")
+    core_bool_param_group.add_argument("--bram",     type=bool,     default=True,      help="Memory type")
 
     # Build Parameters.
     build_group = parser.add_argument_group(title="Build parameters")
@@ -147,14 +147,29 @@ def main():
     json_group.add_argument("--json-template",  action="store_true",            help="Generate JSON Template")
 
     args = parser.parse_args()
+    details =  {   "IP details": {
+    'Name' : 'AXI Crossbar Lite',
+    'Version' : 'V2_0',
+    'Interface' : 'AXI4 Lite ',
+    'Description' : 'The AXI4 Lite Crossbar is AXI4 compliance IP core that connects one or more AXI memory mapped master devices to more memory mapped slave devices. It has multiple clock support for each interface. Supports all burst types.  Fully nonblocking with completely separate read and write paths; FIFO-based transaction ordering protection logic; and per-port address decode, and decode error handling'}
+    }
+
 
     # Import JSON (Optional) -----------------------------------------------------------------------
     if args.json:
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
+        rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version = "v2_0")
+    summary =  { 
+    # "DATA WIDTH": args.data_width,
+    "MASTER COUNT":args.m_count,
+    "SLAVE COUNT": args.s_count,
+    # "PIPELINE OUTPUT": args.pip_out
+    }
 
     # Export JSON Template (Optional) --------------------------------------------------------------
     if args.json_template:
-        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
+        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)
+
 
     # Create Wrapper -------------------------------------------------------------------------------
     platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")

diff --git a/rapidsilicon/ip/axil_eio/v1_0/axil_eio_gen.py b/rapidsilicon/ip/axil_eio/v1_0/axil_eio_gen.py
@@ -116,13 +116,31 @@ def main():
 
     args = parser.parse_args()
 
+    details =  {   "IP details": {
+    'Name' : 'EIO',
+    'Version' : 'V1_0',
+    'Interface' : 'AXI4-Lite ',
+    'Description' : 'The Emulate-IO core is an AXI4-Lite compliant IP that offers input and output probes to sample and drive signals on FPGA fabric. The core provides an AXI4-slave interface that can be used to control the emulated IOs in real time.'}
+    }
     # Import JSON (Optional) -----------------------------------------------------------------------
     if args.json:
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
+        rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version = "v1_0")
+
+    summary =  { 
+    # "DATA WIDTH": args.data_width,
+    "DATA WIDTH":args.data_width,
+    "ADDR WIDTH": args.addr_width,
+    "INPUT PROBE WIDTH": args.input_probe_width,
+    "OUTPUT PROBE WIDTH": args.output_probe_width,
+
+
+    # "PIPELINE OUTPUT": args.pip_out
+    }
 
     # Export JSON Template (Optional) --------------------------------------------------------------
     if args.json_template:
-        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
+        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict, summary=summary)
 
     # Create Wrapper -------------------------------------------------------------------------------
     platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")