PLL generator updates with backend support

rapidsilicon/ip/boot_clock/v1_0/boot_clock_gen.py

@@ -93,7 +93,7 @@ def main():
 
 
     summary =  { 
-    "Frequency in MHz =": 40,
+    "Frequency in MHz " : 40,
   }
 
 

rapidsilicon/ip/boot_clock/v1_0/src/BOOT_CLOCK.v

@@ -7,7 +7,7 @@
 // Copyright (c) 2023 Rapid Silicon, Inc.  All rights reserved.
 //
 
-module BOOT_CLOCK #(
+module BOOT_CLOCK #( 
   parameter PERIOD = 25.0 // Clock period for simulation purposes (nS)
 ) (
   output reg O = 1'b0 // Clock output

rapidsilicon/ip/pll/v1_0/litex_wrapper/pll_litex_wrapper.py

@@ -38,7 +38,7 @@ def colorer(s, color="bright"):
 # PLL Wrapper ------------------------------------------------------------------------------------
 
 class PLL(Module):
-    def __init__(self, platform, divide_clk_in_by_2, pll_mult, pll_div, clk_out0_div, clk_out1_div, clk_out2_div, clk_out3_div, **kwargs):
+    def __init__(self, platform, divided_clks, divide_clk_in_by_2, fast_clk_freq, ref_clk_freq, clk_out0_div, clk_out1_div, clk_out2_div, clk_out3_div, **kwargs):
         self.logger = logging.getLogger("PLL")
         self.logger.propagate = True
 
@@ -51,8 +51,8 @@ def __init__(self, platform, divide_clk_in_by_2, pll_mult, pll_div, clk_out0_div
         self.logger.info(f"=================== PARAMETERS ====================")
 
         self.logger.info(f"DIVIDE_CLK_IN_BY_2   : {divide_clk_in_by_2}")
-        self.logger.info(f"PLL_MULT             : {pll_mult}")
-        self.logger.info(f"PLL_DIV              : {pll_div}")
+#        self.logger.info(f"PLL_MULT             : {pll_mult}")
+#        self.logger.info(f"PLL_DIV              : {pll_div}")
         self.logger.info(f"CLK_OUT0_DIV         : {clk_out0_div}")
         self.logger.info(f"CLK_OUT1_DIV         : {clk_out1_div}")
         self.logger.info(f"CLK_OUT2_DIV         : {clk_out2_div}")
@@ -73,32 +73,35 @@ def __init__(self, platform, divide_clk_in_by_2, pll_mult, pll_div, clk_out0_div
         self.GEARBOX_FAST_CLK = Signal()
         self.LOCK = Signal()
 
-        self.specials += Instance("PLL",
-            **kwargs,
 
-            p_DIVIDE_CLK_IN_BY_2    = Instance.PreformattedParam(divide_clk_in_by_2),
-            p_PLL_MULT              = Instance.PreformattedParam(pll_mult),
-            p_PLL_DIV               = Instance.PreformattedParam(pll_div),
-            p_CLK_OUT0_DIV          = Instance.PreformattedParam(clk_out0_div),
-            p_CLK_OUT1_DIV          = Instance.PreformattedParam(clk_out1_div),
-            p_CLK_OUT2_DIV          = Instance.PreformattedParam(clk_out2_div),
-            p_CLK_OUT3_DIV          = Instance.PreformattedParam(clk_out3_div),
-
-            i_PLL_EN                = self.PLL_EN,
-            i_CLK_IN                = self.CLK_IN,
-            i_CLK_OUT0_EN           = self.CLK_OUT0_EN,
-            i_CLK_OUT1_EN           = self.CLK_OUT1_EN,
-            i_CLK_OUT2_EN           = self.CLK_OUT2_EN,
-            i_CLK_OUT3_EN           = self.CLK_OUT3_EN,
-            o_CLK_OUT0              = self.CLK_OUT0,
-            o_CLK_OUT1              = self.CLK_OUT1,
-            o_CLK_OUT2              = self.CLK_OUT2,
-            o_CLK_OUT3              = self.CLK_OUT3,
-            o_GEARBOX_FAST_CLK      = self.GEARBOX_FAST_CLK,
-            o_LOCK                  = self.LOCK
-        )
-
-        self.add_sources(platform)
+        if divided_clks == 3:
+            self.specials += Instance("PLL",
+                **kwargs,
+
+                p_DIVIDED_CLKS          = Instance.PreformattedParam(divided_clks),
+                P_DIVIDE_CLK_IN_BY_2    = Instance.PreformattedParam(divide_clk_in_by_2),
+                p_FAST_CLK_FREQ         = Instance.PreformattedParam(fast_clk_freq),
+                p_REF_CLK_FREQ          = Instance.PreformattedParam(ref_clk_freq),
+                p_CLK_OUT0_DIV          = Instance.PreformattedParam(clk_out0_div),
+                p_CLK_OUT1_DIV          = Instance.PreformattedParam(clk_out1_div),
+                p_CLK_OUT2_DIV          = Instance.PreformattedParam(clk_out2_div),
+                p_CLK_OUT3_DIV          = Instance.PreformattedParam(clk_out3_div),
+
+                i_PLL_EN                = 1,
+                i_CLK_IN                = self.CLK_IN,
+                i_CLK_OUT0_EN           = self.CLK_OUT0_EN,
+                i_CLK_OUT1_EN           = 0,
+                i_CLK_OUT2_EN           = 0,
+                i_CLK_OUT3_EN           = 0,
+                o_CLK_OUT0              = self.CLK_OUT0,
+                o_CLK_OUT1              = self.CLK_OUT1,
+                o_CLK_OUT2              = self.CLK_OUT2,
+                o_CLK_OUT3              = self.CLK_OUT3,
+                o_GEARBOX_FAST_CLK      = self.GEARBOX_FAST_CLK,
+                o_LOCK                  = self.LOCK
+            )
+
+            self.add_sources(platform)
 
     @staticmethod
     def add_sources(platform):

rapidsilicon/ip/pll/v1_0/pll_gen.py

@@ -39,15 +39,16 @@ def get_clkin_ios():
 
 # AXI RAM Wrapper ----------------------------------------------------------------------------------
 class PLLWrapper(Module):
-    def __init__(self, platform, divide_clk_in_by_2, pll_mult, pll_div, clk_out0_div, clk_out1_div, clk_out2_div, clk_out3_div):
+    def __init__(self, platform, divided_clks, divide_clk_in_by_2, fast_clk_freq, ref_clk_freq, clk_out0_div, clk_out1_div, clk_out2_div, clk_out3_div):
 
         self.clock_domains.cd_sys  = ClockDomain()
 
         # AXI-RAM ----------------------------------------------------------------------------------
         self.submodules.pll = pll = PLL(platform,
+            divided_clks        =   divided_clks,
             divide_clk_in_by_2  =   divide_clk_in_by_2, 
-            pll_mult            =   pll_mult,
-            pll_div             =   pll_div,
+            fast_clk_freq       =   fast_clk_freq,
+            ref_clk_freq        =   ref_clk_freq,
             clk_out0_div        =   clk_out0_div,
             clk_out1_div        =   clk_out1_div,
             clk_out2_div        =   clk_out2_div,
@@ -94,29 +95,27 @@ def main():
 
     # Core fix value parameters.
     core_fix_param_group = parser.add_argument_group(title="Core fix parameters")
+    core_fix_param_group.add_argument("--divided_clks",   type=int,   default=4,     choices=[1,2,3,4],    help="Divided clocks to be generated from fast clock")
     core_fix_param_group.add_argument("--clk_out0_div",   type=int,   default=2,     choices=[2,3,4,5,6,7,8,10,12,16,20.24,32,40,48,64],    help="CLK_OUT0 divider value")
     core_fix_param_group.add_argument("--clk_out1_div",   type=int,   default=2,     choices=[2,3,4,5,6,7,8,10,12,16,20.24,32,40,48,64],    help="CLK_OUT1 divider value")
     core_fix_param_group.add_argument("--clk_out2_div",   type=int,   default=2,     choices=[2,3,4,5,6,7,8,10,12,16,20.24,32,40,48,64],    help="CLK_OUT2 divider value")
     core_fix_param_group.add_argument("--clk_out3_div",   type=int,   default=2,     choices=[2,3,4,5,6,7,8,10,12,16,20.24,32,40,48,64],    help="CLK_OUT3 divider value")
 
     # Core range value parameters.
     core_range_param_group = parser.add_argument_group(title="Core range parameters")
-    core_range_param_group.add_argument("--pll_mult",     type=int,   default=16,     choices=range(16,1000),     help="RAM Address Width")
-    core_range_param_group.add_argument("--pll_div",       type=int,   default=1,      choices=range(1, 63),     help="RAM ID Width")
+    core_range_param_group.add_argument("--fast_clk_freq",     type=int,   default=1600,     choices=range(800,3201),     help="Freq in MHz")
+    core_range_param_group.add_argument("--ref_clk_freq",       type=int,   default=5,      choices=range(5, 1201),     help="RAM ID Width")
 
     # Core bool value parameters.
     core_bool_param_group = parser.add_argument_group(title="Core bool parameters")
     core_bool_param_group.add_argument("--divide_clk_in_by_2",    type=bool,   default=False,    help="RAM Pipelined Output")
 
-    # Core file path parameters.
-    # core_file_path_group = parser.add_argument_group(title="Core file path parameters")
-    # core_file_path_group.add_argument("--file_path", type=argparse.FileType('r'), help="File Path for memory initialization file")
 
     # Build Parameters.
     build_group = parser.add_argument_group(title="Build parameters")
     build_group.add_argument("--build",         action="store_true",            help="Build Core")
     build_group.add_argument("--build-dir",     default="./",                   help="Build Directory")
-    build_group.add_argument("--build-name",    default="pll_wrapper",      help="Build Folder Name, Build RTL File Name and Module Name")
+    build_group.add_argument("--build-name",    default="pll_wrapper",          help="Build Folder Name, Build RTL File Name and Module Name")
 
     # JSON Import/Template
     json_group = parser.add_argument_group(title="JSON Parameters")
@@ -125,20 +124,49 @@ def main():
 
     args = parser.parse_args()
 
+    if (args.divided_clks == 1):
+        option_strings_to_remove = ['--clk_out1_div', '--clk_out2_div' , '--clk_out3_div']
+        parser._actions = [action for action in parser._actions if action.option_strings and action.option_strings[0] not in option_strings_to_remove]
+
+#        parser._actions = [action for argument_name in option_strings_to_remove: 
+#            for action in parser._actions:
+#                if action.option_strings and argument_name in action.option_strings:
+#                    parser._remove_action(action)]
+    elif(args.divided_clks == 2):
+        option_strings_to_remove = ['--clk_out2_div' , '--clk_out3_div']
+        parser._actions = [action for action in parser._actions if action.option_strings and action.option_strings[0] not in option_strings_to_remove]
+    elif(args.divided_clks == 3):
+        option_strings_to_remove = ['--clk_out3_div']
+        parser._actions = [action for action in parser._actions if action.option_strings and action.option_strings[0] not in option_strings_to_remove]
+
+    details =  {"IP details": {
+    'Name' : 'PLL',
+    'Version' : 'V1_0',
+    'Interface' : 'Native',
+    'Description' : "PLL IP core is a key component in chip design, used to generate stable clock signals from an input reference clock. Its essential for precise synchronization and clock management in modern integrated circuits, ensuring reliable performance across various applications."}}
+
+
+    summary =  { 
+    "Frequency in MHz =": 40,
+  }
+
     # Import JSON (Optional) -----------------------------------------------------------------------
     if args.json:
         args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json)
+        rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version    = "v1_0")
 
     # Export JSON Template (Optional) --------------------------------------------------------------
     if args.json_template:
-        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict)
+        rs_builder.export_json_template(parser=parser, dep_dict=dep_dict , summary=summary)
+
 
     # Create Wrapper -------------------------------------------------------------------------------
     platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini")
     module   = PLLWrapper(platform,
               divide_clk_in_by_2=args.divide_clk_in_by_2,
-              pll_mult=args.pll_mult,
-              pll_div=args.pll_div,
+              divided_clks=args.divided_clks,
+              fast_clk_freq=args.fast_clk_freq,
+              ref_clk_freq=args.ref_clk_freq,
               clk_out0_div=args.clk_out0_div,
               clk_out1_div=args.clk_out1_div,
               clk_out2_div=args.clk_out2_div,

rapidsilicon/ip/pll/v1_0/src/PLL.v

@@ -81,10 +81,10 @@ module PLL #(
   parameter DIVIDE_CLK_IN_BY_2 = "FALSE", // Enable input divider (TRUE/FALSE)
   parameter PLL_MULT = 16, // Clock multiplier value (16-1000)
   parameter PLL_DIV = 1, // Clock divider value (1-63)
-  parameter CLK_OUT0_DIV = 2, // CLK_OUT0 divider value (2,3,4,5,6,7,8,10,12,16,20.24.32.40,48,64)
-  parameter CLK_OUT1_DIV = 2, // CLK_OUT1 divider value (2,3,4,5,6,7,8,10,12,16,20.24.32.40,48,64)
-  parameter CLK_OUT2_DIV = 2, // CLK_OUT2 divider value (2,3,4,5,6,7,8,10,12,16,20.24.32.40,48,64)
-  parameter CLK_OUT3_DIV = 2 //  CLK_OUT3 divider value (2,3,4,5,6,7,8,10,12,16,20.24.32.40,48,64)
+  parameter CLK_OUT0_DIV = 2, // CLK_OUT0 divider value (2,3,4,5,6,7,8,10,12,16,20.24.32.40,48,64)    () 
+  parameter CLK_OUT1_DIV = 2, // CLK_OUT1 divider value (2,3,4,5,6,7,8,10,12,16,20.24.32.40,48,64)    ()
+  parameter CLK_OUT2_DIV = 2, // CLK_OUT2 divider value (2,3,4,5,6,7,8,10,12,16,20.24.32.40,48,64)    ()
+  parameter CLK_OUT3_DIV = 2 //  CLK_OUT3 divider value (2,3,4,5,6,7,8,10,12,16,20.24.32.40,48,64)    ()
 ) (
   input  PLL_EN, // PLL Enable
   input  CLK_IN, // Clock input

rapidsilicon/lib/common.py

@@ -41,7 +41,7 @@ def add_wrapper_header(self, filename):
 
 
     # JSON template for GUI parsing
-    def export_json_template(self, parser, dep_dict):
+    def export_json_template(self, parser, dep_dict, summary):
 
         # Get "core_fix_param_group" group.
         core_fix_param_group = None
@@ -171,6 +171,11 @@ def export_json_template(self, parser, dep_dict):
                 param_json["parameters"][i].update(disable = dep_dict[param_json["parameters"][i]['parameter']])
 
 
+    #Append summary in JSON
+        summary_temp = {"Summary": summary}
+        param_json.update(summary_temp)
+
+
 
     # Append Build and Json params to final json
         for i in range(len(build_param_list)):
@@ -186,7 +191,13 @@ def import_args_from_json(self, parser, json_filename):
             t_args.__dict__.update(json.load(f))
             args = parser.parse_args(namespace=t_args)
         return args
-
+
+    def import_ip_details_json(self, build_dir,details, build_name, version ):
+        self.build_name         = build_name
+        self.build_path         = os.path.join(build_dir, "rapidsilicon", "ip", self.ip_name, version, build_name)
+        new_json_filename       = os.path.join(self.build_path, "details.json")
+        with open(new_json_filename, "w") as f:
+            json.dump(details, f, indent=4, default=None,)
 
 
     def prepare(self, build_dir, build_name, version):
@@ -296,7 +307,7 @@ def generate_tcl(self):
 
     def generate_wrapper(self, platform, module):
         assert self.prepared
-        build_path     = self.build_path + "build_dir"
+        build_path     = "litex_build"
         build_filename = os.path.join(build_path, self.build_name) + ".v"
 
         # Build LiteX module.