diff --git a/rapidsilicon/ip/axi_async_fifo/v1_0/axi_async_fifo_gen.py b/rapidsilicon/ip/axi_async_fifo/v1_0/axi_async_fifo_gen.py index 5f6f0c6b..4d0ae0b2 100755 --- a/rapidsilicon/ip/axi_async_fifo/v1_0/axi_async_fifo_gen.py +++ b/rapidsilicon/ip/axi_async_fifo/v1_0/axi_async_fifo_gen.py @@ -119,9 +119,26 @@ def main(): args = parser.parse_args() + + details = { "IP details": { + 'Name' : 'axi_asynchronus_fifo', + 'Version' : 'V1_0', + 'Interface' : 'AXI', + 'Description' : 'The AXI Async FIFO is an AXI full compliant customize-able asynchronous FIFO. It can be used to store and retrieve ordered data at different clock domains, while using optimal resources.'}} + + + summary = { + "AXI Data width programmed": args.data_width, + "AXI ID width programmed": args.id_width, + "Memory Type selected": "Single Dual Port", + } + + + # Import JSON (Optional) ----------------------------------------------------------------------- if args.json: args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json) + rs_builder.import_ip_details_json(build_dir=args.build_dir ,details=details , build_name = args.build_name, version = "v1_0") # Export JSON Template (Optional) -------------------------------------------------------------- if args.json_template: diff --git a/rapidsilicon/ip/boot_clock/v1_0/boot_clock_gen.py b/rapidsilicon/ip/boot_clock/v1_0/boot_clock_gen.py index 438a6c73..a90729cc 100755 --- a/rapidsilicon/ip/boot_clock/v1_0/boot_clock_gen.py +++ b/rapidsilicon/ip/boot_clock/v1_0/boot_clock_gen.py @@ -56,7 +56,7 @@ def main(): # Parameter Dependency dictionary # Ports : Dependency - dep_dict = {} + dep_dict = {'period' : 'True'} # IP Builder. rs_builder = IP_Builder(device="gemini", ip_name="boot_clock", language="verilog") @@ -84,13 +84,27 @@ def main(): args = parser.parse_args() + + details = {"IP details": { + 'Name' : 'Boot Clock', + 'Version' : 'V1_0', + 'Interface' : 'Native', + 'Description' : 'This is an oscillator IP.'}} + + + summary = { + "Frequency in MHz " : 40, + } + + # Import JSON (Optional) ----------------------------------------------------------------------- if args.json: args = rs_builder.import_args_from_json(parser=parser, json_filename=args.json) # Export JSON Template (Optional) -------------------------------------------------------------- if args.json_template: - rs_builder.export_json_template(parser=parser, dep_dict=dep_dict) + rs_builder.export_json_template(parser=parser, dep_dict=dep_dict , summary=summary) + rs_builder.import_ip_details_json(json_filename=args.json, build_dir=args.build_dir ,details=details) # Create Wrapper ------------------------------------------------------------------------------- platform = OSFPGAPlatform(io=[], toolchain="raptor", device="gemini") diff --git a/rapidsilicon/ip/pll/v1_0/litex_wrapper/pll_litex_wrapper.py b/rapidsilicon/ip/pll/v1_0/litex_wrapper/pll_litex_wrapper.py index 0b6a79b8..c4984a63 100644 --- a/rapidsilicon/ip/pll/v1_0/litex_wrapper/pll_litex_wrapper.py +++ b/rapidsilicon/ip/pll/v1_0/litex_wrapper/pll_litex_wrapper.py @@ -38,7 +38,7 @@ def colorer(s, color="bright"): # PLL Wrapper ------------------------------------------------------------------------------------ class PLL(Module): - def __init__(self, platform, divide_clk_in_by_2, pll_mult, pll_div, clk_out0_div, clk_out1_div, clk_out2_div, clk_out3_div, **kwargs): + def __init__(self, platform, divided_clks, divide_clk_in_by_2, fast_clk_freq, ref_clk_freq, clk_out0_div, clk_out1_div, clk_out2_div, clk_out3_div, **kwargs): self.logger = logging.getLogger("PLL") self.logger.propagate = True @@ -51,8 +51,8 @@ def __init__(self, platform, divide_clk_in_by_2, pll_mult, pll_div, clk_out0_div self.logger.info(f"=================== PARAMETERS ====================") self.logger.info(f"DIVIDE_CLK_IN_BY_2 : {divide_clk_in_by_2}") - self.logger.info(f"PLL_MULT : {pll_mult}") - self.logger.info(f"PLL_DIV : {pll_div}") +# self.logger.info(f"PLL_MULT : {pll_mult}") +# self.logger.info(f"PLL_DIV : {pll_div}") self.logger.info(f"CLK_OUT0_DIV : {clk_out0_div}") self.logger.info(f"CLK_OUT1_DIV : {clk_out1_div}") self.logger.info(f"CLK_OUT2_DIV : {clk_out2_div}") @@ -73,32 +73,34 @@ def __init__(self, platform, divide_clk_in_by_2, pll_mult, pll_div, clk_out0_div self.GEARBOX_FAST_CLK = Signal() self.LOCK = Signal() - self.specials += Instance("PLL", - **kwargs, - - p_DIVIDE_CLK_IN_BY_2 = Instance.PreformattedParam(divide_clk_in_by_2), - p_PLL_MULT = Instance.PreformattedParam(pll_mult), - p_PLL_DIV = Instance.PreformattedParam(pll_div), - p_CLK_OUT0_DIV = Instance.PreformattedParam(clk_out0_div), - p_CLK_OUT1_DIV = Instance.PreformattedParam(clk_out1_div), - p_CLK_OUT2_DIV = Instance.PreformattedParam(clk_out2_div), - p_CLK_OUT3_DIV = Instance.PreformattedParam(clk_out3_div), - - i_PLL_EN = self.PLL_EN, - i_CLK_IN = self.CLK_IN, - i_CLK_OUT0_EN = self.CLK_OUT0_EN, - i_CLK_OUT1_EN = self.CLK_OUT1_EN, - i_CLK_OUT2_EN = self.CLK_OUT2_EN, - i_CLK_OUT3_EN = self.CLK_OUT3_EN, - o_CLK_OUT0 = self.CLK_OUT0, - o_CLK_OUT1 = self.CLK_OUT1, - o_CLK_OUT2 = self.CLK_OUT2, - o_CLK_OUT3 = self.CLK_OUT3, - o_GEARBOX_FAST_CLK = self.GEARBOX_FAST_CLK, - o_LOCK = self.LOCK - ) - - self.add_sources(platform) + if divided_clks == 3: + self.specials += Instance("PLL", + **kwargs, + + p_DIVIDED_CLKS = Instance.PreformattedParam(divided_clks), + P_DIVIDE_CLK_IN_BY_2 = Instance.PreformattedParam(divide_clk_in_by_2), + p_FAST_CLK_FREQ = Instance.PreformattedParam(fast_clk_freq), + p_REF_CLK_FREQ = Instance.PreformattedParam(ref_clk_freq), + p_CLK_OUT0_DIV = Instance.PreformattedParam(clk_out0_div), + p_CLK_OUT1_DIV = Instance.PreformattedParam(clk_out1_div), + p_CLK_OUT2_DIV = Instance.PreformattedParam(clk_out2_div), + p_CLK_OUT3_DIV = Instance.PreformattedParam(clk_out3_div), + + i_PLL_EN = 1, + i_CLK_IN = self.CLK_IN, + i_CLK_OUT0_EN = self.CLK_OUT0_EN, + i_CLK_OUT1_EN = 0, + i_CLK_OUT2_EN = 0, + i_CLK_OUT3_EN = 0, + o_CLK_OUT0 = self.CLK_OUT0, + o_CLK_OUT1 = self.CLK_OUT1, + o_CLK_OUT2 = self.CLK_OUT2, + o_CLK_OUT3 = self.CLK_OUT3, + o_GEARBOX_FAST_CLK = self.GEARBOX_FAST_CLK, + o_LOCK = self.LOCK + ) + + self.add_sources(platform) @staticmethod def add_sources(platform): diff --git a/rapidsilicon/lib/common.py b/rapidsilicon/lib/common.py index c3f6cad7..4d91ca8b 100644 --- a/rapidsilicon/lib/common.py +++ b/rapidsilicon/lib/common.py @@ -41,7 +41,7 @@ def add_wrapper_header(self, filename): # JSON template for GUI parsing - def export_json_template(self, parser, dep_dict): + def export_json_template(self, parser, dep_dict, summary): # Get "core_fix_param_group" group. core_fix_param_group = None @@ -171,6 +171,11 @@ def export_json_template(self, parser, dep_dict): param_json["parameters"][i].update(disable = dep_dict[param_json["parameters"][i]['parameter']]) + #Append summary in JSON + summary_temp = {"Summary": summary} + param_json.update(summary_temp) + + # Append Build and Json params to final json for i in range(len(build_param_list)): @@ -186,7 +191,13 @@ def import_args_from_json(self, parser, json_filename): t_args.__dict__.update(json.load(f)) args = parser.parse_args(namespace=t_args) return args - + + def import_ip_details_json(self, build_dir,details, build_name, version ): + self.build_name = build_name + self.build_path = os.path.join(build_dir, "rapidsilicon", "ip", self.ip_name, version, build_name) + new_json_filename = os.path.join(self.build_path, "details.json") + with open(new_json_filename, "w") as f: + json.dump(details, f, indent=4, default=None,) def prepare(self, build_dir, build_name, version): @@ -296,7 +307,7 @@ def generate_tcl(self): def generate_wrapper(self, platform, module): assert self.prepared - build_path = self.build_path + "build_dir" + build_path = "litex_build" build_filename = os.path.join(build_path, self.build_name) + ".v" # Build LiteX module.