Update on_chip_memory_litex_wrapper.py #1467
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| name: IP_Catalog Workflow | |
| on: | |
| push: | |
| pull_request: | |
| jobs: | |
| IP_Catalog_Ubuntu: | |
| runs-on: ubuntu-20.04 | |
| steps: | |
| - name: Cancel previous | |
| uses: styfle/[email protected] | |
| with: | |
| access_token: ${{ github.token }} | |
| - name: ssh-agent | |
| uses: webfactory/[email protected] | |
| with: | |
| ssh-private-key: | | |
| ${{ secrets.SSH_PRIVATE_KEY_RAPTOR_TOOLS }} | |
| - name: Checkout code | |
| uses: actions/checkout@v2 | |
| with: | |
| fetch-depth: 0 | |
| - name: Clone Raptor_Tools | |
| run: | | |
| git config --global --add safe.directory $GITHUB_WORKSPACE | |
| git submodule update --init Raptor_Tools | |
| - name: Install dependencies | |
| run: | |
| bash .github/install_ubuntu_dependencies_build.sh | |
| - name: Show shell configuration | |
| run: | | |
| env | |
| which cmake && cmake --version | |
| which make && make --version | |
| #which python3 && python3 --version | |
| #pipenv --version | |
| - name: Create Virtual ENV | |
| shell: bash | |
| run: | | |
| cd Raptor_Tools/python_tools | |
| make build && cd build && make | |
| - name: Sanity Check | |
| shell: bash | |
| run: | | |
| gen_list=`find $GITHUB_WORKSPACE/rapidsilicon/ip -type f -iname "*_gen.py"` | |
| cd Raptor_Tools/python_tools/build/share/envs/litex/bin | |
| for n in $gen_list | |
| do | |
| ./python3 $n --build --json-template | |
| ip_name=$(basename "${n%_gen.py}") | |
| echo $ip_name | |
| find /home/runner/work/IP_Catalog/IP_Catalog/Raptor_Tools/python_tools/build/share/envs/litex/bin -type f -name $ip_name"_wrapper.v" | |
| echo "IP generated RTL generated" | |
| done | |
| - name: Test IP Generation | |
| run: | | |
| cd Raptor_Tools/python_tools/build/share/envs/litex/bin | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_dpram/v1_0/axi_dpram_gen.py --data_width=32 --addr_width=8 --build-name=dpram_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_ram/v1_0/axi_ram_gen.py --data_width=32 --addr_width=8 --build-name=ram_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_register/v1_0/axi_register_gen.py --data_width=64 --addr_width=32 --build-name=register_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axil_gpio/v1_0/axil_gpio_gen.py --data_width=32 --addr_width=8 --build-name=gpio_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axil_uart16550/v1_0/axil_uart16550_gen.py --addr_width=8 --data_width=32 --build-name=uart_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_cdma/v1_0/axi_cdma_gen.py --addr_width=8 --data_width=32 --build-name=cdma --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_cdma/v2_0/axi_cdma_gen.py --axi_data_width=32 --axi_addr_width=32 --build-name=cdma --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_dma/v1_0/axi_dma_gen.py --axi_data_width=32 --axi_addr_width=8 --build-name=dma --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_fifo/v1_0/axi_fifo_gen.py --data_width=32 --addr_width=64 --build-name=fifo --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axis_adapter/v1_0/axis_adapter_gen.py --s_data_width=32 --build-name=adapter --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axis_fifo/v1_0/axis_fifo_gen.py --depth=2048 --data_width=32 --build-name=fifo --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axis_pipeline_register/v1_0/axis_pipeline_register_gen.py --data_width=32 --build-name=reg --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axis_uart/v1_0/axis_uart_gen.py --data_width=8 --build-name=uart --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/i2c_master/v1_0/i2c_master_gen.py --build-name=i2c --build-dir=./test_dir --write_fifo=1 --write_addr_width=5 --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/i2c_slave/v1_0/i2c_slave_gen.py --data_width=32 --build-name=wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/priority_encoder/v1_0/priority_encoder_gen.py --width=7 --build-name=encoder --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/vexriscv_cpu/v1_0/vexriscv_cpu_gen.py --build-name=vexriscv_wrap --build-dir=./ --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axis_width_converter/v1_0/axis_width_converter_gen.py --core_in_width=1024 --core_out_width=32 --build-name=width_converter --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_interconnect/v1_0/axi_interconnect_gen.py --data_width=32 --addr_width=64 --s_count=7 --m_count=4 --build-name=interconnect_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axil_interconnect/v1_0/axil_interconnect_gen.py --data_width=32 --addr_width=64 --s_count=5 --m_count=2 --build-name=interconnect_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axil_crossbar/v1_0/axil_crossbar_gen.py --data_width=32 --addr_width=64 --s_count=5 --m_count=6 --build-name=crossbar_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_crossbar/v1_0/axi_crossbar_gen.py --data_width=32 --addr_width=32 --s_count=7 --m_count=4 --build-name=crossbar_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axis_broadcast/v1_0/axis_broadcast_gen.py --data_width=1024 --m_count=8 --build-name=broadcast --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi2axilite_bridge/v1_0/axi2axilite_bridge_gen.py --data_width=256 --addr_width=8 --build-name=wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axil_quadspi/v1_0/axil_quadspi_gen.py --build-name=wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axil_ocla/v1_0/axil_ocla_gen.py --build-name=axil_ocla_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_async_fifo/v1_0/axi_async_fifo_gen.py --data_width=32 --fifo_depth=64 --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axis_async_fifo/v1_0/axis_async_fifo_gen.py --data_width=32 --depth=64 --build | |
| #--------------------------CentOS------------------------------------ | |
| centos7-gcc: | |
| name: IP_Catalog_centos | |
| runs-on: ubuntu-latest | |
| container: | |
| image: centos:7 | |
| defaults: | |
| run: | |
| shell: bash | |
| steps: | |
| - name: Cancel previous | |
| uses: styfle/[email protected] | |
| with: | |
| access_token: ${{ github.token }} | |
| - name: Install latest Git | |
| run: | | |
| yum install -y openssh-server openssh-clients | |
| yum remove -y git* | |
| yum install -y https://packages.endpointdev.com/rhel/7/os/x86_64/endpoint-repo.x86_64.rpm | |
| yum install -y git | |
| - name: ssh-agent | |
| uses: webfactory/[email protected] | |
| with: | |
| ssh-private-key: | | |
| ${{ secrets.SSH_PRIVATE_KEY_RAPTOR_TOOLS }} | |
| - name: Checkout code | |
| uses: actions/checkout@v2 | |
| with: | |
| fetch-depth: 0 | |
| - name: Clone Raptor_Tools | |
| run: | | |
| git config --global --add safe.directory $GITHUB_WORKSPACE | |
| git submodule update --init Raptor_Tools | |
| - name: Install GCC & CMake | |
| run: | |
| bash .github/install_centos_dependencies_build.sh | |
| - name: Show shell configuration | |
| run: | | |
| export LC_ALL=en_US.utf-8 | |
| export LANG=en_US.utf-8 | |
| which cmake && cmake --version | |
| which make && make --version | |
| #which python3 && python3 --version | |
| #pipenv --version | |
| - name: Create Virtual ENV | |
| shell: bash | |
| run: | | |
| export LC_ALL=en_US.utf-8 | |
| export LANG=en_US.utf-8 | |
| cd Raptor_Tools/python_tools | |
| make build && cd build && make | |
| - name: Sanity Check | |
| shell: bash | |
| run: | | |
| gen_list=`find $GITHUB_WORKSPACE/rapidsilicon/ip -type f -iname "*_gen.py"` | |
| cd Raptor_Tools/python_tools/build/share/envs/litex/bin | |
| for n in $gen_list | |
| do | |
| ./python3 $n --build --json-template | |
| done | |
| - name: Test IP Generation | |
| run: | | |
| export LC_ALL=en_US.utf-8 | |
| export LANG=en_US.utf-8 | |
| cd Raptor_Tools/python_tools/build/share/envs/litex/bin | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_dpram/v1_0/axi_dpram_gen.py --data_width=32 --addr_width=8 --json-template --build-name=dpram_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_ram/v1_0/axi_ram_gen.py --data_width=32 --addr_width=8 --json-template --build-name=ram_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_register/v1_0/axi_register_gen.py --data_width=64 --addr_width=32 --json-template --build-name=register_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axil_gpio/v1_0/axil_gpio_gen.py --data_width=32 --addr_width=8 --json-template --build-name=gpio_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axil_uart16550/v1_0/axil_uart16550_gen.py --addr_width=8 --data_width=32 --json-template --build-name=uart_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_cdma/v1_0/axi_cdma_gen.py --addr_width=8 --data_width=32 --json-template --build-name=cdma --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_cdma/v2_0/axi_cdma_gen.py --axi_data_width=32 --axi_addr_width=32 --json-template --build-name=cdma --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_dma/v1_0/axi_dma_gen.py --axi_data_width=32 --axi_addr_width=8 --json-template --build-name=dma --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_fifo/v1_0/axi_fifo_gen.py --data_width=32 --addr_width=64 --json-template --build-name=fifo --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axis_adapter/v1_0/axis_adapter_gen.py --s_data_width=32 --json-template --build-name=adapter --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axis_fifo/v1_0/axis_fifo_gen.py --depth=2048 --data_width=32 --json-template --build-name=fifo --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axis_pipeline_register/v1_0/axis_pipeline_register_gen.py --data_width=32 --json-template --build-name=reg --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axis_uart/v1_0/axis_uart_gen.py --data_width=8 --json-template --build-name=uart --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/i2c_master/v1_0/i2c_master_gen.py --json-template --build-name=i2c --build-dir=./test_dir --write_fifo=1 --write_addr_width=5 --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/i2c_slave/v1_0/i2c_slave_gen.py --data_width=32 --json-template --build-name=wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/priority_encoder/v1_0/priority_encoder_gen.py --width=7 --json-template --build-name=encoder --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/vexriscv_cpu/v1_0/vexriscv_cpu_gen.py --json-template --build-name=vexriscv_wrap --build-dir=./ --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axis_width_converter/v1_0/axis_width_converter_gen.py --core_in_width=1024 --core_out_width=32 --json-template --build-name=width_converter --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_interconnect/v1_0/axi_interconnect_gen.py --data_width=32 --addr_width=64 --s_count=7 --m_count=4 --json-template --build-name=interconnect_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axil_interconnect/v1_0/axil_interconnect_gen.py --data_width=32 --addr_width=64 --s_count=5 --m_count=2 --json-template --build-name=interconnect_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axil_crossbar/v1_0/axil_crossbar_gen.py --data_width=32 --addr_width=64 --s_count=5 --m_count=6 --json-template --build-name=crossbar_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_crossbar/v1_0/axi_crossbar_gen.py --data_width=32 --addr_width=32 --s_count=7 --m_count=4 --json-template --build-name=crossbar_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axis_broadcast/v1_0/axis_broadcast_gen.py --data_width=1024 --m_count=8 --json-template --build-name=broadcast --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi2axilite_bridge/v1_0/axi2axilite_bridge_gen.py --data_width=256 --addr_width=8 --json-template --build-name=wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axil_quadspi/v1_0/axil_quadspi_gen.py --json-template --build-name=wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axil_ocla/v1_0/axil_ocla_gen.py --build-name=axil_ocla_wrapper --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axi_async_fifo/v1_0/axi_async_fifo_gen.py --data_width=32 --fifo_depth=64 --build | |
| ./python3 $GITHUB_WORKSPACE/rapidsilicon/ip/axis_async_fifo/v1_0/axis_async_fifo_gen.py --data_width=32 --depth=64 --build |