The QMTECH board has a 50MHz crystal clock, whereas Genesys-2 has 200MHz

[jrrk2]

No description provided.

[hansfbaier]

I used the 60MHz ULPI clock as input for the example file.
I didn't really know how I would deal with a differential clock at that point in time.

[unbtorsten]

In general, you could set it up like this

module top (
  input clkin,
  input clkinb,
  output [7:0] led
);

  wire clk;
  IBUFDS ibuf_i(.I(clkin), .IB(clkinb), .O(clk));

  reg [28:0] ctr;

  always @(posedge clk) begin
    ctr <= ctr + 1'b1;
  end

  assign led = ctr[28:22];
endmodule

With constraints

set_property IOSTANDARD LVDS [get_ports {clkin}]
set_property IOSTANDARD LVDS [get_ports {clkinb}]
set_property PACKAGE_PIN AD12 [get_ports {clkin}]
set_property PACKAGE_PIN AD11 [get_ports {clkinb}]

Technically, one should be using IBUFGDS instead of IBUFDS, but nextpnr does not seem to like that at this time.

[jrrk2]

This is moot at the moment because none of the signals in bank 14 on the Genesys2 connect to a steady clock source. Possibly JTAG_CLK could be used from the external USB to JTAG converter.

[hansfbaier]

This should be fixed now, I committed a working example for the STLV7325 board, and would leave the adaptation and test for the Kintex board to you.