skiboot 5.7.0-rc2

skiboot-5.7-rc2

skiboot v5.7-rc2 was released on Thursday July 13th 2017. It is the
second release candidate of skiboot 5.7, which will become the new
stable release of skiboot following the 5.6 release, first released 24th
May 2017.

skiboot v5.7-rc2 contains all bug fixes as of skiboot-5.4.6 and
skiboot-5.1.19 (the currently maintained stable releases). We do not
currently expect to do any 5.6.x stable releases.

For how the skiboot stable releases work, see stable-rules for details.

The current plan is to cut the final 5.7 in the next week or so, with
skiboot 5.7 being for all POWER8 and POWER9 platforms in op-build v1.18
(due July 12th, but will come after skiboot 5.7).

This is the second release using the new regular six week release cycle,
similar to op-build, but slightly offset to allow for a short
stabilisation period. Expected release dates and contents are tracked
using GitHub milestone and issues:
https://github.com/open-power/skiboot/milestones

Over skiboot-5.7-rc1, we have the following changes:

POWER9

There are many important changes for POWER9 DD1 and DD2 systems. POWER9
support should be considered in development and skiboot 5.7 is certainly
NOT suitable for POWER9 production environments.

• HDAT: Add IPMI sensor data under /bmc node

• numa/associativity: Add a new level of NUMA for GPU's

  Today we have an issue where the NUMA nodes corresponding to GPU's
  have the same affinity/distance as normal memory nodes. Our
  reference-points today supports two levels [0x4, 0x4] for normal
  systems and [0x4, 0x3] for Power8E systems. This patch adds a new
  level [0x4, X, 0x2] and uses node-id as at all levels for the GPU.

• xive: Enable memory backing of queues

  This dedicates 6x64k pages of memory permanently for the XIVE to use
  for internal queue overflow. This allows the XIVE to deal with some
  corner cases where the internal queues might prove insufficient.

• xive: Properly get rid of donated indirect pages during reset

  Otherwise they keep being used accross kexec causing memory
  corruption in subsequent kernels once KVM has been used.

• cpu: Better handle unknown flags in opal_reinit_cpus()

  At the moment, if we get passed flags we don't know about, we return
  OPAL_UNSUPPORTED but we still perform whatever actions was requied
  by the flags we do support. Additionally, on P8, we attempt a SLW
  re-init which hasn't been supported since Murano DD2.0 and will
  crash your system.

  It's too late to fix on existing systems so Linux will have to be
  careful at least on P8, but to avoid future issues let's clean that
  up, make sure we only use slw_reinit() when HILE isn't supported.

• cpu: Unconditionally cleanup TLBs on P9 in opal_reinit_cpus()

  This can work around problems where Linux fails to properly cleanup
  part or all of the TLB on kexec.

• Fix scom addresses for power9 nx checkstop hmi handling.

  Scom addresses for NX status, DMA & ENGINE FIR and PBI FIR has
  changed for Power9. Fixup thoes while handling nx checkstop for
  Power9.

• Fix scom addresses for power9 core checkstop hmi handling.

  Scom addresses for CORE FIR (Fault Isolation Register) and
  Malfunction Alert Register has changed for Power9. Fixup those while
  handling core checkstop for Power9.

  Without this change HMI handler fails to check for correct reason
  for core checkstop on Power9.

• core/mem_region: check return value of add_region

  The only sensible thing to do if this fails is to abort() as we've
  likely just failed reserving reserved memory regions, and nothing
  good comes from that.

PHB4

• phb4: Do more retries on link training failures Currently we only
  retry once when we have a link training failure. This changes this
  to be 3 retries as 1 retry is not giving us enough reliablity.

  This will increase the boot time, especially on systems where we
  incorrectly detect a link presence when there really is nothing
  present. I'll post a followup patch to optimise our timings to help
  mitigate this later.

• phb4: Workaround phy lockup by doing full PHB reset on retry

  For PHB4 it's possible that the phy may end up in a bad state where
  it can no longer recieve data. This can manifest as the link not
  retraining. A simple PERST will not clear this. The PHB must be
  completely reset.

  This changes the retry state to CRESET to do this.

  This issue may also manifest itself as the link training in a
  degraded state (lower speed or narrower width). This patch doesn't
  attempt to fix that (will come later).

• pci: Add ability to trace timing

  PCI link training is responsible for a huge chunk of the skiboot
  boot time, so add the ability to trace it waiting in the main state
  machine.

• pci: Print resetting PHB notice at higher log level

  Currently during boot there a long delay while we wait for the PHBs
  to be reset and train. During this time, there is no output from
  skiboot and the last message doesn't give an indication of what's
  happening.

  This boosts the PHB reset message from info to notice so users can
  see what's happening during this long period of waiting.

• phb4: Only set one bit in nfir

  The MPIPL procedure says to only set bit 26 when forcing the PEC
  into freeze mode. Currently we set bits 24-27.

  This changes the code to follow spec and only set bit 26.

• phb4: Fix order of pfir/nfir clearing in CRESET

  According to the workbook, pfir must be cleared before the nfir. The
  way we have it now causes the nfir to not clear properly in some
  error circumstances.

  This swaps the order to match the workbook.

• phb4: Remove incorrect state transition

  When waiting in PHB4_SLOT_CRESET_WAIT_CQ for transations to end,
  we incorrectly move onto the next state. Generally we don't hit this
  as the transactions have ended already anyway.

  This removes the incorrect state transition.

• phb4: Set default lane equalisation

  Set default lane equalisation if there is nothing in the
  device-tree.

  Default value taken from hdat and confirmed by hardware team.
  Neatens the code up a bit too.

• hdata: Fix phb4 lane-eq property generation

  The lane-eq data we get from hdat is all 7s but what we end up in
  the device tree is: :

  xscom@603fc00000000/pbcq@4010c00/stack@0/ibm,lane-eq
                   00000000 31c339e0 00000000 0000000c
                   00000000 00000000 00000000 00000000
                   00000000 31c30000 77777777 77777777
                   77777777 77777777 77777777 77777777
  

  This fixes grabbing the properties from hdat and fixes the call to
  put them in the device tree.

• phb4: Fix PHB4 fence recovery.

  We had a few problems:

  • We used the wrong register to trigger the reset (spec bug)

  • We should clear the PFIR and NFIR while the reset is asserted

  • ... and in the right order !

  • We should only apply the DD1 workaround after the reset has been
    lifted.

  • We should ensure we use ASB whenever we are fenced or doing a
    CRESET

  • Make config ops write with ASB

• phb4: Verbose EEH options

  Enabled via nvram pci-eeh-verbose=true. ie. :

  nvram -p ibm,skiboot --update-config pci-eeh-verbose=true
  

• phb4: Print more info when PHB fences

  For now at PHBERR level. We don't have room in the diags data passed
  to Linux for these unfortunately.

Testing/development

• lpc: remove double LPC prefix from messages
• opal-ci/fetch-debian-jessie-installer: follow redirects Fixes some
  CI failures
• test/qemu-jessie: bail out fast on kernel panic
• test/qemu-jessie: dump boot log on failure
• travis: add fedora26
• xz: add fallthrough annotations to silence GCC7 warning

skiboot 5.7-rc1

skiboot v5.7-rc1 was released on Monday July 3rd 2017. It is the first
release candidate of skiboot 5.7, which will become the new stable release
of skiboot following the 5.6 release, first released 24th May 2017.

skiboot v5.7-rc1 contains all bug fixes as of :ref:skiboot-5.4.6
and :ref:skiboot-5.1.19 (the currently maintained stable releases). We
do not currently expect to do any 5.6.x stable releases.

For how the skiboot stable releases work, see :ref:stable-rules for details.

The current plan is to cut the final 5.7 by July 12th, with skiboot 5.7
being for all POWER8 and POWER9 platforms in op-build v1.18 (Due July 12th).
This is a short cycle as this release is mainly targetted towards POWER9
bringup efforts.

This is the second release using the new regular six week release cycle,
similar to op-build, but slightly offset to allow for a short stabilisation
period. Expected release dates and contents are tracked using GitHub milestone
and issues: https://github.com/open-power/skiboot/milestones

Over skiboot-5.6, we have the following changes:

New Features

New features in this release for POWER9 systems:

• In Memory Counters (IMC) (See :ref:imc for details)
• phb4: Activate shared PCI slot on witherspoon (see :ref:Shared Slot <shared-slot-rn>)
• phb4 capi (i.e. CAPI2): Enable capi mode for PHB4 (see :ref:CAPI on PHB4 <capi2-rn>)

New feature for IBM FSP based systems:

• fsp/tpo: Provide support for disabling TPO alarm

  This patch adds support for disabling a preconfigured
  Timed-Power-On(TPO) alarm on FSP based systems. Presently once a TPO alarm
  is configured from the kernel it will be triggered even if its
  subsequently disabled.

  With this patch a TPO alarm can be disabled by passing
  y_m_d==hr_min==0 to fsp_opal_tpo_write(). A branch is added to the
  function to handle this case by sending FSP_CMD_TPO_DISABLE message to
  the FSP instead of usual FSP_CMD_TPO_WRITE message. The kernel is
  expected to call opal_tpo_write() with y_m_d==hr_min==0 to request
  opal to disable TPO alarm.

POWER9

Development on POWER9 systems continues in earnest.

This release includes the first support for POWER9 DD2 chips. Future releases
will likely contain more bug fixes, this release has booted on real hardware.

• hdata: Reserve Trace Areas

  When hostboot is configured to setup in memory tracing it will reserve
  some memory for use by the hardware tracing facility. We need to mark
  these areas as off limits to the operating system and firmware.

• hdata: Make out-of-range idata print at PR_DEBUG

  Some fields just aren't populated on some systems.

• hdata: Ignore unnamed memory reservations.

  Hostboot should name any and all memory reservations that it provides.
  Currently some hostboots export a broken reservation covering the first
  256MB of memory and this causes the system to crash at boot due to an
  invalid free because this overlaps with the static "ibm,os-reserve"
  region (which covers the first 768MB of memory).

  According to the hostboot team unnamed reservations are invalid and can
  be ignored.

• hdata: Check the Host I2C devices array version

  Currently this is not populated on FSP machines which causes some
  obnoxious errors to appear in the boot log. We also only want to
  parse version 1 of this structure since future versions will completely
  change the array item format.

• Ensure P9 DD1 workarounds apply only to Nimbus

  The workarounds for P9 DD1 are only needed for Nimbus. P9 Cumulus will
  be DD1 but don't need these same workarounds.

  This patch ensures the P9 DD1 workarounds only apply to Nimbus. It
  also renames some things to make clear what's what.

• cpu: Cleanup AMR and IAMR when re-initializing CPUs

  There's a bug in current Linux kernels leaving crap in those registers
  accross kexec and not sanitizing them on boot. This breaks kexec under
  some circumstances (such as booting a hash kernel from a radix one
  on P9 DD2.0).

  The long term fix is in Linux, but this workaround is a reasonable
  way of "sanitizing" those SPRs when Linux calls opal_reinit_cpus()
  and shouldn't have adverse effects.

  We could also use that same mechanism to cleanup other things as
  well such as restoring some other SPRs to their default value in
  the future.

• Set POWER9 RPR SPR to 0x00000103070F1F3F. Same value as P8.

  Without this, thread priorities inside a core don't work.

• cpu: Support setting HID[RADIX] and set it by default on P9

  This adds new opal_reinit_cpus() flags to setup radix or hash
  mode in HID[8] on POWER9.

  By default HID[8] will be set. On P9 DD1.0, Linux will change
  it as needed. On P9 DD2.0 hash works in radix mode (radix is
  really "dual" mode) so KVM won't break and existing kernels
  will work.

  Newer kernels built for hash will call this to clear the HID bit
  and thus get the full size of the TLB as an optimization.

• Add "cleanup_global_tlb" for P9 and later

  Uses broadcast TLBIE's to cleanup the TLB on all cores and on
  the nest MMU

• xive: DD2.0 updates

  Add support for StoreEOI, fix StoreEOI MMIO offset in ESB page,
  and other cleanups

• Update default TSCR value for P9 as recommended by HW folk.

• xive: Fix initialisation of xive_cpu_state struct

  When using XIVE emulation with DEBUG=1, we run into crashes in log_add()
  due to the xive_cpu_state->log_pos being uninitialised (and thus, with
  DEBUG enabled, initialised to the poison value of 0x99999999).

OCC/Power Management
^^^^^^^^^^^^^^^^^^^^

With this release, it's possible to boot POWER9 systems with the OCC
enabled and change CPU frequencies. Doing so does require other firmware
components to also support this (otherwise the frequency will not be set).

• occ: Skip setting cores to nominal frequency in P9

  In P9, once OCC is up, it is supposed to setup the cores to nominal
  frequency. So skip this step in OPAL.

• occ: Fix Pstate ordering for P9

  In P9 the pstate values are positive. They are continuous set of
  unsigned integers [0 to +N] where Pmax is 0 and Pmin is N. The
  linear ordering of pstates for P9 has changed compared to P8.
  P8 has neagtive pstate values advertised as [0 to -N] where Pmax
  is 0 and Pmin is -N. This patch adds helper routines to abstract
  pstate comparison with pmax and adds sanity pstate limit checks.
  This patch also fixes pstate arithmetic by using labs().

• p8-i2c: occ: Add support for OCC to use I2C engines

  This patch adds support to share the I2C engines with host and OCC.
  OCC uses I2C engines to read DIMM temperatures and to communicate with
  GPU. OCC Flag register is used for locking between host and OCC. Host
  requests for the bus by setting a bit in OCC Flag register. OCC sends
  an interrupt to indicate the change in ownership.

opal-prd/PRD
^^^^^^^^^^^^

• opal-prd: Handle SBE passthrough message passing

  This patch adds support to send SBE pass through command to HBRT.

• SBE: Add passthrough command support

  SBE sends passthrough command. We have to capture this interrupt and
  send event to HBRT via opal-prd (user space daemon).

• opal-prd: hook up reset_pm_complex

  This change provides the facility to invoke HBRT's reset_pm_complex, in
  the same manner is done with process_occ_reset previously.

  We add a control command for opal-prd pm-complex reset, which is just
  an alias for occ_reset at this stage.

• prd: Implement firmware side of opaque PRD channel

  This change introduces the firmware side of the opaque HBRT <--> OPAL
  message channel. We define a base message format to be shared with HBRT
  (in include/prd-fw-msg.h), and allow firmware requests and responses to
  be sent over this channel.

  We don't currently have any notifications defined, so have nothing to do
  for firmware_notify() at this stage.

• opal-prd: Add firmware_request & firmware_notify implementations

  This change adds the implementation of firmware_request() and
  firmware_notify(). To do this, we need to add a message queue, so that
  we can properly handle out-of-order messages coming from firmware.

• opal-prd: Add support for variable-sized messages

  With the introductuion of the opaque firmware channel, we want to
  support variable-sized messages. Rather than expecting to read an
  entire 'struct opal_prd_msg' in one read() call, we can split this
  over mutiple reads, potentially expanding our message buffer.

• opal-prd: Sync hostboot interfaces with HBRT

  This change adds new callbacks defined for p9, and the base thunks for
  the added calls.

• opal-prd: interpret log level prefixes from HBRT

  Interpret the (optional) *_MRK log prefixes on HBRT messages, and set
  the syslog log priority to suit.

• opal-prd: Add occ reset to usage text

• opal-prd: allow different chips for occ control actions

  The occ reset and occ error actions can both take a chip id
  argument, but we're currently just using zero. This change changes the
  control message format to pass the chip ID from the control process to
  the opal-prd daemon.

PCI/PHB4
^^^^^^^^

• phb4: Fix number of index bits in IODA tables

  On PHB4 the number of index bits in the IODA table address register
  was bumped to 10 bits to accomodate for 1024 MSIs and 1024 TVEs (DD2).

  However our macro only defined the field to be 9 bits, thus causing
  "interesting" behaviours on some systems.

• phb4: Harden init with bad PHBs

  Currently if we read all 1's from the EEH or IRQ capabilities, we end
  up train wrecking on some other random code (eg. an assert() in xive).

  This hardens the PHB4 code to look for these bad reads and more
  gracefully fails the init for that PHB alone. This allows the rest of
  the system to boot and ignore those ba...

skiboot 5.4.6

skiboot-5.4.6 was released on Wednesday June 14th, 2017. It replaces
:ref:skiboot-5.4.5 as the current stable release in the 5.4.x series.

Over :ref:skiboot-5.4.5, we have a small number of bug fixes for
FSP based platforms:

• FSP/CONSOLE: Workaround for unresponsive ipmi daemon

  In some corner cases, where FSP is active but not responding to
  console MBOX message (due to buggy IPMI) and we have heavy console
  write happening from kernel, then eventually our console buffer
  becomes full. At this point OPAL starts sending OPAL_BUSY_EVENT to
  kernel. Kernel will keep on retrying. This is creating kernel soft
  lockups. In some extreme case when every CPU is trying to write to
  console, user will not be able to ssh and thinks system is hang.

  If we reset FSP or restart IPMI daemon on FSP, system recovers and
  everything becomes normal.

  This patch adds workaround to above issue by returning OPAL_HARDWARE
  when cosole is full. Side effect of this patch is, we may endup dropping
  latest console data. But better to drop console data than system hang.

  Alternative approach is to drop old data from console buffer, make space
  for new data. But in normal condition only FSP can update 'next_out'
  pointer and if we touch that pointer, it may introduce some other
  race conditions. Hence we decided to just new console write request.

• FSP: Set status field in response message for timed out message

  For timed out FSP messages, we set message status as "fsp_msg_timeout".
  But most FSP driver users (like surviellance) are ignoring this field.
  They always look for FSP returned status value in callback function
  (second byte in word1). So we endup treating timed out message as success
  response from FSP.

  Sample output: ::

    [69902.432509048,7] SURV: Sending the heartbeat command to FSP
    [70023.226860117,4] FSP: Response from FSP timed out, word0 = d66a00d7, word1 = 0 state: 3
    ....
    [70023.226901445,7] SURV: Received heartbeat acknowledge from FSP
    [70023.226903251,3] FSP: fsp_trigger_reset() entry

Here SURV code thought it got valid response from FSP. But actually we didn't
receive response from FSP.

• FSP: Improve timeout message

  Presently we print word0 and word1 in error log. word0 contains
  sequence number and command class. One has to understand word0
  format to identify command class.

  Lets explicitly print command class, sub command etc.

• FSP/RTC: Remove local fsp_in_reset variable

  Now that we are using fsp_in_rr() to detect FSP reset/reload, fsp_in_reset
  become redundant. Lets remove this local variable.

• FSP/RTC: Fix possible FSP R/R issue in rtc write path

  fsp_opal_rtc_write() checks FSP status before queueing message to FSP. But if
  FSP R/R starts before getting response to queued message then we will continue
  to return OPAL_BUSY_EVENT to host. In some extreme condition host may
  experience hang. Once FSP is back we will repost message, get response from FSP
  and return OPAL_SUCCESS to host.

  This patch caches new values and returns OPAL_SUCCESS if FSP R/R is happening.
  And once FSP is back we will send cached value to FSP.

• hw/fsp/rtc: read/write cached rtc tod on fsp hir.

  Currently fsp-rtc reads/writes the cached RTC TOD on an fsp
  reset. Use latest fsp_in_rr() function to properly read the cached rtc
  value when fsp reset initiated by the hir.

  Below is the kernel trace when we set hw clock, when hir process starts. ::

    [ 1727.775824] NMI watchdog: BUG: soft lockup - CPU#57 stuck for 23s! [hwclock:7688]
    [ 1727.775856] Modules linked in: vmx_crypto ibmpowernv ipmi_powernv uio_pdrv_genirq ipmi_devintf powernv_op_panel uio ipmi_msghandler powernv_rng leds_powernv ip_tables x_tables autofs4 ses enclosure scsi_transport_sas crc32c_vpmsum lpfc ipr tg3 scsi_transport_fc
    [ 1727.775883] CPU: 57 PID: 7688 Comm: hwclock Not tainted 4.10.0-14-generic #16-Ubuntu
    [ 1727.775883] task: c000000fdfdc8400 task.stack: c000000fdfef4000
    [ 1727.775884] NIP: c00000000090540c LR: c0000000000846f4 CTR: 000000003006dd70
    [ 1727.775885] REGS: c000000fdfef79a0 TRAP: 0901   Not tainted  (4.10.0-14-generic)
    [ 1727.775886] MSR: 9000000000009033 <SF,HV,EE,ME,IR,DR,RI,LE>
    [ 1727.775889]   CR: 28024442  XER: 20000000
    [ 1727.775890] CFAR: c00000000008472c SOFTE: 1
                   GPR00: 0000000030005128 c000000fdfef7c20 c00000000144c900 fffffffffffffff4
                   GPR04: 0000000028024442 c00000000090540c 9000000000009033 0000000000000000
                   GPR08: 0000000000000000 0000000031fc4000 c000000000084710 9000000000001003
                   GPR12: c0000000000846e8 c00000000fba0100
    [ 1727.775897] NIP [c00000000090540c] opal_set_rtc_time+0x4c/0xb0
    [ 1727.775899] LR [c0000000000846f4] opal_return+0xc/0x48
    [ 1727.775899] Call Trace:
    [ 1727.775900] [c000000fdfef7c20] [c00000000090540c] opal_set_rtc_time+0x4c/0xb0 (unreliable)
    [ 1727.775901] [c000000fdfef7c60] [c000000000900828] rtc_set_time+0xb8/0x1b0
    [ 1727.775903] [c000000fdfef7ca0] [c000000000902364] rtc_dev_ioctl+0x454/0x630
    [ 1727.775904] [c000000fdfef7d40] [c00000000035b1f4] do_vfs_ioctl+0xd4/0x8c0
    [ 1727.775906] [c000000fdfef7de0] [c00000000035bab4] SyS_ioctl+0xd4/0xf0
    [ 1727.775907] [c000000fdfef7e30] [c00000000000b184] system_call+0x38/0xe0
    [ 1727.775908] Instruction dump:
    [ 1727.775909] f821ffc1 39200000 7c832378 91210028 38a10020 39200000 38810028 f9210020
    [ 1727.775911] 4bfffe6d e8810020 80610028 4b77f61d <60000000> 7c7f1b78 3860000a 2fbffff4

This is found when executing the op-test-framework fspresetReload testcase <https://github.com/open-power/op-test-framework/blob/master/testcases/fspresetReload.py>_

With this fix ran fsp hir torture testcase in the above test
which is working fine.

• FSP/CHIPTOD: Return false in error path

skiboot 5.4.5

skiboot-5.4.5 was released on Friday June 9th, 2017. It replaces
skiboot-5.4.4 as the current stable release in the 5.4.x series.

Over skiboot-5.4.4, we have a small number of bug fixes:

• On FSP platforms: notify FSP of Platform Log ID after Host Initiated Reset Reload
  Trigging a Host Initiated Reset (when the host detects the FSP has gone
  out to lunch and should be rebooted), would cause "Unknown Command" messages
  to appear in the OPAL log.

  This patch implements those messages.

  Log showing unknown command:

    / # cat /sys/firmware/opal/msglog | grep -i ,3
    [  110.232114723,3] FSP: fsp_trigger_reset() entry
    [  188.431793837,3] FSP #0: Link down, starting R&R
    [  464.109239162,3] FSP #0: Got XUP with no pending message !
    [  466.340598554,3] FSP-DPO: Unknown command 0xce0900
    [  466.340600126,3] FSP: Unhandled message ce0900

• hw/i2c: Fix early lock drop

  When interacting with an I2C master the p8-i2c driver (common to p9)
  aquires a per-master lock which it holds for the duration of it's
  interaction with the master. Unfortunately, when
  p8_i2c_check_initial_status() detects that the master is busy with
  another transaction it drops the lock and returns OPAL_BUSY. This is
  contrary to the driver's locking strategy which requires that the
  caller aquire and drop the lock. This leads to a crash due to the
  double unlock(), which skiboot treats as fatal.

• head.S: store all of LR and CTR

  When saving the CTR and LR registers the skiboot exception handlers use the
  'stw' instruction which only saves the lower 32 bits of the register. Given
  these are both 64 bit registers this leads to some strange register dumps,
  for example: ::

    ***********************************************
    Unexpected exception 200 !
    SRR0 : 0000000030016968 SRR1 : 9000000000201000
    HSRR0: 0000000000000180 HSRR1: 9000000000001000
    LR   : 3003438830823f50 CTR  : 3003438800000018
    CFAR : 00000000300168fc
    CR   : 40004208  XER: 00000000

In this dump the upper 32 bits of LR and CTR are actually stack gunk
which obscures the underlying issue.

skiboot-5.6.0

skiboot-5.6.0 was released on Wednesday 24th May 2017. It is the new stable
release of skiboot, taking over from the 5.5 release, first released on
April 7th 2017. It is the first release done in a regular six week release
cycle, mirroring that of op-build.

skiboot-5.6.0 contains all bug fixes as of :ref:skiboot-5.4.4
and :ref:skiboot-5.1.19 (the currently maintained stable releases). We
do not currently expect to do any 5.5.x stable releases.

For how the skiboot stable releases work, see :ref:stable-rules for details.

This release is a good level set of POWER9 support for bringup activities.
If you are doing bringup, it is strongly suggested you continue to follow
skiboot master.

Changes in skiboot-5.6.0

See changes in the release candidates:

• :ref:skiboot-5.6.0-rc1
• :ref:skiboot-5.6.0-rc2

The final 5.6.0 release has no functional changes over the 5.6.0-rc2.

skiboot-5.6.0-rc2

skiboot-5.6.0-rc2 was released on Friday May 19th 2017. It is the second
release candidate of skiboot 5.6, which will become the new stable release
of skiboot following the 5.5 release, first released April 7th 2017.

skiboot-5.6.0-rc2 contains all bug fixes as of :ref:skiboot-5.4.4
and :ref:skiboot-5.1.19 (the currently maintained stable releases). We
do not currently expect to do any 5.5.x stable releases.

For how the skiboot stable releases work, see :ref:stable-rules for details.

The current plan is to cut the final 5.6.0 by May 22nd, with skiboot 5.6.0
being for all POWER8 and POWER9 platforms in op-build v1.17 (Due May 24th).
This is a short cycle as this release is mainly targetted towards POWER9
bringup efforts.

With skiboot 5.6.0, we are moving to a regular six week release cycle,
similar to op-build, but slightly offset to allow for a short stabilisation
period. Expected release dates and contents are tracked using GitHub milestone
and issues: https://github.com/open-power/skiboot/milestones

Over :ref:skiboot-5.6.0-rc1, we have the following changes:

• hw/i2c: Fix early lock drop

  When interacting with an I2C master the p8-i2c driver (common to p9)
  aquires a per-master lock which it holds for the duration of it's
  interaction with the master. Unfortunately, when
  p8_i2c_check_initial_status() detects that the master is busy with
  another transaction it drops the lock and returns OPAL_BUSY. This is
  contrary to the driver's locking strategy which requires that the
  caller aquire and drop the lock. This leads to a crash due to the
  double unlock(), which skiboot treats as fatal.

• mambo: Add skiboot/linux symbol lookup

  Adds the skisym and linsym commands which can be used to find the
  address of a Linux or Skiboot symbol. To function this requires
  the user to provide the SKIBOOT_MAP and VMLINUX_MAP environmental
  variables which indicate which skiboot.map and System.map files
  should be used.

  Examples:

  • Look up a symbol address: ::

        systemsim % skisym .load_and_boot_kernel
        0x0000000030013a08
    

  • Set a breakpoint there: ::

        systemsim % b [skisym .load_and_boot_kernel]
        breakpoint set at [0:0]: 0x0000000030013a08 (0x0000000030013A08) Enc:0x7D800026 : mfcr    r12
    

• libstb: Fix build in OpenSSL 1.1

  The build failure was as follows: ::

    [ HOSTCC ] libstb/create-container.c
    In file included from /usr/include/openssl/asn1.h:24:0,
                     from /usr/include/openssl/ec.h:30,
                     from libstb/create-container.c:36:
    libstb/create-container.c: In function ‘getSigRaw’:
    libstb/create-container.c:104:31: error: dereferencing pointer to incomplete
                                      type ‘ECDSA_SIG {aka struct ECDSA_SIG_st}’
      rlen = BN_num_bytes(signature->r);
                                   ^

skiboot-5.6.0-rc1

skiboot-5.6.0-rc1 was released on Tuesday May 16th 2017. It is the first
release candidate of skiboot 5.6, which will become the new stable release
of skiboot following the 5.5 release, first released April 7th 2017.

skiboot-5.6.0-rc1 contains all bug fixes as of :ref:skiboot-5.4.4
and :ref:skiboot-5.1.19 (the currently maintained stable releases). We
do not currently expect to do any 5.5.x stable releases.

For how the skiboot stable releases work, see :ref:stable-rules for details.

The current plan is to cut the final 5.6.0 by May 22nd, with skiboot 5.6.0
being for all POWER8 and POWER9 platforms in op-build v1.17 (Due May 24th).
This is a short cycle as this release is mainly targetted towards POWER9
bringup efforts.

This is the first release using the new regular six week release cycle,
similar to op-build, but slightly offset to allow for a short stabilisation
period. Expected release dates and contents are tracked using GitHub milestone
and issues: https://github.com/open-power/skiboot/milestones

Over skiboot-5.5, we have the following changes:

New Platforms

Thanks to SuperMicro for submitting support for the p9dsu platform, AKA Boston.

POWER9

XIVE:

• xive: Clear emulation mode queue on reset

• xive: Fixes/improvements to xive reset for multi-chip systems

• xive: Synchronize after disable IRQs in opal_xive_reset()

• xive: Workaround a problem with indirect TM access

• hdata: Make FSPv1 work again
  One less thing to work around for those crazy enough to try.

• xive: Log more information in opal_xive_dump() for emulation state

  Add a counter of total interrupts taken by a CPU, dump the
  queue buffer both before and after the current pointer,
  and also display the HW state of the queue descriptor and
  the PQ state of the IPI.

• xive: Add a per-cpu logging mechanism to XICS emulation

  This is a small 32-entries rolling buffer that logs a few
  operations. It's useful to debug odd problems. The output
  is printed when opal_xive_dump() is called.

• xive: Check queues for duplicates in DEBUG builds.

  There should never be duplicate interrupts in a queue.
  This adds code to check that when looking at the queue
  content. Since it can be a performance loss, this is only
  done for debug builds.

• xive+phb4: Fix exposing trigger page to Linux

HDAT Parsing:

• hdata/spira.c: Add device-tree bindings for nest mmu

• hdata/i2c: Workaround broken i2c devices

• hdata: indicate when booted with elevated risk level

  When the system is IPLed with an elevated risk level Hostboot will
  set a flag in the IPL parameters structure. Parse and export this
  in the device tree at: /ipl-params/sys-params/elevated-risk-level

• hdata: Respect OCC and HOMER resevations

  In the past we've ignored these since Hostboot insisted in exporting
  broken reservations and the OCC was not being used yet. This situation
  seems to have resolved itself so we should respect the reservations that
  hostboot provides.

I2C:

• i2c: Add interrupts support on P9

  Some older revisions of hostboot populate the host i2c device fields
  with all zero entires. Detect and ignore these so we don't crash on
  boot.

  Without this we get: ::

  [ 151.251240444,3] DT: dt_attach_root failed, duplicate unknown@0
  [ 151.251300274,3] ***********************************************
  [ 151.251339330,3] Unexpected exception 200 !
  [ 151.251363654,3] SRR0 : 0000000030090c28 SRR1 : 9000000000201000
  [ 151.251409207,3] HSRR0: 0000000000000010 HSRR1: 9000000000001000
  [ 151.251444114,3] LR : 30034018300c5ab0 CTR : 30034018300a343c
  [ 151.251478314,3] CFAR : 0000000030024804
  [ 151.251500346,3] CR : 40004208 XER: 00000000
  
  [ 151.252083372,0] Aborting!
  CPU 0034 Backtrace:
  S: 0000000031cd36a0 R: 000000003001364c .backtrace+0x2c
  S: 0000000031cd3730 R: 0000000030018db8 ._abort+0x4c
  S: 0000000031cd37b0 R: 0000000030025c6c .exception_entry+0x114
  S: 0000000031cd3840 R: 0000000000001f00 * +0x1f00
  S: 0000000031cd3a10 R: 0000000031cd3ab0 *
  S: 0000000031cd3aa0 R: 00000000300248b8 .new_property+0x90
  S: 0000000031cd3b30 R: 0000000030024b50 .__dt_add_property_cells+0x30
  S: 0000000031cd3bd0 R: 000000003009abec .parse_i2c_devs+0x350
  S: 0000000031cd3cf0 R: 0000000030093ffc .parse_hdat+0x11e4
  S: 0000000031cd3e30 R: 00000000300144c8 .main_cpu_entry+0x138
  S: 0000000031cd3f00 R: 0000000030002648 boot_entry+0x198

PHB4:

• phb4: Enforce root complex config space size of 2048

  The root complex config space size on PHB4 is 2048. This patch sets
  that size and enforces it when trying to read/write the config space
  in the root complex.

  Without this someone reading the config space via /sysfs in linux will
  cause an EEH on the PHB.

  If too high, reads returns 1s and writes are silently dropped.

• phb4: Add an option for disabling EEH MMIO in nvram

  Having the option to disable EEH for MMIO without rebuilding skiboot
  could be useful for testing, so check for pci-eeh-mmio=disabled in nvram.

  This is not designed to be a supported option or configuration, just
  an option that's useful in bringup and development of POWER9 systems.

• phb4: Fix slot presence detect

  This has the nice side effect of improving boot times since we no
  longer waste time tring to train links that don't have anything
  present.

• phb4: Enable EEH for MMIO

• phb4: Implement fence check

• phb4: Implement diag data

OCC:

• occ/irq: Fix SCOM address and irq reasons for P9 OCC

  This patch fixes the SCOM address for OCC_MISC register which is used
  for OCC interupts. In P9, OCC sends an interrupt to notify change in
  the shared memory like throttle status. This patch handles this
  interrupt reason.

PRD:

• prd: Fix PRD scoms for P9

NX/DARN:

• nx: Add POWER9 DARN support

NPU2:

• npu2: Do not attempt to initialise non DD1 hardware

  There are significant changes to hardware register addresses and
  meanings on newer chip revisions making them unlikely to work
  correctly with the existing code. Better to fail clearly and early.

• npu, npu2: Describe diag data size in device tree

Memory Reservation:

• mem_region: Add reserved regions after memory init

  When a new memory region is added (e.g for memory reserved by firmware)
  the list of existing memory regions is iterated through and a cut-out is
  made in any existing region that overlaps with the new one. Prior to the
  HDAT reservations being made the region init process was always:

  1. Create regions from the memory@ DT nodes. (mostly large)
  2. Create reserved regions from the device-tree. (mostly small)

  When adding new regions we have assumed that the new region will only
  every intersect with at most one existing region, which it will split.
  Adding reservations inside the HDAT parser breaks this because when
  adding the memory@ node regions we can potentially overlap with
  multiple reserved regions. This patch fixes this by maintaining a
  seperate list of memory reservations and delaying merging them until
  after the normal memory init has finished, similar to how DT
  reservations are handled.

PCI

• pci: Describe PHB diag data size in device tree

  Linux hardcodes the PHB diag data buffer at (as of this commit) 8192 bytes.
  This has been enough for P7IOC and PHB3, but the 512 PEs of PHB4 pushes
  the diag data blob over this size. Rather than just increasing the
  hardcoded size in Linux, provide the size of the diag data blob in the
  device tree so that the OS can dynamically allocate as much as it needs.
  This both enables more space for PHB4 and less wasted memory for P7IOC
  and PHB3.

  P7IOC communicates both hub and PHB data using this buffer, so when
  setting the size, use whichever struct is largest.

• hdata/i2c: Fix bus and clock frequencies

• ibm-fsp: use opal-prd on p9 and above

  Previously the PRD tooling ran on the FSP, but it was moved into
  userspace on the host for OpenPower systems. For P9 this system
  was adopted for FSP systems too.

I2C

• i2c: Remove old hack for bad clock frequency

  This hack dates back to ancient P8 hostboots. The value
  it would use if it detected the "bad" value was incorrect
  anyway.

• i2c: Log the engine clock frequency at boot

FSP Systems

These include the Apollo, Firenze and ZZ platforms.

• Remove multiple logging for un-handled fsp sub commands.

  If any new or unknown command need to be handled, just log
  un-hnadled message from only fsp, not required from fsp-dpo. ::

  cat /sys/firmware/opal/msglog | grep -i ,3
  [ 110.232114723,3] FSP: fsp_trigger_reset() entry
  [ 188.431793837,3] FSP #0: Link down, starting R&R
  [ 464.109239162,3] FSP #0: Got XUP with no pending message !
  [ 466.340598554,3] FSP-DPO: Unknown command 0xce0900
  [ 466.340600126,3] FSP: Unhandled message ce0900

• FSP: Notify FSP of Platform Log ID after Host Initiated Reset Reload

  Trigging a Host Initiated Reset (when the host detects the FSP has gone
  out to lunch and should be rebooted), would cause "Unknown Command" messages
  to appear in the OPAL log.

  This patch implements those messages

  How to trigger FSP RR(HIR): ::

  $ putmemproc 300000f8 0x00000000deadbeef
  s1 k0:n0:s0:p00
  ecmd_ppc putmemproc 300000f8 0x00000000deadbeef

  Log showing unknown command:
  / # cat /sys/firmware/opal/msglog | grep -i ,3
  [ 110.232114723,3] FSP: fsp_trigger_reset() entry
  [ 188.431793837,3] FSP #0: Link down, starting R...

skiboot-5.4.4

skiboot-5.4.4 was released on Wednesday May 3rd, 2017. It replaces
:ref:skiboot-5.4.3 as the current stable release in the 5.4.x series.

Over :ref:skiboot-5.4.3, we have a small number of bug fixes:

• hw/fsp: Do not queue SP and SPCN class messages during reset/reload
  In certain cases of communicating with the FSP (e.g. sensors), the OPAL FSP
  driver returns a default code (async
  completion) even though there is no known bound from the time of this error
  return to the actual data being available. The kernel driver keeps waiting
  leading to soft-lockup on the host side.

  Mitigate both these (known) cases by returning OPAL_BUSY so the host driver
  knows to retry later.

• core/pci: Fix PCIe slot's presence
  According to PCIe spec, the presence bit is hardcoded to 1 if PCIe
  switch downstream port doesn't support slot capability. The register
  used for the check in pcie_slot_get_presence_state() is wrong. It
  should be PCIe capability register instead of PCIe slot capability
  register. Otherwise, we always have present bit on the PCI topology.

  The issue is found on Supermicro's p8dtu2u machine: ::

  lspci -t

  -+-[0022:00]---00.0-[01-08]----00.0-[02-08]--+-01.0-[03]----00.0
  | -02.0-[04-08]--

  cat /sys/bus/pci/slots/S002204/adapter

  1

  lspci -vvs 0022:02:02.0

  lspci -vvs 0022:02:02.0

  0022:02:02.0 PCI bridge: PLX Technology, Inc. PEX 8718 16-Lane,
  5-Port PCI Express Gen 3 (8.0 GT/s) Switch (rev ab) (prog-if 00 [Normal decode])
  :
  Capabilities: [68] Express (v2) Downstream Port (Slot+), MSI 00
  :
  SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-
  Changed: MRL- PresDet- LinkState-

  This fixes the issue by checking the correct register (PCIe capability).
  Also, the register's value is cached in advance as we did for slot and
  link capability.

• core/pci: More reliable way to update PCI slot power state

  The power control bit (SLOT_CTL, offset: PCIe cap + 0x18) isn't
  reliable enough to reflect the PCI slot's power state. Instead,
  the power indication bits are more reliable comparatively. This
  leads to mismatch between the cached power state and PCI slot's
  presence state, resulting in the hotplug driver in kernel refuses
  to unplug the devices properly on the request. The issue was
  found on below NVMe card on "supermicro,p8dtu2u" machine. We don't
  have this issue on the integrated PLX 8718 switch. ::

  lspci

  0022:01:00.0 PCI bridge: PLX Technology, Inc. PEX 9733 33-lane,
  9-port PCI Express Gen 3 (8.0 GT/s) Switch (rev aa)
  0022:02:01.0 PCI bridge: PLX Technology, Inc. PEX 9733 33-lane,
  9-port PCI Express Gen 3 (8.0 GT/s) Switch (rev aa)
  0022:02:04.0 PCI bridge: PLX Technology, Inc. PEX 9733 33-lane,
  9-port PCI Express Gen 3 (8.0 GT/s) Switch (rev aa)
  0022:02:05.0 PCI bridge: PLX Technology, Inc. PEX 9733 33-lane,
  9-port PCI Express Gen 3 (8.0 GT/s) Switch (rev aa)
  0022:02:06.0 PCI bridge: PLX Technology, Inc. PEX 9733 33-lane,
  9-port PCI Express Gen 3 (8.0 GT/s) Switch (rev aa)
  0022:02:07.0 PCI bridge: PLX Technology, Inc. PEX 9733 33-lane,
  9-port PCI Express Gen 3 (8.0 GT/s) Switch (rev aa)
  0022:17:00.0 Non-Volatile memory controller: Device 19e5:0123 (rev 45)

  This updates the cached PCI slot's power state using the power
  indication bits instead of power control bit, to fix above issue.

• core/pci: Avoid hreset after freset

skiboot-5.5.0

skiboot-5.5.0 was released on Friday April 7th 2017. It is the new stable
release of skiboot, taking over from the 5.4 release, first released on
November 11th 2016.

skiboot-5.5.0 contains all bug fixes as of :ref:skiboot-5.4.3
and :ref:skiboot-5.1.19 (the currently maintained stable releases).

For how the skiboot stable releases work, see :ref:stable-rules for details.

This release is a good level set of POWER9 support for bringup activities.
If you are doing bringup, it is strongly suggested you continue to follow
skiboot master.

After skiboot 5.5.0, we move to a regular six week release cycle,
similar to op-build, but slightly offset to allow for a short stabilisation
period. Expected release dates and contents are tracked using GitHub milestone
and issues: https://github.com/open-power/skiboot/milestones

Changes in skiboot-5.5.0

See changes in the release candidates:

• :ref:skiboot-5.5.0-rc1
• :ref:skiboot-5.5.0-rc2
• :ref:skiboot-5.5.0-rc3

Changes since skiboot-5.5.0-rc3

• hdat: parse processor attached i2c devices

  Adds basic parsing for i2c devices that are attached to the processor
  I2C interfaces. This is mainly VPD SEEPROMs.

• libflash/blocklevel: Add blocklevel_smart_erase()

  With recent changes to flash drivers in linux not all erase blocks are
  4K anymore. While most level of the pflash/gard tool stacks were written
  to not mind, it turns out there are bugs which means not 4K erase block
  backing stores aren't handled all that well. Part of the problem is the
  FFS layout that is 4K aligned and with larger block sizes pflash and the
  gard tool don't check if their erase commands are erase block aligned -
  which they are usually not with 64K erase blocks.

  This patch aims to add common functionality to blocklevel so that (at
  least) pflash and the gard tool don't need to worry about the problem
  anymore.

• external/pflash: Use blocklevel_smart_erase()

• external/gard: Use blocklevel_smart_erase()

• libstb/create-container: Add full container build and sign with imprint keys

  This adds support for writing all the public key and signature fields to the
  container header, and for dumping the prefix and software headers so they may
  may be signed, and for signing those headers with the imprint keys.

• asm: do not set SDR1 on POWER9. This register does not exist in ISAv3.

Testing:

• mambo: Allow setting the Linux command line from the environment

  For automated testing it's helpful to be able to set the Linux command
  line via an environment variable.

• mambo: Add util function for breaking on console output

Contributors

Processed 408 csets from 31 developers

3 employers found

A total of 24073 lines added, 16759 removed (delta 7314)

Extending the analysis done for the last few releases, we can see our trends
in code review across versions:

======== ====== ======= ======= ====== ========
Release csets Ack Reviews Tested Reported
======== ====== ======= ======= ====== ========
5.0 329 15 20 1 0
5.1 372 13 38 1 4
5.2-rc1 334 20 34 6 11
5.3-rc1 302 36 53 4 5
5.4.0 361 16 28 1 9
5.5.0 408 11 48 14 10
======== ====== ======= ======= ====== ========

I am absolutely thrilled as to the uptick of reviews and tested-by occuring
over our 5.4.0 release. Although we are not yet back up to 5.3 era levels for
review, we're much closer. For tested-by, we've set a new record, which is
excellent!

Developers with the most changesets
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
========================== === =======
Developer # %
========================== === =======
Benjamin Herrenschmidt 139 (34.1%)
Stewart Smith 60 (14.7%)
Oliver O'Halloran 54 (13.2%)
Gavin Shan 23 (5.6%)
Michael Neuling 20 (4.9%)
Vasant Hegde 15 (3.7%)
Cyril Bur 15 (3.7%)
Claudio Carvalho 14 (3.4%)
Andrew Donnellan 11 (2.7%)
Ananth N Mavinakayanahalli 9 (2.2%)
Alistair Popple 6 (1.5%)
Nicholas Piggin 5 (1.2%)
Cédric Le Goater 5 (1.2%)
Pridhiviraj Paidipeddi 5 (1.2%)
Michael Ellerman 4 (1.0%)
Shilpasri G Bhat 4 (1.0%)
Russell Currey 3 (0.7%)
Jack Miller 2 (0.5%)
Chris Smart 2 (0.5%)
Dave Heller 1 (0.2%)
Akshay Adiga 1 (0.2%)
Reza Arbab 1 (0.2%)
Matt Brown 1 (0.2%)
Frederic Barrat 1 (0.2%)
Hank Chang 1 (0.2%)
Willie Liauw 1 (0.2%)
Werner Fischer 1 (0.2%)
Jeremy Kerr 1 (0.2%)
Patrick Williams 1 (0.2%)
Joel Stanley 1 (0.2%)
Alexey Kardashevskiy 1 (0.2%)
========================== === =======

Developers with the most changed lines
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

========================== ===== =======
Developer # %
========================== ===== =======
Oliver O'Halloran 18278 (48.5%)
Benjamin Herrenschmidt 5512 (14.6%)
Cyril Bur 3184 (8.4%)
Alistair Popple 3102 (8.2%)
Stewart Smith 2757 (7.3%)
Gavin Shan 802 (2.1%)
Ananth N Mavinakayanahalli 544 (1.4%)
Claudio Carvalho 489 (1.3%)
Dave Heller 425 (1.1%)
Willie Liauw 361 (1.0%)
Andrew Donnellan 315 (0.8%)
Michael Neuling 290 (0.8%)
Vasant Hegde 253 (0.7%)
Shilpasri G Bhat 228 (0.6%)
Nicholas Piggin 222 (0.6%)
Reza Arbab 198 (0.5%)
Russell Currey 158 (0.4%)
Jack Miller 127 (0.3%)
Cédric Le Goater 126 (0.3%)
Chris Smart 95 (0.3%)
Akshay Adiga 57 (0.2%)
Hank Chang 56 (0.1%)
Pridhiviraj Paidipeddi 47 (0.1%)
Michael Ellerman 29 (0.1%)
Matt Brown 29 (0.1%)
Alexey Kardashevskiy 2 (0.0%)
Frederic Barrat 1 (0.0%)
Werner Fischer 1 (0.0%)
Jeremy Kerr 1 (0.0%)
Patrick Williams 1 (0.0%)
Joel Stanley 1 (0.0%)
========================== ===== =======

Developers with the most lines removed
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
========================== ===== =======
Developer # %
========================== ===== =======
Oliver O'Halloran 8516 (50.8%)
Werner Fischer 1 (0.0%)
========================== ===== =======

Developers with the most signoffs
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Total: 364

======================== ===== =======
Developer # %
======================== ===== =======
Stewart Smith 348 (95.6%)
Michael Neuling 6 (1.6%)
Oliver O'Halloran 3 (0.8%)
Benjamin Herrenschmidt 2 (0.5%)
Vaidyanathan Srinivasan 1 (0.3%)
Hank Chang 1 (0.3%)
Jack Miller 1 (0.3%)
Gavin Shan 1 (0.3%)
Alistair Popple 1 (0.3%)
======================== ===== =======

Developers with the most reviews
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Total 50

======================== ===== =======
Developer # %
======================== ===== =======
Vasant Hegde 14 (28.0%)
Andrew Donnellan 9 (18.0%)
Russell Currey 6 (12.0%)
Cédric Le Goater 5 (10.0%)
Oliver O'Halloran 4 (8.0%)
Vaidyanathan Srinivasan 3 (6.0%)
Gavin Shan 3 (6.0%)
Alistair Popple 2 (4.0%)
Frederic Barrat 2 (4.0%)
Mahesh Salgaonkar 1 (2.0%)
Cyril Bur 1 (2.0%)
======================== ===== =======

Developers with the most test credits
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Total 14

======================== ===== =======
Developer # %
======================== ===== =======
Willie Liauw 4 (28.6%)
Mark E Schreiter 3 (21.4%)
Claudio Carvalho 3 (21.4%)
Gavin Shan 1 (7.1%)
Michael Neuling 1 (7.1%)
Pridhiviraj Paidipeddi 1 (7.1%)
Chris Smart 1 (7.1%)
======================== ===== =======

Developers who gave the most tested-by credits
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Total 14

========================== === =======
Developer # %
========================== === =======
Gavin Shan 7 (50.0%)
Stewart Smith 4 (28.6%)
Chris Smart 1 (7.1%)
Oliver O'Halloran 1 (7.1%)
Ananth N Mavinakayanahalli 1 (7.1%)
========================== === =======

Developers with the most report credits
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Total 10

============================ = =======
Developer # %
============================ = =======
Hank Chang 4 (40.0%)
Mark E Schreiter 3 (30.0%)
Guilherme G. Piccoli 1 (10.0%)
Colin Ian King 1 (10.0%)
Pradipta Ghosh 1 (10.0%)
============================ = =======

Developers who gave the most report credits
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Total 10

============================ = =======
Developer # %
============================ = =======
Gavin Shan 8 (80.0%)
Andrew Donnellan 1 (10.0%)
Jer...

skiboot-5.5.0-rc3

skiboot-5.5.0-rc3 was released on Wednesday April 5th 2017. It is the third
release candidate of skiboot 5.5, which will become the new stable release
of skiboot following the 5.4 release, first released November 11th 2016.

skiboot-5.5.0-rc3 contains all bug fixes as of :ref:skiboot-5.4.3
and :ref:skiboot-5.1.19 (the currently maintained stable releases).

For how the skiboot stable releases work, see :ref:stable-rules for details.

The current plan is to cut the final 5.5.0 by April 8th, with skiboot 5.5.0
being for all POWER8 and POWER9 platforms in op-build v1.16 (Due April 12th).
This is a short cycle as this release is mainly targetted towards POWER9
bringup efforts.

Following skiboot-5.5.0, we will move to a regular six week release cycle,
similar to op-build, but slightly offset to allow for a short stabilisation
period. Expected release dates and contents are tracked using GitHub milestone
and issues: https://github.com/open-power/skiboot/milestones

Over :ref:skiboot-5.5.0-rc2, we have the following changes:

• xive: Fix setting of remote NVT VSD

  This fixes a checkstop when using my XIVE exploitation mode on some multi-chip machines.

• core/init: Use '_' as separator in names of "exports" properties

  The names of the properties under /ibm,opal/firmware/exports are used
  directly by Linux to create files in sysfs. To remain consistent with
  the existing naming of OPAL sysfs files, use '_' as the separator.

  In particular for the symbol map which is already exported separately,
  it's cleaner for the two files to have the same name, eg: ::

  /sys/firmware/opal/exports/symbol_map
  /sys/firmware/opal/symbol_map
  

• hdata: fix reservation size

  The hostboot reserved ranges are [start, end] pairs rather than
  [start, end) so we need to stick a +1 in there to calculate the
  size properly.

• hdat: Add model-name property for OpenPower system

• hdat: Read description from ibm, vpd binary blob

• hdat: Populate model property with 'Unknown' in error path