Meeting notes from April 4th, 2023

[glopesdev]

Meeting Notes

Analog IO device

everything is loop-back, everything you write is also read

• board is always reporting current state at all times on the copper
• currently pretty happy with the current UX design
• good example to develop as it uses everything in liboni API
• there is no buffer in the hardware (sends as fast as possible one sample to all channels!)
• there is no way to have buffered playback (requests go to a FIFO that handle requests and stuff for all devices)
• if you should send two frames too quickly it could happen that one gets lost (if device is busy; the last one would be dropped):
  • the device can get interrupted
  • SPI sequences cannot be stopped (would need small buffer to save last one; drop everything is coming if target device is not able to accept it)
• outputs are always +/- 10 V
• idea: externalized properties could give you handle of which IOs are output (and set voltages)

Digital IO device

• what are "links"?
• each of 16-pins (8 are input / 8 are output)
• digital outputs and input pins are completely different hardware
• probably should be split into two separate devices (IO) but there is a reason to keep it like that due to breakout board

All the breakout board is a local HUB:

• treat all coaxials are pass-through
• the hubs have a reference switch
• except for LEDs and digital IOs
• when you create a context you create a context to top-level streams, but on FPGA there is a local hub
  • HUB 0
  • local hub can be treated like a headstage

Other Notes

• would be nice to have high-level properties used to compute low-level properties:
  • Example with tethers being so thin they require specific target voltages depending on length
  • At the top-level Headstage, we could tell it the desired tether length and check and compute target voltages
• other baroque case is Neuropix headstage:
  • neuropix configuration macro will be a challenging test case