diff --git a/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MyProcPlatform.scala b/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MyProcPlatform.scala new file mode 100644 index 0000000..afdc3c5 --- /dev/null +++ b/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MyProcPlatform.scala @@ -0,0 +1,208 @@ +/******************************************************************************* + * Copyright (c) 2023. ONERA + * This file is part of PML Analyzer + * + * PML Analyzer is free software ; + * you can redistribute it and/or modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation ; + * either version 2 of the License, or (at your option) any later version. + * + * PML Analyzer is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY ; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License along with this program ; + * if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + ******************************************************************************/ + +package onera.pmlanalyzer.pml.examples.mySys + +import onera.pmlanalyzer.pml.model.hardware.* +import onera.pmlanalyzer.pml.operators.* +import sourcecode.Name + +/** + * Simple model of the Keystone platform illustrating the main features of PML. + * The components of the architectures can be created using the constructors provided in [[pml.model.hardware.BaseHardwareNodeBuilder]] + * For instance the [[package.SimpleKeystonePlatform.dma]] is built with: + * {{{val dma: Initiator = Initiator()}}} + * An axi-bus is built with: + * {{{val axi-bus: SimpleTransporter= SimpleTransporter()}}} + * A peripheral or a memory is built with + * {{{val sram: Target = Target()}}} + * Some components may be composite, if you want to define one instance of composite you can use the object + * instantiation pattern used for the TeraNet + * {{{object TeraNet extends Composite }}} + * You can also define a type of Composite that may be instantiated afterward, for instance here ARMCores are defined + * as a composition of a core (initiator) and a cache (transporter). A name is given as a parameter of the ARMCore class + * {{{class ARMCore (name:Symbol) extends Composite }}} + * Then components can be linked together, this operation simply connect the service of the same type provided by the + * two components. For instance + * {{{ARM0.core link axi_bus}}} + * links the [[pml.model.service.Load]] and [[pml.model.service.Store]] service of the ARM0.core to the ones of the axi-bus + * Beware that all links are not possible, for instance you cannot link two [[pml.model.hardware.Target]] or a + * [[pml.model.hardware.Composite]] to another component. + * @see [[pml.operators.Link.Ops]] for link operator definition + * @see [[pml.model.hardware.BaseHardwareNodeBuilder]] for component instantiation + * @param name the name of the final object merging all facets of the model + * + */ +class MyProcPlatform(name: Symbol) extends Platform(name) { + + /** + * Enable to provide the name implicitly + * @param implicitName the name of the object/class inheriting from this class + * will be the name of platform + */ + def this()(implicit implicitName: Name) = { + this(Symbol(implicitName.value)) + } + + /** Initiator modelling the DMA + * @group initiator + */ + val dma: Initiator = Initiator() + + /** Composite modelling the Teranet + * @group composite + */ + object TeraNet extends Composite { + /** Transporter modelling the peripheral interconnect + * @group transporter */ + val periph_bus: SimpleTransporter = SimpleTransporter() + + /** Transporter modelling the register interconnect + * @group transporter */ + val config_bus: SimpleTransporter = SimpleTransporter() + + periph_bus link config_bus + } + + /** Composite modelling memory subsystem + * @group composite */ + object MemorySubsystem extends Composite { + + /** Transporter modelling the MSMC controller + * @group transporter */ + val msmc: SimpleTransporter = SimpleTransporter() + + /** Transporter modelling the DDR controller + * @group transporter */ + val ddr_ctrl: SimpleTransporter = SimpleTransporter() + + /** Target modelling the SRAM peripheral + * @group transporter */ + val sram: Target = Target() + + msmc link sram + msmc link ddr_ctrl + } + + /** Composite representing Keystone ARM cores and their internal L1 cache + * @group composite_def + */ + class ARMCore(name: Symbol) extends Composite(name) { + + /** + * Enable to provide the name implicitly + * @param implicitName the name of the object/class inheriting from this class + * will be the name of composite + */ + def this()(implicit implicitName: Name) = { + this(implicitName.value) + } + + /** Initiator modelling an ARM Core + * @group initiator */ + val core: Initiator = Initiator() + + /** Transporter modelling the cache of the core + * @group target */ + val cache: Target = Target() + + // ARM access to its private L1 cache + core link cache + + } + + /* ----------------------------------------------------------- + * Global components + * ----------------------------------------------------------- */ + + /** Composite modelling ARM0 + * @group composite + */ + val ARM0 = new ARMCore() + /** + * Composite modelling ARM1 + * @group composite + */ + val ARM1 = new ARMCore() + + /** Initiator modelling ethernet peripheral + * @group initiator + */ + val eth: Initiator = Initiator() + + /** Transporter modelling AXI bus + * @group transporter + */ + val axi_bus: SimpleTransporter = SimpleTransporter() + + /** Target modelling SPI peripheral + * @group target + */ + val spi: Target = Target() + /** Target modelling MPIC peripheral + * @group target + */ + val mpic: Target = Target() + /** Target modelling SPI registers + * @group target + */ + val spi_reg: Target = Target() + /** Target modelling DMA registers + * @group target + */ + val dma_reg: Target = Target() + /** Target modelling external DDR + * @group target + */ + val ddr: Target = Target() + + /* ----------------------------------------------------------- + * Physical connections + ----------------------------------------------------------- */ + + // Each ARM core is connected to the internal interconnect + ARM0.core link axi_bus + ARM1.core link axi_bus + + ARM0.core link TeraNet.config_bus + ARM1.core link TeraNet.config_bus + + // Eth connection to internal interconnect + eth link TeraNet.periph_bus + + // Peripheral bus connections + TeraNet.periph_bus link MemorySubsystem.msmc + + TeraNet.periph_bus link spi + + // Accesses to peripherals + TeraNet.config_bus link dma_reg + TeraNet.config_bus link spi_reg + + // Accesses to config registers + axi_bus link mpic + axi_bus link MemorySubsystem.msmc + + //MSMC connections + MemorySubsystem.msmc link TeraNet.periph_bus + + MemorySubsystem.ddr_ctrl link ddr + + // DMA connections + dma link TeraNet.periph_bus + +} diff --git a/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MyProcRoutingConfiguration.scala b/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MyProcRoutingConfiguration.scala new file mode 100644 index 0000000..0702993 --- /dev/null +++ b/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MyProcRoutingConfiguration.scala @@ -0,0 +1,33 @@ +/******************************************************************************* + * Copyright (c) 2023. ONERA + * This file is part of PML Analyzer + * + * PML Analyzer is free software ; + * you can redistribute it and/or modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation ; + * either version 2 of the License, or (at your option) any later version. + * + * PML Analyzer is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY ; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License along with this program ; + * if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + ******************************************************************************/ + +package onera.pmlanalyzer.pml.examples.mySys + +import onera.pmlanalyzer.pml.operators.* + +/** + * Routing constraints considered for simple Keystone + */ +trait MyProcRoutingConfiguration { + self: MyProcPlatform => + + //Arm cores, ethernet and dma cannot use the periph_bus from msmc + ARM0.core cannotUseLink MemorySubsystem.msmc to TeraNet.periph_bus + ARM1.core cannotUseLink MemorySubsystem.msmc to TeraNet.periph_bus + eth cannotUseLink MemorySubsystem.msmc to TeraNet.periph_bus + dma cannotUseLink MemorySubsystem.msmc to TeraNet.periph_bus +} diff --git a/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MySysExport.scala b/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MySysExport.scala new file mode 100644 index 0000000..ec29883 --- /dev/null +++ b/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MySysExport.scala @@ -0,0 +1,67 @@ +/** ***************************************************************************** + * Copyright (c) 2023. ONERA + * This file is part of PML Analyzer + * + * PML Analyzer is free software ; + * you can redistribute it and/or modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation ; + * either version 2 of the License, or (at your option) any later version. + * + * PML Analyzer is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY ; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License along with this program ; + * if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * **************************************************************************** */ + +package onera.pmlanalyzer.pml.examples.mySys + +import onera.pmlanalyzer.pml.exporters.* +import onera.pmlanalyzer.pml.model.utils.Message +import onera.pmlanalyzer.pml.operators.* +import onera.pmlanalyzer.views.interference.examples.mySys.{MySysApplicativeTableBasedInterferenceSpecification, MySysPhysicalTableBasedInterferenceSpecification} + +/** + * Program entry point to export several version of Keystone + */ +object MySysExport extends App { + + /** + * Keystone where all transactions are considered + * + * @group platform_def + */ + object MySys extends MyProcPlatform + with MySysLibraryConfiguration + with MyProcRoutingConfiguration + with MySysPhysicalTableBasedInterferenceSpecification + with MySysApplicativeTableBasedInterferenceSpecification + + // Export only HW used by SW (explicit) + MySys.exportRestrictedHWAndSWGraph() + // Export HW and SW graph whether used or not + MySys.exportHWAndSWGraph() + + // Export individually the Service graph of each software + MySys.applications foreach { s => MySys.exportRestrictedServiceGraphForSW(s) } + + // Export the application allocation table + MySys.exportAllocationTable() + + // Export the data allocation table + MySys.exportDataAllocationTable() + + // Export the target used by software + MySys.exportSWTargetUsageTable() + + // Export the routing constraints + MySys.exportRouteTable() + + // Export the deactivated components + MySys.exportDeactivatedComponents() + + // Export the transactions defined by the user + MySys.exportUserScenarios() + +} diff --git a/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MySysLibraryConfiguration.scala b/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MySysLibraryConfiguration.scala new file mode 100644 index 0000000..4c5eb8b --- /dev/null +++ b/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MySysLibraryConfiguration.scala @@ -0,0 +1,46 @@ +/******************************************************************************* + * Copyright (c) 2023. ONERA + * This file is part of PML Analyzer + * + * PML Analyzer is free software ; + * you can redistribute it and/or modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation ; + * either version 2 of the License, or (at your option) any later version. + * + * PML Analyzer is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY ; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License along with this program ; + * if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + ******************************************************************************/ + +package onera.pmlanalyzer.pml.examples.mySys + +/** + * Transaction that are used/ + * A user transaction is considered during the analyses if identified as so. + * For instance to indicate that the t11 transaction defined in [[MySysTransactionLibrary]] is used + * {{{t11.used}}} + * @see [[pml.operators.Use.Ops]] for operator definition + */ +trait MySysLibraryConfiguration extends MySysTransactionLibrary with MySysSoftwareAllocation { + self: MyProcPlatform => + + t11.used + t12.used + t13.used + t14.used + + t21.used + + t22.used + t23.used + t24.used + t25.used + t26.used + + t31.used + + t41.used +} diff --git a/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MySysSoftwareAllocation.scala b/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MySysSoftwareAllocation.scala new file mode 100644 index 0000000..2025126 --- /dev/null +++ b/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MySysSoftwareAllocation.scala @@ -0,0 +1,130 @@ +/******************************************************************************* + * Copyright (c) 2023. ONERA + * This file is part of PML Analyzer + * + * PML Analyzer is free software ; + * you can redistribute it and/or modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation ; + * either version 2 of the License, or (at your option) any later version. + * + * PML Analyzer is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY ; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License along with this program ; + * if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + ******************************************************************************/ + +package onera.pmlanalyzer.pml.examples.mySys + +import onera.pmlanalyzer.pml.model.software.{Application, Data} +import onera.pmlanalyzer.pml.operators.* + +import scala.language.postfixOps + +/** + * Definition and allocation of software and data to hardware for simple Keystone. + * Declaring the application app1 + * {{{val app1: Application = Application()}}} + * Allocating app1 on [[pml.examples.simpleKeystone.SimpleKeystonePlatform.ARM0]] + * {{{app1 hostedBy ARM0.core}}} + * Declaring the data input_d + * {{{val input_d: Data = Data()}}} + * Allocating app1 on [[pml.examples.simpleKeystone.SimpleKeystonePlatform.MemorySubsystem.sram]] + * {{{input_d hostedBy MemorySubsystem.sram}}} + * @see [[pml.operators.Use.Ops]] for hostedBy operator definition + */ +trait MySysSoftwareAllocation { + self: MyProcPlatform => + + /* ----------------------------------------------------------- + * Application declaration + * ----------------------------------------------------------- */ + + /** [[app1]] is an asynchronous applicative activated each time a external interrupt arrives + * @group application + */ + val app1: Application = Application() + + /** At each period [[app21]] reads the last Ethernet message from [[SimpleKeystonePlatform.MemorySubsystem.sram]], + * makes some input treatments on the message, and makes it available for [[app1]] in [[SimpleKeystonePlatform.ddr]]. + * @group application + */ + val app21: Application = Application() + + /** At each period [[app22]] reads output data of [[app1]] from [[SimpleKeystonePlatform.ddr]]. + * It transforms them into [[SimpleKeystonePlatform.spi]] frames. + * The frames are then store in [[SimpleKeystonePlatform.MemorySubsystem.sram]]. And finally [[app22]] wakes up [[app3]] + * by writing the address of the [[SimpleKeystonePlatform.spi]] frames into [[SimpleKeystonePlatform.dma_reg]]. + * @group application + * */ + val app22: Application = Application() + + /** [[app3]] is a microcode running on [[SimpleKeystonePlatform.dma]]. When woke up, + * [[app3]] reads the [[SimpleKeystonePlatform.spi]] frame from [[SimpleKeystonePlatform.MemorySubsystem.sram]] + * and transfers it to [[SimpleKeystonePlatform.spi]] + * @group application + * */ + val app3: Application = Application() + + /** [[app4]] is an asynchronous microcode running on the [[SimpleKeystonePlatform.eth]] component. + * Each time an [[SimpleKeystonePlatform.eth]] frame arrives, it transfers the payload of the + * frame to [[SimpleKeystonePlatform.MemorySubsystem.sram]]. + * @group application + * */ + val app4: Application = Application() + + + /* ----------------------------------------------------------- + * Data declaration + * ----------------------------------------------------------- */ + + /** Data written by [[SimpleKeystonePlatform.eth]] in [[SimpleKeystonePlatform.MemorySubsystem.sram]] and read by [[app21]] + * @group data */ + val ethernet_frame: Data = Data() + /** Data written by [[app21]] in [[SimpleKeystonePlatform.ddr]] and read by [[app1]] + * @group data */ + val input_app1: Data = Data() + /** Interrupt read by [[app1]] + * @group data */ + val interrupt_code: Data = Data() + /** Data written by [[app1]] in [[SimpleKeystonePlatform.ddr]] and read by [[app22]] + * @group data */ + val output_app1: Data = Data() + /** Data written by [[app22]] in [[SimpleKeystonePlatform.MemorySubsystem.sram]] and read by [[SimpleKeystonePlatform.dma]] + * @group data*/ + val spi_frame: Data = Data() + /** Register value written by [[app21]] in [[SimpleKeystonePlatform.dma_reg]] + * @group data */ + val dma_reg_value: Data = Data() + /** [[SimpleKeystonePlatform.spi]] frame put by [[SimpleKeystonePlatform.dma]] on the [[SimpleKeystonePlatform.spi]] port + * @group data */ + val output_spi_frame: Data = Data() + /** Private cache of [[app1]] + * @group data */ + val app1_cache: Data = Data() + + /* ----------------------------------------------------------- + * Data allocation + * ----------------------------------------------------------- */ + + input_app1 hostedBy ddr + interrupt_code hostedBy mpic + app1_cache hostedBy ARM0.cache + output_app1 hostedBy ddr + spi_frame hostedBy MemorySubsystem.sram + dma_reg_value hostedBy dma_reg + output_spi_frame hostedBy spi + ethernet_frame hostedBy MemorySubsystem.sram + + /* ----------------------------------------------------------- + * Application allocation + * ----------------------------------------------------------- */ + + app1 hostedBy ARM0.core + app21 hostedBy ARM1.core + app22 hostedBy ARM1.core + app3 hostedBy dma + app4 hostedBy eth + +} diff --git a/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MySysTransactionLibrary.scala b/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MySysTransactionLibrary.scala new file mode 100644 index 0000000..77cf428 --- /dev/null +++ b/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/MySysTransactionLibrary.scala @@ -0,0 +1,104 @@ +/******************************************************************************* + * Copyright (c) 2023. ONERA + * This file is part of PML Analyzer + * + * PML Analyzer is free software ; + * you can redistribute it and/or modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation ; + * either version 2 of the License, or (at your option) any later version. + * + * PML Analyzer is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY ; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License along with this program ; + * if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + ******************************************************************************/ + +package onera.pmlanalyzer.pml.examples.mySys + +import onera.pmlanalyzer.pml.model.configuration.TransactionLibrary +import onera.pmlanalyzer.pml.operators.* + +import scala.language.postfixOps + +/** + * This trait contains a library of all transactions that can occur on the platform + * One way to define a [[pml.model.configuration.TransactionLibrary.Transaction]] or + * a [[pml.model.configuration.TransactionLibrary.Scenario]] is to use the read/write operators specifying + * which [[pml.model.software.Data]] is used by which [[pml.model.software.Application]]. + * For instance + * {{{val app4_wr_input_d : Transaction = Transaction(app4 write input_d)}}} + * defines a read transaction called '''app4_wr_input_d''' between the initiator of app4 and the input_d data. + * The location of the application and the data are provided in the [[MySysSoftwareAllocation]] trait. + * + * If you want to define several paths representing a multi-transaction use the [[pml.model.configuration.TransactionLibrary.Scenario]] + * For instance + * {{{val app1_rd_wr_L1 : Scenario = Scenario(app1_rd_L1, app1_wr_L1)}}} + * defines a scenario named '''app1_rd_wr_L1''' where app1 is reading and writing L1 cache + * @note A transaction or a scenario is only '''declared''' here, it will be considered during the interference analysis if it is + * actually used. This is done in the [[SimpleKeystoneLibraryConfiguration]] files. + * A transaction should be a path from an initiator to a target, if several paths are possible a warning will be raised. + * @see [[pml.operators.Use.Ops]] for read/write operator definitions + * */ +trait MySysTransactionLibrary extends TransactionLibrary { + self: MyProcPlatform with MySysSoftwareAllocation => + + /** t11: [[MySysSoftwareAllocation.app1]] begins by reading the interrupt code from [[MyProcPlatform.mpic]] + * @group transaction_def */ + val t11 : Transaction = Transaction(app1 read interrupt_code) + + /** t12: [[MySysSoftwareAllocation.app1]] reads its input data from [[MyProcPlatform.ddr]] + * @group transaction_def*/ + val t12 : Transaction = Transaction(app1 read input_app1) + + private val app1_rd_L1: Transaction = Transaction(app1 read ARM0.cache) + private val app1_wr_L1: Transaction = Transaction(app1 write ARM0.cache) + /** t13: [[MySysSoftwareAllocation.app1]] runs using [[MyProcPlatform.ARM0]] cache + * + * @group scenario_def */ + val t13: Scenario = Scenario(app1_rd_L1, app1_wr_L1) + + /** t14: [[MySysSoftwareAllocation.app1]] it stores its output data in [[MyProcPlatform.ddr]] + * @group transaction_def */ + val t14 : Transaction = Transaction(app1 write output_app1) + + /** t21: [[MySysSoftwareAllocation.app21]] reads [[MyProcPlatform.dma_reg]] value + * @group transaction_def */ + val t21 : Transaction = Transaction(app21 read dma_reg_value) + + /** t22: [[MySysSoftwareAllocation.app22]] load the Ethernet frame in [[MyProcPlatform.MemorySubsystem.sram]] + * @group transaction_def*/ + val t22 : Transaction = Transaction(app22 read ethernet_frame) + + /** t23: [[MySysSoftwareAllocation.app22]] stores the processed Ethernet frame in [[MyProcPlatform.ddr]] + * and makes it available for [[MySysSoftwareAllocation.app1]] + * @group transaction_def */ + val t23: Transaction = Transaction(app22 write input_app1) + + /** t24: [[MySysSoftwareAllocation.app22]] reads the output of [[MySysSoftwareAllocation.app1]] + * and transforms them into SPI frames + * @group transaction_def */ + val t24: Transaction = Transaction(app22 read output_app1) + + /** t25: [[MySysSoftwareAllocation.app22]] writs the transformation in [[MyProcPlatform.MemorySubsystem.sram]] + * @group transaction_def */ + val t25: Transaction = Transaction(app22 read spi_frame) + + /** t26: [[MySysSoftwareAllocation.app22]] wakes up the [[MyProcPlatform.dma]] by + * writing the address of the [[MyProcPlatform.spi]] + * frames into [[MyProcPlatform.dma_reg]] + * @group transaction_def*/ + val t26 : Transaction = Transaction(app22 write dma_reg) + + /** t31: When woke up, [[MySysSoftwareAllocation.app3]] reads the [[MyProcPlatform.spi]] frame + * from [[MyProcPlatform.MemorySubsystem.sram]] and transfers it to [[MyProcPlatform.spi]] + * @group scenario_def*/ + val t31: Scenario = Scenario(app3 read spi_frame, app3 write output_spi_frame) + + /** t41: Each time an [[MyProcPlatform.eth]] frame arrives, it transfers the payload of the frame + * to [[MyProcPlatform.MemorySubsystem.sram]] + * @group transaction_def */ + val t41 : Transaction = Transaction(app4 write ethernet_frame) + +} diff --git a/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/mySys.scala b/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/mySys.scala new file mode 100644 index 0000000..c1d54c2 --- /dev/null +++ b/src/main/scala/onera/pmlanalyzer/pml/examples/mySys/mySys.scala @@ -0,0 +1,28 @@ +/******************************************************************************* + * Copyright (c) 2023. ONERA + * This file is part of PML Analyzer + * + * PML Analyzer is free software ; + * you can redistribute it and/or modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation ; + * either version 2 of the License, or (at your option) any later version. + * + * PML Analyzer is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY ; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License along with this program ; + * if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + ******************************************************************************/ + +package onera.pmlanalyzer.pml.examples + +/** + * Package containing an example on a simplification of a TI Keystone platform + * @see [[MyProcPlatform]] for examples of [[pml.model.hardware.Hardware]] modelling features + * [[MySysSoftwareAllocation]] for examples of [[pml.model.software.Application]] modelling features + * [[MySysTransactionLibrary]] for examples of transaction/scenario modelling features + * [[MySysLibraryConfiguration]] for example of transaction library configuration + * [[MySysExport]] for examples of platform instantiation and [[pml.exporters]] usage + */ +package object mySys diff --git a/src/main/scala/onera/pmlanalyzer/pml/examples/simpleKeystone/SimpleSoftwareAllocation.scala b/src/main/scala/onera/pmlanalyzer/pml/examples/simpleKeystone/SimpleSoftwareAllocation.scala index 780ca76..f639d33 100644 --- a/src/main/scala/onera/pmlanalyzer/pml/examples/simpleKeystone/SimpleSoftwareAllocation.scala +++ b/src/main/scala/onera/pmlanalyzer/pml/examples/simpleKeystone/SimpleSoftwareAllocation.scala @@ -96,7 +96,7 @@ trait SimpleSoftwareAllocation { val output_d: Data = Data() /** Register value written by [[app21]] in [[SimpleKeystonePlatform.dma_reg]] * @group data */ - val dma_red_value: Data = Data() + val dma_reg_value: Data = Data() /** [[SimpleKeystonePlatform.spi]] frame put by [[SimpleKeystonePlatform.dma]] on the [[SimpleKeystonePlatform.spi]] port * @group data */ val output_spi_frame: Data = Data() @@ -110,7 +110,7 @@ trait SimpleSoftwareAllocation { interrupt1 hostedBy mpic d2 hostedBy ddr output_d hostedBy MemorySubsystem.sram - dma_red_value hostedBy dma_reg + dma_reg_value hostedBy dma_reg output_spi_frame hostedBy spi /* ----------------------------------------------------------- diff --git a/src/main/scala/onera/pmlanalyzer/pml/exporters/RelationExporter.scala b/src/main/scala/onera/pmlanalyzer/pml/exporters/RelationExporter.scala index d97013f..a6a10e3 100644 --- a/src/main/scala/onera/pmlanalyzer/pml/exporters/RelationExporter.scala +++ b/src/main/scala/onera/pmlanalyzer/pml/exporters/RelationExporter.scala @@ -249,9 +249,14 @@ object RelationExporter { import platform._ for { (n,s) <- scenarioByUserName.toSeq.sortBy(_._1.toString) - t <- s.map(transactionsByName).toSeq.sortBy(_.toString()) + t = s.map(transactionsByName).map( x => + if(s.size <= 1) + x.mkString("\u2219") + else + x.mkString("(","\u2219",")") + ).toSeq.sorted } - writer.write(s"$n, ${t.mkString("\u2219")}\n") + writer.write(s"$n, ${t.mkString("+")}\n") writer.flush() writer.close() } diff --git a/src/main/scala/onera/pmlanalyzer/views/interference/examples/mySys/MySysApplicativeTableBasedInterferenceSpecification.scala b/src/main/scala/onera/pmlanalyzer/views/interference/examples/mySys/MySysApplicativeTableBasedInterferenceSpecification.scala new file mode 100644 index 0000000..04bd484 --- /dev/null +++ b/src/main/scala/onera/pmlanalyzer/views/interference/examples/mySys/MySysApplicativeTableBasedInterferenceSpecification.scala @@ -0,0 +1,42 @@ +/******************************************************************************* + * Copyright (c) 2023. ONERA + * This file is part of PML Analyzer + * + * PML Analyzer is free software ; + * you can redistribute it and/or modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation ; + * either version 2 of the License, or (at your option) any later version. + * + * PML Analyzer is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY ; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License along with this program ; + * if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + ******************************************************************************/ + +package onera.pmlanalyzer.views.interference.examples.mySys + +import onera.pmlanalyzer.pml.examples.mySys.{MySysLibraryConfiguration, MyProcPlatform, MySysTransactionLibrary, MySysSoftwareAllocation} +import onera.pmlanalyzer.pml.operators.* +import onera.pmlanalyzer.views.interference.model.specification.ApplicativeTableBasedInterferenceSpecification +import onera.pmlanalyzer.views.interference.operators.* + +/** + * The interference calculus assumptions for the MySys's applications are gathered here. + * For instance app22 and app3 cannot execute simultaneously so + * {{{app22 exclusiveWith app3}}} + * The app3 transfer transaction does not significantly impact the [[TeraNet]] + * {{{app3 notInterfereWith TeraNet.periph_bus.loads}}} + * @see [[views.interference.operators.Exclusive.Ops]] for interfere operator definition + */ +trait MySysApplicativeTableBasedInterferenceSpecification extends ApplicativeTableBasedInterferenceSpecification { + self: MyProcPlatform with MySysTransactionLibrary with MySysLibraryConfiguration with MySysSoftwareAllocation => + + app22 exclusiveWith app3 + + t11 notInterfereWith axi_bus.loads + app3 notInterfereWith TeraNet.periph_bus.loads + app3 notInterfereWith TeraNet.periph_bus.stores + app3 notInterfereWith MemorySubsystem.msmc.loads +} diff --git a/src/main/scala/onera/pmlanalyzer/views/interference/examples/mySys/MySysPhysicalTableBasedInterferenceSpecification.scala b/src/main/scala/onera/pmlanalyzer/views/interference/examples/mySys/MySysPhysicalTableBasedInterferenceSpecification.scala new file mode 100644 index 0000000..de9cac5 --- /dev/null +++ b/src/main/scala/onera/pmlanalyzer/views/interference/examples/mySys/MySysPhysicalTableBasedInterferenceSpecification.scala @@ -0,0 +1,70 @@ +/******************************************************************************* + * Copyright (c) 2023. ONERA + * This file is part of PML Analyzer + * + * PML Analyzer is free software ; + * you can redistribute it and/or modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation ; + * either version 2 of the License, or (at your option) any later version. + * + * PML Analyzer is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY ; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License along with this program ; + * if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + ******************************************************************************/ + +package onera.pmlanalyzer.views.interference.examples.mySys + +import onera.pmlanalyzer.pml.examples.mySys.MyProcPlatform +import onera.pmlanalyzer.pml.operators.* +import onera.pmlanalyzer.views.interference.model.specification.PhysicalTableBasedInterferenceSpecification +import onera.pmlanalyzer.views.interference.operators.* + +/** + * The interference calculus assumptions for the hardware components of the MySys are gathered here. + * For instance to specify that two service l and r interfere with each other if + * + * - they are provided by the same owner except for + * [[pml.examples.mySys.MyProcPlatform.TeraNet.periph_bus]], [[pml.examples.mySys.MyProcPlatform.axi_bus]], + * [[pml.examples.mySys.MyProcPlatform.MemorySubsystem.msmc]] + * - they are provided by the [[pml.examples.mySys.MyProcPlatform.dma]] and [[pml.examples.mySys.MyProcPlatform.dma_reg]] + * {{{ + * for { + * l <- services + * r <- services + * if l != r + * if (l.hardwareOwnerIs(dma) && r.hardwareOwnerIs(dma_reg)) || + * (l.hardwareOwner == r.hardwareOwner && !l.hardwareOwnerIs(TeraNet.periph_bus) + * && !l.hardwareOwnerIs(axi_bus) && !l.hardwareOwnerIs(MemorySubsystem.msmc)) + * } yield { + * l interfereWith r + * } + * }}} + */ +trait MySysPhysicalTableBasedInterferenceSpecification extends PhysicalTableBasedInterferenceSpecification { + self: MyProcPlatform => + + //Encoding of Rule 1 and Rule 2 + for { + l <- services + r <- services + if l != r + if (l.hardwareOwnerIs(dma) && r.hardwareOwnerIs(dma_reg)) || + (l.hardwareOwner == r.hardwareOwner && !l.hardwareOwnerIs(TeraNet.periph_bus) && !l.hardwareOwnerIs(axi_bus) && !l.hardwareOwnerIs(MemorySubsystem.msmc)) + } yield { + l interfereWith r + } + + //All transactions issued from the same initiator are exclusive + for { + l <- transactions + r <- transactions + if l != r + if l.initiator == r.initiator + } yield { + l exclusiveWith r + } + +}