v2.5-rc

This is a release candidate for oneDNN v2.5. Please provide feedback and submit defect reports via Github issues.

Performance Optimizations

• Intel Architecture Processors
  • Improved performance for future Intel Xeon Scalable processors (code name Sapphire Rapids). The functionality is disabled by default and should be enabled via CPU dispatcher control.
  • Improved performance of matmul primitive for processors with Intel AVX-512 support.
• Intel Graphics Products
  • Introduced initial optimizations for future Xe Architecture graphics (code name Ponte Vecchio).
  • Improved pooling and layer normalization primitives performance.
• AArch64-based Processors
  • Improved softmax primitive performance with Arm Compute Library (ACL)

Functionality

• Introduced support for compiler with SYCL 2020 standard support.
• Introduced support for the ICX/ICPX and DPCPP compiler drivers available in the Intel oneAPI DPC++ Compiler.

Usability

• Added compile time option to manage the set of supported instruction set architectures on Intel64/AMD64 processors. See 'DNNL_ENABLE_PRIMITIVE_CPU_ISA' for more details. This feature further reduces the binary footprint.
• Added environment variables and build options with 'ONEDNN' prefix.
• Introduced support for QNX operating system.
• Introduced support for RISC-V architecture.

Breaking Changes

• The Intel MKL-DNN compatibility API is removed. See Transition from Intel MKL-DNN to oneDNN page for instructions on moving to the new API.

Deprecated Functionality

• Support for Intel Xeon Phi processors is deprecated and will be removed in the next release.
• Support for SYCL 1.2.1 (aka SYCL 2017 standard) is deprecated and will be removed in future releases.

Thanks to the Contributors

This release contains contributions from the project core team as well as Aaron Franke @aaronfranke, Arthur Mitrano @aaraujom, Crefeda Rodrigues @cfRod, Diana Bite @diaena, Joel Dippold @jedippold, Joe Konno @thac0, Jonathan Deakin @jondea, Luke Ireland @LukeIreland1, Mark Ryan @markdryan, Mesut Meterelliyoz @mmeterel, Michel Migdal @Michoumichmich, Nathan John Sircombe @nSircombe, Pablo Romero @pablorcum, Peter Caday @petercad, Sergey Razumovskiy @srazumov, and Tsao Zhong @CaoZhongZ. We would also like to thank everyone who asked questions and reported issues.

v2.4.4

This is a patch release containing the following changes to v2.4.3:

• Fixed incorrect results for reorder with zero-points on CPUs (ee63629)
• Fixed an issue with reorder with zero-points not respecting rounding mode on processors without Intel DL Boost support (a165c4a)
• Fixed correctness issue in bfloat16 inner product weight gradient on processors with Intel DL Boost support (b782f19)
• Improved bfloat16 inner product weights gradient performance on processors with Intel AMX support (ebf9f81)
• Fixed potential undefined access in convolution, inner product, matmul, and RNNs primitives on processors with Intel AMX support (dcd98ad)

graph-v0.3

This is a technical preview for oneDNN Graph API based on oneDNN v2.4.

Functionality

• Introduced int8 inference support.
• Updated API to comply with oneDNN Graph API specification v0.8.

Known Issues and Limitations

• Some subgraphs might not be recognized as a partition even if it matches the general pattern description due to internal implementation.
• The weight’s opaque layout can be queried only from a compiled partition, which requires that tensor shapes must be known at compilation time.

Thanks to the Contributors

This release contains contributions from the project core teams as well as Tian Feng, Zhang Guoming, Jiong Gong, Chunyuan Wu, Nishant Patel, Yiqiang Li, Yang Sheng, Yunfei Mao, Kiefer Kuah and others.

v2.4.3

This is a patch release containing the following changes to v2.4.2:

• Fixed and issue with reorder primitive producing NaN results for some cases on future Intel Xeon Scalable processor (code name Sapphire Rapids) (ac20af3)
• Fixed performance regression for inner product primitive for future Intel Xeon Scalable processor (code name Sapphire Rapids) (ac6a24d, 2cf3526, d02dddf, bcdc175)
• Fixed segmentation fault in int8 deconvolution primitive with asymmetric quantization for processors with Intel AVX-512 support (6ba086a)

v2.4.2

This is a patch release containing the following changes to v2.4.1:

• Fixed performance regression for convolution primitive for the shapes with 3D spatial for future Intel Xeon Scalable processor (code name Sapphire Rapids) (aca0af1)
• Fixed segmentation fault in bfloat16 forward and backward inner product primitive or future Intel Xeon Scalable processor (code name Sapphire Rapids) (ae8cf18, 3de9549)
• Fixed reorder primitive with compensation (6ba086a)
• Fixed issue in scratch pad size calculation for BRGEMM-based convolutions (dd9eceb)

v2.3.3

This is a patch release containing the following changes to v2.3.2:

• Reverted check for memory descriptor stride validity for unit dimensions (861c625)
• Fixed build errors on Fucshia OS (753b531)
• Fixed implicit conversion in GPU GEMM implementation (30dee23)
• Addressed issues detected by clang TSan (888ab52, 7555fd8, 4ffdb3c, 57b8ffd, b52b2c0, 84b200f, 67deb8e)
• Fixed undefined access issues detected by clang UBSan (5bab17c, 3494b1e, 6885360, 8cbe861, b13a215, 859622d, 5813c99)
• Fixed memory leak in CPU GEMM implementation (45e3039, fd6d14c)
• Fixed int8 convolution correctnes issues on Intel Integrated Graphics (b7d40a0, 72e4856)
• Fixed access violation issue in GEMM implementation on Windows (aac6b23)

v2.4.1

This is a patch release containing the following changes to v2.4:

• Reduced scratch pad size requirements for BRGEMM-based convolutions (a81ce3c)
• Worked around an issue with the number of threads detection on AMD processors (ad901e5)

v2.4

Performance Optimizations

• Improved primitive cache performance for Intel Graphics products.
• Intel Architecture Processors
  • Improved performance for future Intel Xeon Scalable processor (code name Sapphire Rapids). The functionality is disabled by default and should be enabled via CPU dispatcher control.
  • Improved binary primitive performance for cases when one of the tensors is broadcasted.
  • Improved performance of reduction primitive, reorder, shuffle primitives.
  • Improved performance of depthwise convolution forward propagation for processors with Intel AVX5-12 support
  • Improved performance of forward inner product primitive for the shapes with minibatch equal to 1 for processors with Intel AVX-512 support
  • Improved performance of int8 matmul and inner product primitives for processors with Intel AVX2 and Intel DL Boost support
• Intel Graphics Products
  • Introduced initial optimizations for future Intel Arc graphics (code name Alchemist and DG2).
  • Improved performance of convolution and deconvolution primitives with new JIT convolution kernel generator implementation. These optimizations are identified by jit:ir marker in oneDNN verbose log.
• AArch64-based Processors
  • Added support for bfloat16 acceleration with Arm Compute Library (ACL). The behavior is controlled by floating point math mode API.
  • Improved inner product, matmul, and eltwise primitives performance with ACL.
  • Introduced support for sum and for indirect and Winograd convolution implementations with ACL.
• NVIDIA Graphics
  • Improved convolution performance with eltwise post-op.

Functionality

• Introduced PReLU post-op support in convolution and matmul.
• Extended maximum allowed post-ops chain for compute primitives (convolution, deconvolution, inner product, and matmul) to 32.
• Introduced support for zero points in sum post-op for convolution and matmul. The functionality is implemented only for CPUs.
• Extended binary primitive with support for mixed data types for input tensors. The functionality is implemented only for CPUs.
• Extended sum post-op for convolution and matmul primitives with support for mixed data types. The functionality is implemented only for CPUs.
• Added Unified Shared Memory (USM) support for OpenCL GPU runtime.

Usability

• Added compile time options to manage the set of supported primitives and workload types. See DNNL_ENABLE_WORKLOAD and DNNL_ENABLE_PRIMITIVE in build options for more details. This feature allows to reduce binary footprint of the library for specialized applications.
• Reduced overall library size by trimming down use of templates, OpenCL headers, and TBB headers. The configurations that benefitted the most are CPU only configuration with TBB threading and GPU only configuration. Note, that binary footprint depends on the compiler used to build the library and build options.
• Introduced floating point math mode API. The API allows the library to use bfloat16 or float16 hardware acceleration in fp32 operations. Currently this mode is supported only on AArch64 processors when oneDNN is built with ACL.
• Added a build option DNNL_LIBRARY_NAME to change the library name and CMake target. This feature helps projects that use multiple oneDNN configurations.

Breaking Changes

• Updated minimal supported ACL version to 21.08 (was 21.05).

Deprecated functionality

• Intel MKL-DNN compatibility API is deprecated and will be removed in the next update. See Transition from Intel MKL-DNN to oneDNN page for instructions on moving to new API.
• Support for Intel Xeon Phi processors is deprecated and will be removed in the next release.

Thanks to the Contributors

This release contains contributions from the project core team as well as
Aleksandr Nikolaev @alenik01, Arthur Mitrano @aaraujom, Crefeda Rodrigues @cfRod, Diana Bite @diaena, Jing Xu @jingxu10, Kentaro Kawakami @kawakami-k, Kevin Putnam @intelkevinputnam, Mesut Meterelliyoz @mmeterel, MITSUNARI Shigeo @herumi, Nathan John Sircombe @nSircombe, Nicolas Chauvet @kwizart, Peter Caday @petercad. We would also like to thank everyone who asked questions and reported issues.

v2.4-rc

This is a release candidate for oneDNN v2.4. Please provide feedback and submit defect reports via Github issues.

Performance Optimizations

• Improved primitive cache performance for Intel Graphics products.
• Intel Architecture Processors
  • Improved performance for future Intel Xeon Scalable processor (code name Sapphire Rapids). The functionality is disabled by default and should be enabled via CPU dispatcher control.
  • Improved binary primitive performance for cases when one of the tensors is broadcasted.
  • Improved reorder primitive performance for memory formats with padding and/or zero points.
• Intel Graphics Products
  • Introduced initial optimizations for future Intel Arc graphics (code name Alchemist and DG2).
• AArch64-based Processors
  • Improved inner product and eltwise primitives performance with ACL.
  • Introduced support for sum and for indirect and Winograd convolution implementations with ACL.
• NVIDIA Graphics
  • Improved convolution performance with eltwise post-op.

Functionality

• Introduced PReLU post-op support in convolution and matmul.
• Extended maximum allowed post-ops chain for compute primitives (convolution, deconvolution, inner product, and matmul) to 32.
• Introduced support for zero points in sum post-op for convolution and matmul. The functionality is implemented only for CPUs.
• Extended binary primitive with support for mixed data types for input tensors. The functionality is implemented only for CPUs.
• Extended sum post-op for convolution and matmul primitives with support for mixed data types. The functionality is implemented only for CPUs.
• Added USM support for OpenCL GPU runtime.

Usability

• Added compile time options to manage the set of supported primitives and workload types. See DNNL_ENABLE_WORKLOAD and DNNL_ENABLE_PRIMITIVE in build options for more details. This feature allows to reduce binary footprint of the library for specialized applications.
• Reduced overall library size by trimming down use of templates, OpenCL headers, and TBB headers. The configurations that benefitted the most are CPU only configuration with TBB threading and GPU only configuration. Note, that binary footprint depends on the compiler used to build the library and build options.
• Introduced floating point math mode API. The API allows the library to use bfloat16 or float16 hardware acceleration in fp32 operations. Currently this mode is not supported in the implementation.
• Added a build option DNNL_LIBRARY_NAME to change the library name and CMake target. This feature helps projects that use multiple oneDNN configurations.

Breaking Changes

• Updated minimal supported ACL version from 21.08 (was 21.05).

Deprecated functionality

• Intel MKL-DNN compatibility API is deprecated and will be removed in the next update. See Transition from Intel MKL-DNN to oneDNN page for instructions on moving to new API.

Thanks to the Contributors

This release contains contributions from the project core team as well as
Aleksandr Nikolaev @alenik01, Arthur Mitrano @aaraujom, Diana Bite @diaena, Jing Xu @jingxu10, Kentaro Kawakami @kawakami-k, Kevin Putnam @intelkevinputnam, MITSUNARI Shigeo @herumi, Nathan John Sircombe @nSircombe, Nicolas Chauvet (kwizart) @kwizart, Peter Caday @petercad. We would also like to thank everyone who asked questions and reported issues.

graph-v0.2

This is a technical preview for oneDNN Graph API based on oneDNN v2.3.2.

oneDNN Graph API extends oneDNN with a unified, high-level graph API for multiple AI hardware classes (CPU, GPU, accelerators). The graph interface integrates with the deep learning frameworks and inference engines to maximize opportunities for performance optimizations across a variety of hardware targets. This preview has full support for the oneAPI Graph programming model and partial support of the operations in oneDNN Graph API specification v0.7.

Learn more about oneDNN Graph API:

• Introduction to oneDNN Graph API
• Getting started with C++ API
• Getting started with DPC++ API

Supported Functionality

• C++ and DPC++ API.
• Graph partition and compilation API.
• Operations and fusions targeting fp32 inference for CNNs, MLPs, and transformer neural networks.

Performance Optimizations

Backend implementation relies on oneDNN and includes performance optimizations for Intel Architecture processors with Intel SSE4.1, Intel AVX, Intel AVX2, or Intel AVX512 instruction set.

Validation

• Gtest suite is available for basic functional testing.
• Comprehensive functional and performance validation is covered by the extended version of benchdnn.

Known Issues and Limitations

• Some subgraphs might not be recognized as a partition even if it matches the general pattern description due to internal implementation.
• The weight’s opaque layout can be queried only from a compiled partition, which requires that tensor shapes must be known at compilation time.
• Binary operation with scalar and tensor inputs is not optimized.

Thanks to the Contributors

This release contains contributions from the project core teams as well as Jiong Gong, Pinzhen Xu, Chunyuan Wu, Jianping Chen, Scott Cyphers, Nishant Patel, Yiqiang Li, Yang Sheng, Kiefer Kuah, Adam Straw, Tim Zerrell, Namrata Choudhury and others.