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serv.core
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serv.core
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CAPI=2:
name : ::serv:1.3.0
filesets:
core:
files:
- "tool_verilator? (data/verilator_waiver.vlt)" : {file_type: vlt}
- rtl/serv_bufreg.v
- rtl/serv_bufreg2.v
- rtl/serv_alu.v
- rtl/serv_csr.v
- rtl/serv_ctrl.v
- rtl/serv_decode.v
- rtl/serv_immdec.v
- rtl/serv_mem_if.v
- rtl/serv_rf_if.v
- rtl/serv_rf_ram_if.v
- rtl/serv_rf_ram.v
- rtl/serv_state.v
- rtl/serv_debug.v
- rtl/serv_top.v
- rtl/serv_rf_top.v
- rtl/serv_aligner.v
- rtl/serv_compdec.v
file_type : verilogSource
openlane:
files:
- data/params.tcl : {file_type : tclSource}
- rtl/serv_synth_wrapper.v : {file_type : verilogSource}
targets:
default:
filesets : [core]
parameters :
- "is_toplevel? (ALIGN)"
- "is_toplevel? (COMPRESSED)"
- "is_toplevel? (MDU)"
- "is_toplevel? (PRE_REGISTER)"
- "is_toplevel? (RESET_STRATEGY)"
- RISCV_FORMAL
- SERV_CLEAR_RAM
- "is_toplevel? (WITH_CSR)"
toplevel : ["is_toplevel? (serv_rf_top)"]
lint:
default_tool : verilator
description: Run static code checks (linting)
filesets : [core]
tools:
verilator:
mode : lint-only
verilator_options:
- "-Wall"
toplevel : serv_rf_top
sky130:
default_tool : openlane
description: Create GDSII for SkyWater 130nm using OpenLANE
filesets : [core, openlane]
toplevel : serv_synth_wrapper
parameters:
MDU:
datatype : int
description: Enables interface for RISC-V standard M-extension
paramtype : vlogparam
PRE_REGISTER:
datatype : int
description : Register signals before or after the decoder
paramtype : vlogparam
RESET_STRATEGY:
datatype : str
paramtype : vlogparam
RISCV_FORMAL:
datatype : bool
paramtype : vlogdefine
SERV_CLEAR_RAM:
datatype : bool
paramtype : vlogdefine
WITH_CSR:
datatype : int
paramtype : vlogparam
COMPRESSED:
datatype : int
description : Enable/Disable the support for Compressed instructions
paramtype : vlogparam
ALIGN:
datatype : int
paramtype : vlogparam
description : Enable/Disable the support of misaligned instructions