TIMING README

How to use the timing analysis:

First you have to generate a ZUMA overlay with a specific architecture 
described by your zuma_config.py configuration. 
For this generation the parameter params.sdf have to be turned off.

Then you can integrated the overlay into your design 
and extract the timing information from it by generating to sdf files:
(We assume that your toplevel design have the name Top)

Generate the first sdf file where we get the routing delay information from:

>netgen -s 1  -pcf Top.pcf -sdf_anno true -sdf_path "netgen/par" \
-ne -insert_glbl true -insert_pp_buffers false -w \
-dir netgen/par -ofmt verilog -sim Top.ncd Top_no_buffer.v

The second sdf file where we read out the delay on a flipflop (port delay + Tshcko):

>netgen -s 1  -pcf Top.pcf -sdf_anno true -sdf_path "netgen/par" \
-ne -insert_glbl true -insert_pp_buffers true -w \
-dir netgen/par -ofmt verilog -sim Top.ncd Top_with_buffer.v

Then copy the files Top_with_buffer.sdf and Top_no_buffer.sdf 
to your zuma/example directory and edit the parameters 
params.sdfFileName and params.sdfFlipflopFileName of your configuration.
Also you have to turn on the params.sdf flag and edit the instance parameter.

After that you can run the zuma compile.sh script with a circuit 
to get the critical path.
It will be printed on the command line.