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A fast RISC-V emulator based on the RISC-V Sail model

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Fast RISC-V Sail emulation using PyPy/RPython's JIT compiler

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This repository contains Pydrofoil, an experimental emulator for RISC-V based on the Sail RISC-V ISA model. It achieves fast performance by doing dynamic binary translation (aka just-in-time compilation) from RISC-V guest instructions into host machine instructions. It's built on top of the RPython meta-jit compiler and reuses all its optimizations, backends, etc. The emulator is complete enough to boot (an old version of) Linux up to the login prompt.

It also contains an even more experimental emulator for Aarch64 version 9.4, based on the Sail ARM ISA model, which is itself automatically generated from the ASL code that ARM provides. Booting Linux on that emulator is possible, but due to a bug in the Sail model it crashes when starting the init process.

See https://docs.pydrofoil.org for the complete documentation

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  • Python 86.2%
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