From f3a240d2495d920301012b7f31d2efa292e5e4d2 Mon Sep 17 00:00:00 2001 From: Tony Date: Fri, 26 Mar 2021 15:15:15 +0100 Subject: [PATCH 1/5] Added compatibility for RFM7X and bk242x-style nRF24 clones including example --- RF24.cpp | 19 + RF24_config.h | 4 + examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp | 891 ++++++++++++++++++ examples/rfm7xAndBk242xCompatiblity/rfm7x.h | 692 ++++++++++++++ .../rfm7xAndBk242xCompatiblity.ino | 168 ++++ .../rfm7xAndBk242xCompatiblity/rfm7x_config.h | 500 ++++++++++ .../rfm7x_hardware.cpp | 177 ++++ .../rfm7x_hardware.h | 65 ++ 8 files changed, 2516 insertions(+) create mode 100644 examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp create mode 100644 examples/rfm7xAndBk242xCompatiblity/rfm7x.h create mode 100644 examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino create mode 100644 examples/rfm7xAndBk242xCompatiblity/rfm7x_config.h create mode 100644 examples/rfm7xAndBk242xCompatiblity/rfm7x_hardware.cpp create mode 100644 examples/rfm7xAndBk242xCompatiblity/rfm7x_hardware.h diff --git a/RF24.cpp b/RF24.cpp index 94ab708eb..4b81cf9ec 100644 --- a/RF24.cpp +++ b/RF24.cpp @@ -1065,7 +1065,17 @@ bool RF24::txStandBy() #if defined(FAILURE_HANDLING) || defined(RF24_LINUX) uint32_t timeout = millis(); #endif + +#if defined(RF24_COMPATIBILITY_MODE_FOR_RFM7X_BK242X) + while (!((read_register(FIFO_STATUS)) & _BV(TX_EMPTY)) || !(status & _BV(TX_DS))) { //rfm75 might set TX_EMPTY although a packet is in transmission + if (status & _BV(TX_DS)) { //at least one packet has been sent + if (!(read_register(FIFO_STATUS) & _BV(TX_EMPTY))) { //check fifo again, because rfm75 might set tx_empty although packet in transmission + write_register(NRF_STATUS, _BV(TX_DS)); //this is not the last payload, so clear data sent flag + } + } +#else while (!(read_register(FIFO_STATUS) & _BV(TX_EMPTY))) { +#endif if (status & _BV(MAX_RT)) { write_register(NRF_STATUS, _BV(MAX_RT)); ce(LOW); @@ -1097,7 +1107,16 @@ bool RF24::txStandBy(uint32_t timeout, bool startTx) } uint32_t start = millis(); +#if defined(RF24_COMPATIBILITY_MODE_FOR_RFM7X_BK242X) + while (!((read_register(FIFO_STATUS)) & _BV(TX_EMPTY)) || !(status & _BV(TX_DS))) { //rfm75 might set TX_EMPTY although a packet is in transmission + if (status & _BV(TX_DS)) { //at least one packet has been sent + if (!(read_register(FIFO_STATUS) & _BV(TX_EMPTY))) { //check fifo again, because rfm75 might set tx_empty although packet in transmission + write_register(NRF_STATUS, _BV(TX_DS)); //this is not the last payload, so clear data sent flag + } + } +#else while (!(read_register(FIFO_STATUS) & _BV(TX_EMPTY))) { +#endif if (status & _BV(MAX_RT)) { write_register(NRF_STATUS, _BV(MAX_RT)); ce(LOW); // Set re-transmit diff --git a/RF24_config.h b/RF24_config.h index 361e70486..0c8eadf25 100644 --- a/RF24_config.h +++ b/RF24_config.h @@ -25,6 +25,10 @@ //#define SPI_UART // Requires library from https://github.com/TMRh20/Sketches/tree/master/SPI_UART //#define SOFTSPI // Requires library from https://github.com/greiman/DigitalIO +//This introduces some changes to make the library work with RFM73/75 and other bk242x derivates. See examples/rfm7xAndBk242xCompatiblity +//Those modules require additional initialization which can be done with https://github.com/jnk0le/RFM7x-lib +//#define RF24_COMPATIBILITY_MODE_FOR_RFM7X_BK242X + /** * User access to internally used delay time (in microseconds) during RF24::powerUp() * @warning This default value compensates for all supported hardware. Only adjust this if you diff --git a/examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp b/examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp new file mode 100644 index 000000000..e11b0db63 --- /dev/null +++ b/examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp @@ -0,0 +1,891 @@ +//************************************************************** +//Compiler : GCC +//Author : jnk0le@hotmail.com +// https://github.com/jnk0le +//License : MIT +//************************************************************** + +#if defined(__AVR_ARCH__) + #include + #include + #include + #include + + #define CRITICAL_SECTION ATOMIC_BLOCK(ATOMIC_RESTORESTATE) + +#else + #include + + // workaround for ATOMIC_BLOCK + __attribute__((always_inline)) + inline int __int_disable_irq(void) + { + int primask; + asm volatile("mrs %0, PRIMASK\n" : "=r"(primask)); + asm volatile("cpsid i\n"); + return primask & 1; + } + + __attribute__((always_inline)) + inline void __int_restore_irq(int *primask) + { + if (!(*primask)) + { + asm volatile ("" ::: "memory"); + asm volatile("cpsie i\n"); + } + } + + #define CRITICAL_SECTION for(int primask_save __attribute__((__cleanup__(__int_restore_irq))) = __int_disable_irq(), __ToDo = 1; __ToDo; __ToDo = 0) + +#endif + +#include +#include +#include "rfm7x.h" + +#if defined(__AVR_ARCH__)&&!defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) + const __flash uint8_t rfm7x_init_struct[] = +#else + const uint8_t rfm7x_init_struct[] = // generic for all architectures // table will be placed in SRAM if your mcu doesn't have unified memory space (flash + ram) +#endif + { + ////////////////////////////////////////// bank 1 initialization registers ////////////////////////////////////////// + + RFM7x_BANK1_REG0, + RFM7x_BANK1_REG1, + RFM7x_BANK1_REG2, + RFM7x_BANK1_REG3, + RFM7x_BANK1_REG4, + RFM7x_BANK1_REG5, + RFM7x_BANK1_REG6, + RFM7x_BANK1_REG7, + RFM7x_BANK1_REG8, + RFM7x_BANK1_REG9, + RFM7x_BANK1_REGA, + RFM7x_BANK1_REGB, + RFM7x_BANK1_REGC, + RFM7x_BANK1_REGD, + RFM7x_BANK1_RAMP_CURVE, + + ////////////////////////////////////////// bank 0 initialization registers ////////////////////////////////////////// +#ifndef RFM7x_DO_NOT_INITIALIZE_BANK0 + RFM7x_BANK0_REG_CONFIG, // PTX/PRX mode - doesn't care, it will be set later with rest commands + RFM7x_BANK0_REG_EN_AA, + RFM7x_BANK0_REG_EN_RXADDR, + RFM7x_BANK0_REG_SETUP_AW, + RFM7x_BANK0_REG_SETUP_RETR, + RFM7x_BANK0_REG_RF_CH, + RFM7x_BANK0_REG_RF_SETUP, + + RFM7x_BANK0_REG_STATUS, // status register that have to be initialized - not documented + RFM7x_BANK0_REG_OBSERVE_TX, // status register that have to be initialized - not documented + RFM7x_BANK0_REG_CD, // status register that have to be initialized - not documented + + #ifndef RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS + 0xE7, // pipe0 default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined + 0xC2, // pipe1 default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined + + RFM7x_PIPE2_RX_ADDRESS, // pipe 2 address // LSB only + RFM7x_PIPE3_RX_ADDRESS, // pipe 3 address // LSB only + RFM7x_PIPE4_RX_ADDRESS, // pipe 4 address // LSB only + RFM7x_PIPE5_RX_ADDRESS, // pipe 5 address // LSB only + #endif + + #if !defined(RFM7x_DO_NOT_INITIALIZE_RX_PAYLOAD_LEN_REGS)&&!defined(RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS) + 0xE7, // TX default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined + + RFM7x_PIPE0_RX_PAYLOAD_LEN, // pipe 0 - payload length // 0 equals to dynamic payload ?? + RFM7x_PIPE1_RX_PAYLOAD_LEN, // pipe 1 - payload length // 0 equals to dynamic payload ?? + RFM7x_PIPE2_RX_PAYLOAD_LEN, // pipe 2 - payload length // 0 equals to dynamic payload ?? + RFM7x_PIPE3_RX_PAYLOAD_LEN, // pipe 3 - payload length // 0 equals to dynamic payload ?? + RFM7x_PIPE4_RX_PAYLOAD_LEN, // pipe 4 - payload length // 0 equals to dynamic payload ?? + RFM7x_PIPE5_RX_PAYLOAD_LEN, // pipe 5 - payload length // 0 equals to dynamic payload ?? + + RFM7x_BANK0_REG_FIFO_STATUS, // status register that have to be initialized - not documented + #endif + + //0x00, // dummy + //0x00, // dummy + //0x00, // dummy + //0x00, // dummy + + //RFM7x_BANK0_REG_DYNPD, + //RFM7x_BANK0_REG_FEATURE, + + #if defined(RFM7x_TX_ADDRESS)&&!defined(RFM7x_USE_PIPE0_ADDRESS_FOR_TX_ADDRESS) + RFM7x_TX_ADDRESS, + #endif + #ifdef RFM7x_PIPE0_RX_ADDRESS + RFM7x_PIPE0_RX_ADDRESS, + #endif + #ifdef RFM7x_PIPE1_RX_ADDRESS + RFM7x_PIPE1_RX_ADDRESS, + #endif + +#endif //RFM7x_DO_NOT_INITIALIZE_BANK0 + }; + + void rfm7x_init(void) + { + #ifdef RFM7x_ATOMIC_REG_ACCES + CRITICAL_SECTION + #endif + { + #if defined(__AVR_ARCH__)&&!defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) + const __flash uint8_t *p_init_struct = rfm7x_init_struct; + #else + const uint8_t *p_init_struct = rfm7x_init_struct; + #endif + + if((0x80 & rfm7x_reg_read(RFM7x_REG_STATUS)) == 0) + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // select bank 1 + + for(uint_fast8_t i=0; i rfm75 migration) says that it should be executed after every PWR_UP, not only during initialization + + // 4. RFM75 PowerUP after the first packet of data sent unsuccessful solution + // RFM75 from the POWER DOWN state to switch to POWER UP state, send the first packet is not successful, the reason + // Is the PLL is not locked, the solution is as follows: + // Before transmitting data normally, please follow the following procedure: + // Power up = 1 + // Wait for 2ms + // Operate the bank1 register, writing a 1 to bit 25 of register 04 + // Wait 20us + // Operate the bank1 register, writing a 0 to bit 25 of register 04 + // Wait for 0.5ms. + // Then normal launch. + + // AN0008 + // 9. Toggle REG4<25?26>, write 1 to bit25, bit 26, then write 0 to them. + + #ifdef RFM7x_ATOMIC_REG_ACCES + CRITICAL_SECTION + #endif + { + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 + + #if defined(__AVR_ARCH__)&&!defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) + rfm7x_reg_buff_write_P(0x04,rfm7x_REG4_toggle_struct,4); + _delay_us(20); // if not required then this function may not be required, so better to leave it here + rfm7x_reg_buff_write_P(0x04,&rfm7x_init_struct[16],4); + #else + rfm7x_reg_buff_write(0x04,(uint8_t*)rfm7x_REG4_toggle_struct,4); + //_delay_us(20); // if not required then this function may not be required, so better to leave it here + rfm7x_reg_buff_write(0x04,(uint8_t*)&rfm7x_init_struct[16],4); + #endif + + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 + } + } + + void rfm7x_cmd_write(uint8_t reg, uint8_t dat) + { + #ifdef RFM7x_ATOMIC_REG_ACCES + CRITICAL_SECTION + #endif + { + RFM7x_CSN_LOW; + rfm7x_spi_rw(reg); + rfm7x_spi_rw(dat); + RFM7x_CSN_HI; + } + } + + uint8_t rfm7x_cmd_read(uint8_t reg) + { + uint8_t tmp; + + #ifdef RFM7x_ATOMIC_REG_ACCES + CRITICAL_SECTION + #endif + { + RFM7x_CSN_LOW; + rfm7x_spi_rw(reg); + tmp = rfm7x_spi_rw(0); // rfm7x_spi_rw(rfm7x_spi_rw()) + RFM7x_CSN_HI; + } + + return tmp; + } + +#ifdef RFM7x_USE_UNIVERSAL_SPI_BUFF_RW_FUNCTIONS + void rfm7x_cmd_buff_write(uint8_t reg, uint8_t *buff, uint8_t len) + { + #ifdef RFM7x_ATOMIC_REG_ACCES + CRITICAL_SECTION + #endif + { + RFM7x_CSN_LOW; + rfm7x_spi_rw(reg); + rfm7x_buff_write(buff, len); + RFM7x_CSN_HI; + } + } + + void rfm7x_cmd_buff_read(uint8_t reg, uint8_t *buff, uint8_t len) + { + #ifdef RFM7x_ATOMIC_REG_ACCES + CRITICAL_SECTION + #endif + { + RFM7x_CSN_LOW; + rfm7x_spi_rw(reg); + rfm7x_buff_read(buff, len); + RFM7x_CSN_HI; + } + } +#else + void rfm7x_cmd_buff_write(uint8_t reg, uint8_t *buff, uint8_t len) + { + #ifdef RFM7x_ATOMIC_REG_ACCES + CRITICAL_SECTION + #endif + { + RFM7x_CSN_LOW; + + rfm7x_spi_rw(reg); + + for(uint_fast8_t i=0; i> 2) << 4); // to optimize ? + rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); + + #endif + } + + void rfm7x_set_lna_gain(uint8_t enable) + { + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); + + if(enable) + tmp |= RFM7x_RF_SETUP_LNA_HCURR; + else + tmp &= ~(RFM7x_RF_SETUP_LNA_HCURR); + + rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); + } + + void rfm7x_set_datarate(uint8_t datarate) + { + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); + + #if (RFM7x_MODULECHIP_USED == 0)|(RFM7x_MODULECHIP_USED == 1)|(RFM7x_MODULECHIP_USED == 4)|(RFM7x_MODULECHIP_USED == 5) // bk2401/bk2421/bk2411/bk2412/bk5811 + tmp &= ~(RFM7x_RF_SETUP_RF_DR_HIGH); + + if(datarate & 0x01) + tmp |= RFM7x_RF_SETUP_RF_DR_HIGH; + + //tmp |= ((datarate & 0x01) << 3); + #elif (RFM7x_MODULECHIP_USED == 2)|(RFM7x_MODULECHIP_USED == 3) // bk2423/bk2425 + tmp &= ~(RFM7x_RF_SETUP_RF_DR_HIGH|RFM7x_RF_SETUP_RF_DR_LOW); + + if(datarate & 0x01) + tmp |= RFM7x_RF_SETUP_RF_DR_HIGH; + + if(datarate & 0x02) + tmp |= RFM7x_RF_SETUP_RF_DR_LOW; + + //tmp |= ((datarate & 0x01) << 3)|(((datarate >> 1) & 0x01) << 5); + #endif + + rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); + } + +#if (RFM7x_MODULECHIP_USED == 4)||(RFM7x_MODULECHIP_USED == 5) + void rfm7x_enable_rssi_measurements(uint8_t enable) + { + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); + + if(enable) + tmp |= RFM7x_RF_SETUP_RSSI_EN; + else + tmp &= ~(RFM7x_RF_SETUP_RSSI_EN); + + rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); + } +#endif + +#if (RFM7x_MODULECHIP_USED == 4) + void rfm7x_dreg_enable(uint8_t enable) + { + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); + + if(enable) + tmp |= BK2411_RF_SETUP_DREG_ON; + else + tmp &= ~(BK2411_RF_SETUP_DREG_ON); + + rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); + } +#endif + + void rfm7x_enable_pipe_autoack(uint8_t pipe, uint8_t enabled) + { + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_EN_AA); + + tmp &= ~(1 << pipe); + + if(enabled) + tmp |= (1 << pipe); + + rfm7x_reg_write(RFM7x_REG_EN_AA, tmp); + } + + void rfm7x_enable_pipe_receive(uint8_t pipe, uint8_t enabled) + { + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_EN_RXADDR); + + tmp &= ~(1 << pipe); + + if(enabled) + tmp |= (1 << pipe); + + rfm7x_reg_write(RFM7x_REG_EN_RXADDR, tmp); + } + + void rfm7x_enable_dynamic_payload_feature(uint8_t enable) + { + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); + + tmp &= ~(RFM7x_FEATURE_EN_DPL); + + if(enable) + tmp |= RFM7x_FEATURE_EN_DPL; + + rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); + } + + void rfm7x_enable_ack_payload_feature(uint8_t enable) + { + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); + + tmp &= ~(RFM7x_FEATURE_EN_ACK_PAY); + + if(enable) + tmp |= RFM7x_FEATURE_EN_ACK_PAY; + + rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); + } + + void rfm7x_enable_noack_payload_feature(uint8_t enable) + { + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); + + tmp &= ~(RFM7x_FEATURE_EN_DYN_ACK); + + if(enable) + tmp |= RFM7x_FEATURE_EN_DYN_ACK; + + rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); + } + + void rfm7x_set_transmit_address(uint8_t* addr) + { + uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); + size += 2; + rfm7x_reg_buff_write(RFM7x_REG_TX_ADDR, addr, size); + } + + void rfm7x_open_writing_pipe(uint64_t addr) + { + uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); + size += 2; + + //initialize also RX0 ? + rfm7x_reg_buff_write(RFM7x_REG_TX_ADDR, (uint8_t *)&addr, size); // just push that onto the stack, forget about shifts + } + + //pipe 1 and 2 (??) + void rfm7x_set_receive_address(uint8_t pipe, uint8_t* addr) + { + uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); + size += 2; + rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P0+pipe, addr, size); + } + + void rfm7x_open_reading_pipe(uint8_t pipe, uint64_t addr) + { + rfm7x_enable_pipe_receive(pipe, 1); + + if(pipe >= 2) + { + rfm7x_reg_write(RFM7x_REG_RX_ADDR_P0+pipe, (addr & 0xff)); + } + else + { + uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); + size += 2; + + rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P0+pipe, (uint8_t *)&addr, size); // just push that onto the stack, forget about shifts // LE archs only ? + } + } + +#if (RFM7x_MODULECHIP_USED == 5) + +#if defined(__AVR_ARCH__)&&!defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) + const __flash uint8_t rfm7x_swapbandtune_struct[] = +#else + const uint8_t rfm7x_swapbandtune_struct[] = // generic for all architectures // table will be placed in SRAM if your mcu doesn't have unified memory space (flash + ram) +#endif + { + #if (BK5811_BANK1_DEFAULT_BAND == 0) // 5.1GHz in rfm7x_init_struct + + 0x04, 0x05, 0x78, 0x32, // reg 0 + 0xC0, 0x05, 0xAE, 0x00, // reg 1 // dummy + 0xE8, 0x80, 0x0C, 0xD2, // reg 2 + 0x19, 0x0D, 0x7D, 0x6D // reg 3 + + #else //(BK5811_BANK1_DEFAULT_BAND == 1) // 5.8GHz in rfm7x_init_struct + + 0x04, 0x05, 0x78, 0x33, // reg 0 + 0xC0, 0x05, 0xAE, 0x00, // reg 1 // dummy + 0xE8, 0x80, 0x8C, 0xD3, // reg 2 + 0x18, 0x0D, 0x7D, 0x6C // reg 3 + #endif + }; + + void bk5811_set_frequency_band(uint8_t range) + { + #if defined(__AVR_ARCH__)&&!defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) + const __flash uint8_t *p_swapband_struct; + #else + const uint8_t *p_swapband_struct; + #endif + + #if (BK5811_BANK1_DEFAULT_BAND == 0) // 5.1GHz in rfm7x_init_struct + if(range) + p_swapband_struct = rfm7x_init_struct; + else + p_swapband_struct = rfm7x_swapbandtune_struct; + #else //(BK5811_BANK1_DEFAULT_BAND == 1) // 5.8GHz in rfm7x_init_struct + if(range) + p_swapband_struct = rfm7x_swapbandtune_struct; + else + p_swapband_struct = rfm7x_init_struct; + #endif + + #ifdef RFM7x_ATOMIC_REG_ACCES + CRITICAL_SECTION + #endif + { + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 + + for(uint_fast8_t i=0; i<4; i++) + { + #if defined(__AVR_ARCH__)&&!defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) + rfm7x_reg_buff_write_P(i,p_swapband_struct+i*4, 4); + #else + rfm7x_reg_buff_write(i,p_swapband_struct+i*4, 4); + #endif + } + + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 + } + + } +#endif diff --git a/examples/rfm7xAndBk242xCompatiblity/rfm7x.h b/examples/rfm7xAndBk242xCompatiblity/rfm7x.h new file mode 100644 index 000000000..543ec6455 --- /dev/null +++ b/examples/rfm7xAndBk242xCompatiblity/rfm7x.h @@ -0,0 +1,692 @@ +#ifndef RFM7x_H_ +#define RFM7x_H_ + +/************************************************************************************ + * Author: jnk0le@hotmail.com * + * https://github.com/jnk0le * + * This library is distributed under MIT license terms * + ************************************************************************************/ + +#include "rfm7x_config.h" +#include "rfm7x_hardware.h" + +#ifdef __cplusplus + extern "C" { +#endif + +#define RFM7x_CMD_READ_REG 0x00 +#define RFM7x_CMD_WRITE_REG 0x20 +#define RFM7x_CMD_R_RX_PAYLOAD 0x61 +#define RFM7x_CMD_W_TX_PAYLOAD 0xA0 +#define RFM7x_CMD_FLUSH_TX 0xE1 +#define RFM7x_CMD_FLUSH_RX 0xE2 +#define RFM7x_CMD_REUSE_TX_PL 0xE3 +#define RFM7x_CMD_W_TX_PAYLOAD_NOACK 0xB0 +#define RFM7x_CMD_W_ACK_PAYLOAD 0xA8 +#define RFM7x_CMD_ACTIVATE 0x50 +#define RFM7x_CMD_R_RX_PL_WID 0x60 +#define RFM7x_CMD_NOP 0xFF + +#define RFM7x_REG_CONFIG 0x00 // 'Config' +#define RFM7x_REG_EN_AA 0x01 // 'Enable Auto Acknowledgment' +#define RFM7x_REG_EN_RXADDR 0x02 // 'Enabled RX addresses' +#define RFM7x_REG_SETUP_AW 0x03 // 'Setup address width' +#define RFM7x_REG_SETUP_RETR 0x04 // 'Setup Auto. Retrans' +#define RFM7x_REG_RF_CH 0x05 // 'RF channel' +#define RFM7x_REG_RF_SETUP 0x06 // 'RF setup' +#define RFM7x_REG_STATUS 0x07 // 'Status' +#define RFM7x_REG_OBSERVE_TX 0x08 // 'Observe TX' +#define RFM7x_REG_CD 0x09 // 'Carrier Detect' +#define RFM7x_REG_RX_ADDR_P0 0x0A // 'RX address pipe0' +#define RFM7x_REG_RX_ADDR_P1 0x0B // 'RX address pipe1' +#define RFM7x_REG_RX_ADDR_P2 0x0C // 'RX address pipe2' +#define RFM7x_REG_RX_ADDR_P3 0x0D // 'RX address pipe3' +#define RFM7x_REG_RX_ADDR_P4 0x0E // 'RX address pipe4' +#define RFM7x_REG_RX_ADDR_P5 0x0F // 'RX address pipe5' +#define RFM7x_REG_TX_ADDR 0x10 // 'TX address' +#define RFM7x_REG_RX_PW_P0 0x11 // 'RX payload width, pipe0' +#define RFM7x_REG_RX_PW_P1 0x12 // 'RX payload width, pipe1' +#define RFM7x_REG_RX_PW_P2 0x13 // 'RX payload width, pipe2' +#define RFM7x_REG_RX_PW_P3 0x14 // 'RX payload width, pipe3' +#define RFM7x_REG_RX_PW_P4 0x15 // 'RX payload width, pipe4' +#define RFM7x_REG_RX_PW_P5 0x16 // 'RX payload width, pipe5' +#define RFM7x_REG_FIFO_STATUS 0x17 // 'FIFO Status Register' +#define RFM7x_REG_DYNPD 0x1c // 'Enable dynamic payload length' +#define RFM7x_REG_FEATURE 0x1d // 'Feature' register address + +// Status Register +#define RFM7x_STATUS_IRQ_RX_DR 0x40 +#define RFM7x_STATUS_IRQ_TX_DS 0x20 +#define RFM7x_STATUS_IRQ_MAX_RT 0x10 +#define RFM7x_STATUS_IRQ_TX_FULL 0x01 +#define RFM7x_STATUS_RBANK 0x80 +#define RFM7x_STATUS_RX_PIPE_NUM 0x0E + +// FIFO Status Register +#define RFM7x_FIFO_STATUS_TX_REUSE 0x40 +#define RFM7x_FIFO_STATUS_TX_FULL 0x20 +#define RFM7x_FIFO_STATUS_TX_EMPTY 0x10 +#define RFM7x_FIFO_STATUS_RX_FULL 0x02 +#define RFM7x_FIFO_STATUS_RX_EMPTY 0x01 + +// Config Register +#define RFM7x_CONFIG_MASK_RX_DR 0x40 // Mask interrupt caused by RX_DR when 1 +#define RFM7x_CONFIG_MASK_TX_DS 0x20 // Mask interrupt caused by TX_DS when 1 +#define RFM7x_CONFIG_MASK_MAX_RT 0x10 // Mask interrupt caused by MAX_RT when 1 +#define RFM7x_CONFIG_EN_CRC 0x08 +#define RFM7x_CONFIG_CRCO 0x04 +#define RFM7x_CONFIG_POWER 0x02 // 1 - Power up ; 0 - Power down +#define RFM7x_CONFIG_PRIM_RX 0x01 // 1 - Receiver ; 0 - Transmitter + +//RF config register +#define RFM7x_RF_SETUP_LNA_HCURR 0x01 +#define RFM7x_RF_SETUP_RF_DR_HIGH 0x08 // not high +#define RFM7x_RF_SETUP_RF_DR_LOW 0x20 // and not low // doesn't exists in bk2421/bk2411 +#define RFM7x_RF_SETUP_PLL_LOCK 0x10 // doesn't exists in bk2421/bk2411 +#define BK2411_RF_SETUP_DREG_ON 0x20 // "Digital regulator can be shut down or not " +#define RFM7x_RF_SETUP_RSSI_EN 0x40 // bk2411/12/5811 only +//RF_PWR mask ?? + +//EN_AA +//EN_RXADDR +//SETUP_RETR +//OBSERVE_TX +//DYNPD + +// Feature Register +#define RFM7x_FEATURE_EN_DPL 0x04 +#define RFM7x_FEATURE_EN_ACK_PAY 0x02 +#define RFM7x_FEATURE_EN_DYN_ACK 0x01 + +////////////////////////////////////////////////////////////////// + +#define RFM7x_BANK0_REG_CONFIG ((RFM7x_BANK0_CONF_PWR_UP << 1)|(RFM7x_BANK0_CONF_CRCO << 2)|(RFM7x_BANK0_CONF_EN_CRC << 3)|(RFM7x_BANK0_CONF_MASK_MAX_RT << 4)|(RFM7x_BANK0_CONF_MASK_TX_DS << 5)|(RFM7x_BANK0_CONF_MASK_RX_DR << 6)) +#define RFM7x_BANK0_REG_EN_AA ((RFM7x_BANK0_CONF_ENAA_P0 << 0)|(RFM7x_BANK0_CONF_ENAA_P1 << 1)|(RFM7x_BANK0_CONF_ENAA_P2 << 2)|(RFM7x_BANK0_CONF_ENAA_P3 << 3)|(RFM7x_BANK0_CONF_ENAA_P4 << 4)|(RFM7x_BANK0_CONF_ENAA_P5 << 5)) +#define RFM7x_BANK0_REG_EN_RXADDR ((RFM7x_BANK0_CONF_ERX_P0 << 0)|(RFM7x_BANK0_CONF_ERX_P1 << 1)|(RFM7x_BANK0_CONF_ERX_P2 << 2)|(RFM7x_BANK0_CONF_ERX_P3 << 3)|(RFM7x_BANK0_CONF_ERX_P4 << 4)|(RFM7x_BANK0_CONF_ERX_P5 << 5)) +#define RFM7x_BANK0_REG_SETUP_AW ((RFM7x_BANK0_CONF_AW)) +#define RFM7x_BANK0_REG_SETUP_RETR ((RFM7x_BANK0_CONF_ARC)|(RFM7x_BANK0_CONF_ARD << 4)) +#define RFM7x_BANK0_REG_RF_CH (RFM7x_BANK0_CONF_RF_CH) + +#if (RFM7x_MODULECHIP_USED == 4) // bk2411, bk2412 + #define RFM7x_BANK0_REG_RF_SETUP ((RFM7x_BANK0_CONF_LNA_HCURR)|((RFM7x_BANK0_CONF_RF_PWR & 0x03) << 1)|((RFM7x_BANK0_CONF_RF_PWR >> 2) << 4)|(RFM7x_BANK0_CONF_RF_DR << 3)|(BK2411_BANK0_CONF_DREG_ON << 5)|(RFM7x_BANK0_CONF_RSSI_EN << 6)) +#elif (RFM7x_MODULECHIP_USED == 5) // bk5811 + #define RFM7x_BANK0_REG_RF_SETUP ((RFM7x_BANK0_CONF_LNA_HCURR)|((RFM7x_BANK0_CONF_RF_PWR & 0x03) << 1)|((RFM7x_BANK0_CONF_RF_PWR >> 2) << 4)|(RFM7x_BANK0_CONF_RF_DR << 3)|(RFM7x_BANK0_CONF_RSSI_EN << 6)) +#else + #define RFM7x_BANK0_REG_RF_SETUP ((RFM7x_BANK0_CONF_LNA_HCURR)|(RFM7x_BANK0_CONF_RF_PWR << 1)|((RFM7x_BANK0_CONF_RF_DR & 0x01) << 3)|((RFM7x_BANK0_CONF_RF_DR >> 1) << 5)) +#endif + +#define RFM7x_BANK0_REG_DYNPD ((RFM7x_BANK0_CONF_DPL_P0 << 0)|(RFM7x_BANK0_CONF_DPL_P1 << 1)|(RFM7x_BANK0_CONF_DPL_P2 << 2)|(RFM7x_BANK0_CONF_DPL_P3 << 3)|(RFM7x_BANK0_CONF_DPL_P4 << 4)|(RFM7x_BANK0_CONF_DPL_P5 << 5)) +#define RFM7x_BANK0_REG_FEATURE ((RFM7x_BANK0_CONF_EN_DYN_ACK)|(RFM7x_BANK0_CONF_EN_ACK_PAY << 1)|(RFM7x_BANK0_CONF_EN_DPL << 2)) + +#ifdef RFM7x_USE_PIPE0_ADDRESS_FOR_TX_ADDRESS + #ifdef RFM7x_TX_ADDRESS_SIZE + #undef RFM7x_TX_ADDRESS_SIZE + #endif + + #define RFM7x_TX_ADDRESS_SIZE RFM7x_PIPE0_RX_ADDRESS_SIZE +#endif + + #define RFM7x_BANK0_ENTRIES_BASE 10 + +#if !defined(RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS) + #define RFM7x_BANK0_ENTRIES_RX_ADDR 6 +#else + #define RFM7x_BANK0_ENTRIES_RX_ADDR 0 +#endif + +#if !defined(RFM7x_DO_NOT_INITIALIZE_RX_PAYLOAD_LEN_REGS)&&!defined(RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS) + #define RFM7x_BANK0_ENTRIES_RX_LEN 8 +#else + #define RFM7x_BANK0_ENTRIES_RX_LEN 0 +#endif + +#ifdef RFM7x_DO_NOT_INITIALIZE_BANK0 + #define RFM7x_BANK0_ENTRIES 0 +#else + #define RFM7x_BANK0_ENTRIES (RFM7x_BANK0_ENTRIES_BASE + RFM7x_BANK0_ENTRIES_RX_ADDR + RFM7x_BANK0_ENTRIES_RX_LEN) +#endif + +////////////////////////////////////////// bank 1 initialization registers ////////////////////////////////////////// +// datasheet values are given as little endian - LSB should be first +// "replacing" manual have big endian order - MSB should be first +// of course they are different and no one knows which ones are correct +// regs 0 to 8 are double reversed so MSB is written first // regs 9 to 14 are LSB first // reg 8 is also LSB first (when read) +// most of those registers are write only + +#define RFM7x_BANK1_ENTRIES 15 // including RAMP_CURVE + +#if (RFM7x_MODULECHIP_USED == 0 || RFM7x_MODULECHIP_USED == 1) // BK2421 aka RFM70 + BK2401 + + #define RFM7x_BANK1_REG0 0x40, 0x4B, 0x01, 0xE2 + #define RFM7x_BANK1_REG1 0xC0, 0x4B, 0x00, 0x00 + #define RFM7x_BANK1_REG2 0xD0, 0xFC, 0x8C, 0x02 + + #if (RFM70_BANK1_REG3_MODE == 0) + #define RFM7x_BANK1_REG3 0x99, 0x00, 0x39, 0x41 + #elif (RFM70_BANK1_REG3_MODE == 1) + #define RFM7x_BANK1_REG3 0xF9, 0x00, 0x39, 0x41 + #elif (RFM70_BANK1_REG3_MODE == 2) + #define RFM7x_BANK1_REG3 0x03, 0x00, 0x12, 0x00 + #endif + + #if (RFM70_BANK1_REG4_MODE == 0) + #define RFM7x_BANK1_REG4 0xD9, 0x8E|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x86, 0x0B + #elif (RFM70_BANK1_REG4_MODE == 1) + #define RFM7x_BANK1_REG4 0xC9, 0x8E|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x86, 0x0B + #elif (RFM70_BANK1_REG4_MODE == 2) + #define RFM7x_BANK1_REG4 0xF9, 0x8E|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x86, 0x0B + #elif (RFM70_BANK1_REG4_MODE == 3) + #define RFM7x_BANK1_REG4 0xB9, 0x8E|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x86, 0x0B + #elif (RFM70_BANK1_REG4_MODE == 4) + #define RFM7x_BANK1_REG4 0x09, 0x8E|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x86, 0x0B + #elif (RFM70_BANK1_REG4_MODE == 5) + #define RFM7x_BANK1_REG4 0xD9, 0x8E|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x86, 0x21 + #elif (RFM70_BANK1_REG4_MODE == 6) + #define RFM7x_BANK1_REG4 0xD9, 0x86|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x82, 0x1B + #elif (RFM70_BANK1_REG4_MODE == 7) + #define RFM7x_BANK1_REG4 0xF9, 0x8E|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x84, 0x0B + #elif (RFM70_BANK1_REG4_MODE == 8) + #define RFM7x_BANK1_REG4 0xF9, 0x86|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x84, 0x1B + #elif (RFM70_BANK1_REG4_MODE == 9) + #define RFM7x_BANK1_REG4 0xF9, 0x86|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x80, 0x1B + #elif (RFM70_BANK1_REG4_MODE == 10) + #define RFM7x_BANK1_REG4 0xF9, 0x86|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x82, 0x1B + #elif (RFM70_BANK1_REG4_MODE == 11) + #define RFM7x_BANK1_REG4 0xC1, 0x8E|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x9A, 0x0B + #endif + + #if (RFM70_BANK1_REG5_MODE == 0) + #define RFM7x_BANK1_REG5 0x24, 0x06, 0x7F, 0xA6 + #elif (RFM70_BANK1_REG5_MODE == 1) + #define RFM7x_BANK1_REG5 (RFM73_RSSI_THRESHOLD_LEVEL << 2), 0x02, 0x7F, 0xA6 + #endif + + #define RFM7x_BANK1_REG6 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REG7 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REG8 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REG9 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REGA 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REGB 0x00, 0x00, 0x00, 0x00 + + #if (RFM70_BANK1_REGC_MODE == 0) + #define RFM7x_BANK1_REGC 0x00, 0x12, 0x73, 0x00 + #elif (RFM70_BANK1_REGC_MODE == 1) + #define RFM7x_BANK1_REGC 0x00, 0x12, 0x73, 0x05 + #elif (RFM70_BANK1_REGC_MODE == 2) + #define RFM7x_BANK1_REGC 0x00, 0x1a, 0x73, 0x00 + #endif + + #if (RFM70_BANK1_REGD_MODE == 0) + #define RFM7x_BANK1_REGD 0x36, 0xB4, 0x80, 0x00 + #elif (RFM70_BANK1_REGD_MODE == 1) + #define RFM7x_BANK1_REGD 0x46, 0xB4, 0x80, 0x00 + #endif + + #if (RFM70_BANK1_RAMP_CURVE_MODE == 0) + #define RFM7x_BANK1_RAMP_CURVE 0x41, 0x20, 0x08, 0x04, 0x81, 0x20, 0xCF, 0xF7, 0xFE, 0xFF, 0xFF + #elif (RFM70_BANK1_RAMP_CURVE_MODE == 1) + #define RFM7x_BANK1_RAMP_CURVE 0x41, 0x10, 0x04, 0x82, 0x20, 0x08, 0x08, 0xF2, 0x7D, 0xEF, 0xFF + #endif + +#elif (RFM7x_MODULECHIP_USED == 2) // BK2423 aka RFM73 + + #define RFM7x_BANK1_REG0 0x40, 0x4B, 0x01, 0xE2 + #define RFM7x_BANK1_REG1 0xC0, 0x4B, 0x00, 0x00 + #define RFM7x_BANK1_REG2 0xD0, 0xFC, 0x8C, 0x02 + + #if (RFM73_BANK1_REG3_MODE == 0) + #define RFM7x_BANK1_REG3 0x99, 0x00, 0x39, 0x41 + #elif (RFM73_BANK1_REG3_MODE == 1) + #define RFM7x_BANK1_REG3 0xF9, 0x00, 0x39, 0x41 + #elif (RFM73_BANK1_REG3_MODE == 2) + #define RFM7x_BANK1_REG3 0x03, 0x00, 0x12, 0x00 + #endif + + #if (RFM73_BANK1_REG4_MODE == 0) + #define RFM7x_BANK1_REG4 0xD9, 0x8E|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x86, 0x0B + #elif (RFM73_BANK1_REG4_MODE == 1) + #define RFM7x_BANK1_REG4 0xD9, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x82, 0x1B + #elif (RFM73_BANK1_REG4_MODE == 2) + #define RFM7x_BANK1_REG4 0xF9, 0x8E|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x84, 0x0B + #elif (RFM73_BANK1_REG4_MODE == 3) + #define RFM7x_BANK1_REG4 0xD9, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x86, 0x1B + #elif (RFM73_BANK1_REG4_MODE == 4) + #define RFM7x_BANK1_REG4 0xF9, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x84, 0x1B + #elif (RFM73_BANK1_REG4_MODE == 5) + #define RFM7x_BANK1_REG4 0xF9, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x80, 0x1B + #elif (RFM73_BANK1_REG4_MODE == 6) + #define RFM7x_BANK1_REG4 0xD9, 0x8E|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x86, 0x21 + #elif (RFM73_BANK1_REG4_MODE == 7) + #define RFM7x_BANK1_REG4 0xF9, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x82, 0x1B + #elif (RFM73_BANK1_REG4_MODE == 8) + #define RFM7x_BANK1_REG4 0xF9, 0x8E|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x86, 0x0B + #elif (RFM73_BANK1_REG4_MODE == 9) + #define RFM7x_BANK1_REG4 0xB9, 0x8E|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x86, 0x0B + #elif (RFM73_BANK1_REG4_MODE == 10) + #define RFM7x_BANK1_REG4 0xB9, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x82, 0x1B + #elif (RFM73_BANK1_REG4_MODE == 11) + #define RFM7x_BANK1_REG4 0x09, 0x8E|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x86, 0x0B + #elif (RFM73_BANK1_REG4_MODE == 12) + #define RFM7x_BANK1_REG4 0x09, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x82, 0x1B + #elif (RFM73_BANK1_REG4_MODE == 13) + #define RFM7x_BANK1_REG4 0xC1, 0x8E|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x9A, 0x0B + #elif (RFM73_BANK1_REG4_MODE == 14) + #define RFM7x_BANK1_REG4 0xC1, 0x8E|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x9A, 0x1B + #elif (RFM73_BANK1_REG4_MODE == 15) + #define RFM7x_BANK1_REG4 0xC1, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x9A, 0x1B + #elif (RFM73_BANK1_REG4_MODE == 16) + #define RFM7x_BANK1_REG4 0xC1, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x9C, 0x1B + #elif (RFM73_BANK1_REG4_MODE == 17) + #define RFM7x_BANK1_REG4 0xC1, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x9E, 0x1B + #endif + + #if (RFM73_BANK1_REG5_MODE == 0) + #define RFM7x_BANK1_REG5 0x24, 0x06, 0x7F, 0xA6 + #elif (RFM73_BANK1_REG5_MODE == 1) + #define RFM7x_BANK1_REG5 (RFM73_RSSI_THRESHOLD_LEVEL << 2), 0x02, 0x7F, 0xA6 + #endif + + #define RFM7x_BANK1_REG6 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REG7 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REG8 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REG9 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REGA 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REGB 0x00, 0x00, 0x00, 0x00 + + #if (RFM73_BANK1_REGC_MODE == 0) + #define RFM7x_BANK1_REGC 0x00, 0x10|(RFM73_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x00 + #elif (RFM73_BANK1_REGC_MODE == 1) + #define RFM7x_BANK1_REGC 0x00, 0x10|(RFM73_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x05 + #elif (RFM73_BANK1_REGC_MODE == 2) + #define RFM7x_BANK1_REGC 0x00, 0x18|(RFM73_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x00 + #elif (RFM73_BANK1_REGC_MODE == 3) + #define RFM7x_BANK1_REGC 0x00, 0x18|(RFM73_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x05 + #endif + + #if (RFM73_BANK1_REGD_MODE == 0) + #define RFM7x_BANK1_REGD 0x36, 0xB4, 0x80, 0x00 + #elif (RFM73_BANK1_REGD_MODE == 1) + #define RFM7x_BANK1_REGD 0x46, 0xB4, 0x80, 0x00 + #endif + + #if (RFM73_BANK1_RAMP_CURVE_MODE == 0) + #define RFM7x_BANK1_RAMP_CURVE 0x41, 0x10, 0x04, 0x82, 0x20, 0x08, 0x08, 0xF2, 0x7D, 0xEF, 0xFF + #elif (RFM73_BANK1_RAMP_CURVE_MODE == 1) + #define RFM7x_BANK1_RAMP_CURVE 0x41, 0x20, 0x08, 0x04, 0x81, 0x20, 0xCF, 0xF7, 0xFE, 0xFF, 0xFF + #endif + +#elif (RFM7x_MODULECHIP_USED == 3) // bk2425 aka RFM75 + + #define RFM7x_BANK1_REG0 0x40, 0x4B, 0x01, 0xE2 + #define RFM7x_BANK1_REG1 0xC0, 0x4B, 0x00, 0x00 + #define RFM7x_BANK1_REG2 0xD0, 0xFC, 0x8C, 0x02 + + #if (RFM75_BANK1_REG3_MODE == 0) + #define RFM7x_BANK1_REG3 0x99, 0x00, 0x39, 0x21 + #elif (RFM75_BANK1_REG3_MODE == 1) + #define RFM7x_BANK1_REG3 0x03, 0x00, 0x12, 0x00 + #elif (RFM75_BANK1_REG3_MODE == 2) + #define RFM7x_BANK1_REG3 0xF9, 0x00, 0x39, 0x21 + #elif (RFM75_BANK1_REG3_MODE == 3) + #define RFM7x_BANK1_REG3 0x99, 0x00, 0x39, 0x41 + #elif (RFM75_BANK1_REG3_MODE == 4) + #define RFM7x_BANK1_REG3 0xF9, 0x00, 0x39, 0x41 + #endif + + #if (RFM75_BANK1_REG4_MODE == 0) + #define RFM7x_BANK1_REG4 0xC1|(RFM75_CONFIG_txIctrl << 3), 0x96|(RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x82, 0x1B + #elif (RFM75_BANK1_REG4_MODE == 1) + #define RFM7x_BANK1_REG4 0xC1|(RFM75_CONFIG_txIctrl << 3), 0x96|(RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x82, 0xDB + #elif (RFM75_BANK1_REG4_MODE == 2) + #define RFM7x_BANK1_REG4 0xC1|(RFM75_CONFIG_txIctrl << 3), 0x96|(RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x8A, 0xDB + #elif (RFM75_BANK1_REG4_MODE == 3) + #define RFM7x_BANK1_REG4 0xC1|(RFM75_CONFIG_txIctrl << 3), 0x96|(RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x82, 0x21 + #elif (RFM75_BANK1_REG4_MODE == 4) + #define RFM7x_BANK1_REG4 0xC1|(RFM75_CONFIG_txIctrl << 3), 0x96|(RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x80, 0x1B + #elif (RFM75_BANK1_REG4_MODE == 5) + #define RFM7x_BANK1_REG4 0xC1|(RFM75_CONFIG_txIctrl << 3), 0x96|(RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x80, 0xDB + #elif (RFM75_BANK1_REG4_MODE == 6) + #define RFM7x_BANK1_REG4 0xC1|(RFM75_CONFIG_txIctrl << 3), 0x96|(RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x88, 0xDB + #endif + + #if (RFM75_BANK1_REG5_MODE == 0) + #define RFM7x_BANK1_REG5 0x24, 0x06, 0x0F, 0xA6 + #elif (RFM75_BANK1_REG5_MODE == 1) + #define RFM7x_BANK1_REG5 0x24, 0x06, 0x0F, 0xB6 + #elif (RFM75_BANK1_REG5_MODE == 2) + #define RFM7x_BANK1_REG5 0x24, 0x02, 0x0F, 0xA6 + #elif (RFM75_BANK1_REG5_MODE == 3) + #define RFM7x_BANK1_REG5 0x24, 0x02, 0x0F, 0xB6 + #elif (RFM75_BANK1_REG5_MODE == 4) + #define RFM7x_BANK1_REG5 (RFM75_UNDOCUMENTED_RSSI_THRESHOLD_LEVEL << 2), 0x02, 0x0F, 0xA6 + #elif (RFM75_BANK1_REG5_MODE == 5) + #define RFM7x_BANK1_REG5 (RFM75_UNDOCUMENTED_RSSI_THRESHOLD_LEVEL << 2), 0x02, 0x0F, 0xB6 + #elif (RFM75_BANK1_REG5_MODE == 6) + #define RFM7x_BANK1_REG5 0x24, 0x06, 0x7F, 0xA6 + #elif (RFM75_BANK1_REG5_MODE == 7) + #define RFM7x_BANK1_REG5 0x24, 0x06, 0x7F, 0xB6 + #elif (RFM75_BANK1_REG5_MODE == 8) + #define RFM7x_BANK1_REG5 (RFM75_UNDOCUMENTED_RSSI_THRESHOLD_LEVEL << 2), 0x02, 0x7F, 0xA6 + #elif (RFM75_BANK1_REG5_MODE == 9) + #define RFM7x_BANK1_REG5 (RFM75_UNDOCUMENTED_RSSI_THRESHOLD_LEVEL << 2), 0x02, 0x7F, 0xB6 + #endif + + #define RFM7x_BANK1_REG6 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REG7 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REG8 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REG9 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REGA 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REGB 0x00, 0x00, 0x00, 0x00 + + #if (RFM75_BANK1_REGC_MODE == 0) + #define RFM7x_BANK1_REGC 0x00, 0x10|(RFM75_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x00 + #elif (RFM75_BANK1_REGC_MODE == 1) + #define RFM7x_BANK1_REGC 0x00, 0x10|(RFM75_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x05 + #elif (RFM75_BANK1_REGC_MODE == 2) + #define RFM7x_BANK1_REGC 0x00, 0x18|(RFM75_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x00 + #elif (RFM75_BANK1_REGC_MODE == 3) + #define RFM7x_BANK1_REGC 0x00, 0x18|(RFM75_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x05 + #endif + + #if (RFM75_BANK1_REGD_MODE == 0) + #define RFM7x_BANK1_REGD 0x36, 0xB4, 0x80, 0x00 + #elif (RFM75_BANK1_REGD_MODE == 1) + #define RFM7x_BANK1_REGD 0x46, 0xB4, 0x80, 0x00 + #endif + + #if (RFM75_BANK1_RAMP_CURVE_MODE == 0) + #define RFM7x_BANK1_RAMP_CURVE 0x41, 0x20, 0x08, 0x04, 0x81, 0x20, 0xCF, 0xF7, 0xFE, 0xFF, 0xFF + #elif (RFM75_BANK1_RAMP_CURVE_MODE == 1) + #define RFM7x_BANK1_RAMP_CURVE 0x41, 0x10, 0x04, 0x82, 0x20, 0x08, 0x08, 0xF2, 0x7D, 0xEF, 0xFF + #endif + +#elif (RFM7x_MODULECHIP_USED == 4) // bk2411/2412 + + #define RFM7x_BANK1_REG0 0x41, 0x4B, 0x01, 0xF2 + #define RFM7x_BANK1_REG1 0xC0, 0x4B, 0x06, 0x30 + #define RFM7x_BANK1_REG2 0xA0, 0xFC, 0xC4, 0x00 + + #if (BK2411_BANK1_REG3_MODE == 0) + #define RFM7x_BANK1_REG3 0x17, 0x00, 0x35, 0x60 + #elif (BK2411_BANK1_REG3_MODE == 1) + #define RFM7x_BANK1_REG3 0x03, 0x00, 0x12, 0x00 + #endif + + #if (BK2411_BANK1_REG4_MODE == 0) + #define RFM7x_BANK1_REG4 0x41, 0x99, 0x00, 0x0B + #elif (BK2411_BANK1_REG4_MODE == 1) + #define RFM7x_BANK1_REG4 0x41, 0x99, 0x10, 0x0B + #elif (BK2411_BANK1_REG4_MODE == 2) + #define RFM7x_BANK1_REG4 0x41, 0x11, 0x04, 0x21 + #elif (BK2411_BANK1_REG4_MODE == 3) + #define RFM7x_BANK1_REG4 0x41, 0x98|(BK2411_XTALFC >> 3), 0x00|(BK2411_XTALFC << 5), 0x0B + #elif (BK2411_BANK1_REG4_MODE == 4) + #define RFM7x_BANK1_REG4 0x41, 0x98|(BK2411_XTALFC >> 3), 0x10|(BK2411_XTALFC << 5), 0x0B + #elif (BK2411_BANK1_REG4_MODE == 5) + #define RFM7x_BANK1_REG4 0x41, 0x10|(BK2411_XTALFC >> 3), 0x04|(BK2411_XTALFC << 5), 0x21 + #endif + + #define RFM7x_BANK1_REG5 (BK2411_RSSI_THRESHOLD_LEVEL << 2), 0x01, 0x17, 0xBE + #define RFM7x_BANK1_REG6 0x00, 0x00, 0x40, 0x00 + #define RFM7x_BANK1_REG7 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REG8 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REG9 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REGA 0xF6, 0x4E, 0xF5, 0xF6 + #define RFM7x_BANK1_REGB 0x5C, 0x18, 0x51, 0xD6 + + #if (BK2411_BANK1_REGC_MODE == 0) + #define RFM7x_BANK1_REGC 0x40, 0x55, 0x00, 0x2D + #elif (BK2411_BANK1_REGC_MODE == 1) + #define RFM7x_BANK1_REGC 0x60, 0x50, 0x00, 0x2D + #elif (BK2411_BANK1_REGC_MODE == 2) + #define RFM7x_BANK1_REGC 0x00|(BK2411_TX_RAMP_SEL << 5), 0x50|(BK2411_TX_LOCK_SEL << 1)|(BK2411_TX_RAMP_SEL >> 3), 0x00, 0x2D + #endif + + #if (BK2411_BANK1_REGD_MODE == 0) + #define RFM7x_BANK1_REGD 0x00, 0x70, 0x00, 0x00 + #elif (BK2411_BANK1_REGD_MODE == 1) + #define RFM7x_BANK1_REGD 0x00, 0x04, 0x00, 0x00 + #elif (BK2411_BANK1_REGD_MODE == 2) + #define RFM7x_BANK1_REGD 0x00, 0x74, 0x00, 0x00 + #elif (BK2411_BANK1_REGD_MODE == 3) + #define RFM7x_BANK1_REGD 0xFF, 0x71, 0x00, 0x00 + #elif (BK2411_BANK1_REGD_MODE == 4) + #define RFM7x_BANK1_REGD 0xFF, 0x05, 0x00, 0x00 + #elif (BK2411_BANK1_REGD_MODE == 5) + #define RFM7x_BANK1_REGD 0xFF, 0x75, 0x00, 0x00 + #elif (BK2411_BANK1_REGD_MODE == 3) + #define RFM7x_BANK1_REGD (BK2411_LEN_LONG), (BK2411_LONG_PL)|(BK2411_GFSK_BT << 1)|(BK2411_MODU_MOD << 2)|(BK2411_CYST_ACCU <<4), 0x00, 0x00 + #endif + + #define RFM7x_BANK1_RAMP_CURVE 0x41, 0x10, 0x08, 0x82, 0x40, 0x10, 0x08, 0xF2, 0x7C, 0xEF, 0xCF + +#elif (RFM7x_MODULECHIP_USED == 5) // bk5811 + + #if (BK5811_BANK1_DEFAULT_BAND == 0) + #define RFM7x_BANK1_REG0 0x04, 0x05, 0x78, 0x33 + #elif (BK5811_BANK1_DEFAULT_BAND == 1) + #define RFM7x_BANK1_REG0 0x04, 0x05, 0x78, 0x32 + #endif + + #define RFM7x_BANK1_REG1 0xC0, 0x05, 0xAE, 0x00 + + #if (BK5811_BANK1_DEFAULT_BAND == 0) + #define RFM7x_BANK1_REG2 0xE8, 0x80, 0x8C, 0xD3 + #elif (BK5811_BANK1_DEFAULT_BAND == 1) + #define RFM7x_BANK1_REG2 0xE8, 0x80, 0x0C, 0xD2 + #endif + + #if (BK5811_BANK1_DEFAULT_BAND == 0) + #define RFM7x_BANK1_REG3 0x18, 0x0D, 0x7D, 0x6C + #elif (BK5811_BANK1_DEFAULT_BAND == 1) + #define RFM7x_BANK1_REG3 0x19, 0x0D, 0x7D, 0x6D + #endif + + #if (BK5811_BANK1_REG4_MODE == 0) + #define RFM7x_BANK1_REG4 0xE9, 0x8E, 0x82, 0x1B + #elif (BK5811_BANK1_REG4_MODE == 1) + #define RFM7x_BANK1_REG4 0xE9, 0x8E, 0x82, 0x21 + #endif + + #define RFM7x_BANK1_REG5 (BK5811_RSSI_THRESHOLD_LEVEL << 2), 0x10, 0xFF, 0xA6 + #define RFM7x_BANK1_REG6 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REG7 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REG8 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REG9 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REGA 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REGB 0x00, 0x00, 0x00, 0x00 + #define RFM7x_BANK1_REGC 0x00, 0x12, 0x73, 0x00 + #define RFM7x_BANK1_REGD 0x36, 0xB4, 0x80, 0x00 + + #define RFM7x_BANK1_RAMP_CURVE 0x41, 0x20, 0x08, 0x04, 0x81, 0x20, 0xCF, 0xF7, 0xFE, 0xFF, 0xFF +#endif + +////////////////////////////////////////////////////////////////// +//?????? +/*#if defined(RFM7x_TX_ADDRESS)&&defined(RFM7x_PIPE0_RX_ADDRESS)&&defined(RFM7x_PIPE1_RX_ADDRESS) + #define RFM7x_LONG_ADDR_ENTRIES 3 +#elif (defined(RFM7x_TX_ADDRESS)&&defined(RFM7x_PIPE0_RX_ADDRESS))||(defined(RFM7x_PIPE0_RX_ADDRESS)&&defined(RFM7x_PIPE1_RX_ADDRESS))||(defined(RFM7x_TX_ADDRESS)&&defined(RFM7x_PIPE1_RX_ADDRESS)) + #define RFM7x_LONG_ADDR_ENTRIES 2 +#elif defined(RFM7x_TX_ADDRESS)||defined(RFM7x_PIPE0_RX_ADDRESS)||defined(RFM7x_PIPE1_RX_ADDRESS) + #define RFM7x_LONG_ADDR_ENTRIES 1 +#else + #define RFM7x_LONG_ADDR_ENTRIES 0 +#endif*/ + +////////////////////////////////////////////////////////////////// + +void rfm7x_init(void); + +// one of the chinese AN's (rfm73 -> rfm75) says that it should be executed after every PWR_UP, not only during initialization +void rfm7x_toggle_reg4(void); // MIGHT NOT BE THE CASE FOR BK2411/BK2412/BK5811 + +#define rfm7x_reg_write(__reg,__dat) rfm7x_cmd_write(RFM7x_CMD_WRITE_REG|(__reg),__dat) +#define rfm7x_reg_read(__reg) rfm7x_cmd_read(RFM7x_CMD_READ_REG|(__reg)) + +void rfm7x_cmd_write(uint8_t reg, uint8_t dat); +uint8_t rfm7x_cmd_read(uint8_t reg); + +#define rfm7x_reg_buff_write(__reg,__buff,__len) rfm7x_cmd_buff_write(RFM7x_CMD_WRITE_REG|(__reg),__buff,__len) +#define rfm7x_reg_buff_read(__reg,__buff,__len) rfm7x_cmd_buff_read(RFM7x_CMD_READ_REG|(__reg),__buff,__len) + +void rfm7x_cmd_buff_write(uint8_t reg, uint8_t *buff, uint8_t len); +void rfm7x_cmd_buff_read(uint8_t reg, uint8_t *buff, uint8_t len); + +#if defined(__AVR_ARCH__)&&!defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) // temporary workaround ?? + #define rfm7x_reg_buff_write_P(__reg,__buff,__len) rfm7x_cmd_buff_write_P(RFM7x_CMD_WRITE_REG|(__reg),__buff,__len) + +#ifdef __cplusplus + void rfm7x_cmd_buff_write_P(uint8_t reg, const uint8_t* buff, uint8_t len); +#else + void rfm7x_cmd_buff_write_P(uint8_t reg, const __flash uint8_t* buff, uint8_t len); +#endif + +#endif + +uint8_t rfm7x_is_present(void); + +void rfm7x_power_up(void); +void rfm7x_power_down(void); // this function will not wait for finishing any ongoing transmission (results may be undefined) + +void rfm7x_mode_receive(void); +void rfm7x_mode_transmit(void); + +inline void rfm7x_mode_standby(void) { RFM7x_CE_LOW; } + +inline uint8_t rfm7x_tx_fifo_full(void) { return (rfm7x_reg_read(RFM7x_REG_FIFO_STATUS) & RFM7x_FIFO_STATUS_TX_FULL) != 0; } +inline uint8_t rfm7x_tx_fifo_empty(void) { return (rfm7x_reg_read(RFM7x_REG_FIFO_STATUS) & RFM7x_FIFO_STATUS_TX_EMPTY) != 0; } + +inline uint8_t rfm7x_rx_fifo_full(void) { return (rfm7x_reg_read(RFM7x_REG_FIFO_STATUS) & RFM7x_FIFO_STATUS_RX_FULL) != 0; } +inline uint8_t rfm7x_rx_fifo_empty(void) { return (rfm7x_reg_read(RFM7x_REG_FIFO_STATUS) & RFM7x_FIFO_STATUS_RX_EMPTY) != 0; } + +inline uint8_t rfm7x_receive_next_pipe(void) { return (rfm7x_reg_read(RFM7x_REG_STATUS) >> 1) & 0x07; } +inline uint8_t rfm7x_receive_next_length(void) { return rfm7x_cmd_read(RFM7x_CMD_R_RX_PL_WID); } + +uint8_t rfm7x_receive(uint8_t *buff); // returns received length // 0x00 - nothing received, or empty packet +void rfm7x_receive_nocheck(uint8_t *buff); + +uint8_t rfm7x_receive_p_(uint8_t *pipe, uint8_t *buff); // returns received length // 0x00 - nothing received +static inline uint8_t rfm7x_receive_p(uint8_t *buff, uint8_t *pipe) __attribute__((always_inline)); +static inline uint8_t rfm7x_receive_p(uint8_t *buff, uint8_t *pipe) { return rfm7x_receive_p_(pipe, buff); } + +inline void rfm7x_receive_nocheck_s(uint8_t *buff, uint8_t length) { rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, length); } +uint8_t rfm7x_receive_s(uint8_t *buff, uint8_t length); // returns number of received pipe // 0x07 - nothing received + +uint8_t rfm7x_receive_f(uint8_t *buff, uint8_t *pipe, uint8_t *length); + +inline void rfm7x_transmit(uint8_t *buff, uint8_t length) { rfm7x_cmd_buff_write(RFM7x_CMD_W_TX_PAYLOAD, buff, length); } +inline void rfm7x_transmit_noack(uint8_t *buff, uint8_t length) { rfm7x_cmd_buff_write(RFM7x_CMD_W_TX_PAYLOAD_NOACK, buff, length); } + +// used in RX mode // transmit message while ACK'ing received packet on selected pipe +inline void rfm7x_rx_ack_transmit(uint8_t pipe, uint8_t *buff, uint8_t length) { rfm7x_cmd_buff_write(RFM7x_CMD_W_ACK_PAYLOAD | pipe, buff, length); } + +//uint8_t rfm7x_available(uint8_t *pipe); // normal receive mode // +// reset irq flags?? + +void rfm7x_set_rssi_threshold_step(uint8_t level); // usually linear scale from 0 (-97/100dBm) to 15 (-67/70dBm) // bk2423 is also linearized by this function, some levels may be out of useable range (over -105dBm) +inline uint8_t rfm7x_read_CD(void) { return rfm7x_reg_read(RFM7x_REG_CD); } + +//config +inline void rfm7x_set_channel(uint8_t channel) { rfm7x_reg_write(RFM7x_REG_RF_CH, channel); } // 0-83 , 0-127 , clears MAX_RT counter +void rfm7x_set_crc_length(uint8_t len); + +//bk2421/bk2423 aka rfm70/73 +// 0 - -10 dBm +// 1 - -5 dBm +// 2 - 0 dBm +// 3 - 5 dBm + +//bk2425 aka rfm75 +// 0 - -25 dBm +// 1 - -18 dBm +// 2 - -12 dBm +// 3 - -7 dBm +// 4 - -1 dBm +// 5 - 4 dBm + +//bk2411/bk2412 +// 0 - -35 dBm +// 1 - -25 dBm +// 2 - -15 dBm +// 3 - -5 dBm +// 4 - -5 dBm +// 5 - -5 dBm +// 6 - 0 dBm +// 7 - 5 dBm + +//bk5811 +// 0 - -35 dBm +// 1 - -30 dBm +// 2 - -30 dBm +// 3 - -24 dBm +// 4 - -12 dBm +// 5 - -8 dBm +// 6 - -4 dBm +// 7 - 0 dBm +void rfm7x_set_tx_pwr(uint8_t level); +void rfm7x_set_lna_gain(uint8_t enable); + +// 0 - 1mbps +// 1 - 2mbps +// 2 - 250kbps // only 73/75 +// 3 - 2mbps // only 73/75 (treat as reserved) +void rfm7x_set_datarate(uint8_t datarate); + +#if (RFM7x_MODULECHIP_USED == 4)||(RFM7x_MODULECHIP_USED == 5) + void rfm7x_enable_rssi_measurements(uint8_t enable); +#endif + +#if (RFM7x_MODULECHIP_USED == 4) + //enable on-chip "digital regulator" + void rfm7x_dreg_enable(uint8_t enable); +#endif + +//250us steps +inline void rfm7x_set_retransmits(uint8_t retransmits, uint8_t delay) { rfm7x_reg_write(RFM7x_REG_SETUP_RETR, (retransmits)|(delay<<4)); } + +// 3 to 5 bytes (2 byte width is reserved) +inline void rfm7x_set_addres_width(uint8_t width) { rfm7x_reg_write(RFM7x_REG_SETUP_AW, width-2); } + +//0-32 +inline void rfm7x_set_rx_pyaload_size(uint8_t pipe, uint8_t size) { rfm7x_reg_write(RFM7x_REG_RX_PW_P0+pipe, size); } + +//void rfm7x_set_receiving_pipes(uint8_t mask); +//void rfm7x_set_autoack_pipes(uint8_t mask); +void rfm7x_enable_pipe_autoack(uint8_t pipe, uint8_t enabled); +void rfm7x_enable_pipe_receive(uint8_t pipe, uint8_t enabled); + +//feature +void rfm7x_enable_dynamic_payload_feature(uint8_t enable); +void rfm7x_enable_ack_payload_feature(uint8_t enable); +void rfm7x_enable_noack_payload_feature(uint8_t enable); + +// execute rfm7x_set_addres_width before (function reads AW from the chip) +//AVR: MSB LSB +// 0x 44 33 22 11 +void rfm7x_set_transmit_address(uint8_t* addr); // LSB first +void rfm7x_open_writing_pipe(uint64_t addr); + +//pipe 1 and 2 (??) +void rfm7x_set_receive_address(uint8_t pipe, uint8_t* addr); // LSB first +inline void rfm7x_set_receive_address_pn(uint8_t pipe, uint8_t LSB_addr) { rfm7x_reg_write(RFM7x_REG_RX_ADDR_P0+pipe, LSB_addr); } + +//all pipes +void rfm7x_open_reading_pipe(uint8_t pipe, uint64_t addr); + +//observe tx +// lost packet reset + +// irq ? +//status flags + +#if (RFM7x_MODULECHIP_USED == 5) + // 0: 5.1GHz band + // 1: 5.8GHz band + void bk5811_set_frequency_band(uint8_t range); +#endif + +#ifdef __cplusplus + } +#endif + +#endif /* RFM7x_H_ */ diff --git a/examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino b/examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino new file mode 100644 index 000000000..2544d7f5d --- /dev/null +++ b/examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino @@ -0,0 +1,168 @@ +/* + * See documentation at https://nRF24.github.io/RF24 + * See License information at root directory of this library + * Author: Brendan Doherty (2bndy5) + */ + +/** + * A simple example of sending data from 1 nRF24L01 transceiver to another. + * + * This example was written to be used on 2 devices acting as "nodes". + * Use the Serial Monitor to change each node's behavior. + */ +#include +#include "printf.h" +#include "RF24.h" + +// See https://github.com/jnk0le/RFM7x-lib +#include "rfm7x.h" + +// instantiate an object for the nRF24L01 transceiver +RF24 radio(7, 8); // using pin 7 for the CE pin, and pin 8 for the CSN pin + +// Let these addresses be used for the pair +uint8_t address[][6] = {"1Node", "2Node"}; +// It is very helpful to think of an address as a path instead of as +// an identifying device destination + +// to use different addresses on a pair of radios, we need a variable to +// uniquely identify which address this radio will use to transmit +bool radioNumber = 1; // 0 uses address[0] to transmit, 1 uses address[1] to transmit + +// Used to control whether this node is sending or receiving +bool role = false; // true = TX role, false = RX role + +// For this example, we'll be using a payload containing +// a single float number that will be incremented +// on every successful transmission +float payload = 0.0; + +void setup() { + + Serial.begin(115200); + while (!Serial) { + // some boards need to wait to ensure access to serial over USB + } + + // initialize the transceiver on the SPI bus + if (!radio.begin()) { + Serial.println(F("radio hardware is not responding!!")); + while (1) {} // hold in infinite loop + } + + rfm7x_io_init(); + spi_init(); + if (rfm7x_is_present()) { + Serial.println("RFM7X connected, initializing"); + //this code initializes the required registers for the clones. Especially bank1 + rfm7x_init(); + delay(2); + rfm7x_toggle_reg4(); + delay(1); + } + + // print example's introductory prompt + Serial.println(F("RF24/examples/rfm7xAndBk242xCompatiblity")); + + // To set the radioNumber via the Serial monitor on startup + Serial.println(F("Which radio is this? Enter '0' or '1'. Defaults to '0'")); + while (!Serial.available()) { + // wait for user input + } + char input = Serial.parseInt(); + radioNumber = input == 1; + Serial.print(F("radioNumber = ")); + Serial.println((int)radioNumber); + + // role variable is hardcoded to RX behavior, inform the user of this + Serial.println(F("*** PRESS 'T' to begin transmitting to the other node")); + + // Set the PA Level low to try preventing power supply related problems + // because these examples are likely run with nodes in close proximity to + // each other. + radio.setPALevel(RF24_PA_LOW); // RF24_PA_MAX is default. + + // save on transmission time by setting the radio to only transmit the + // number of bytes we need to transmit a float + radio.setPayloadSize(sizeof(payload)); // float datatype occupies 4 bytes + + // set the TX address of the RX node into the TX pipe + radio.openWritingPipe(address[radioNumber]); // always uses pipe 0 + + // set the RX address of the TX node into a RX pipe + radio.openReadingPipe(1, address[!radioNumber]); // using pipe 1 + + // additional setup specific to the node's role + if (role) { + radio.stopListening(); // put radio in TX mode + } else { + radio.startListening(); // put radio in RX mode + } + + // For debugging info + // printf_begin(); // needed only once for printing details + // radio.printDetails(); // (smaller) function that prints raw register values + // radio.printPrettyDetails(); // (larger) function that prints human readable data + +} // setup + +void loop() { + + if (role) { + // This device is a TX node + + unsigned long start_timer = micros(); // start the timer + bool report = radio.write(&payload, sizeof(float)); // transmit & save the report + unsigned long end_timer = micros(); // end the timer + + if (report) { + Serial.print(F("Transmission successful! ")); // payload was delivered + Serial.print(F("Time to transmit = ")); + Serial.print(end_timer - start_timer); // print the timer result + Serial.print(F(" us. Sent: ")); + Serial.println(payload); // print payload sent + payload += 0.01; // increment float payload + } else { + Serial.println(F("Transmission failed or timed out")); // payload was not delivered + } + + // to make this example readable in the serial monitor + delay(1000); // slow transmissions down by 1 second + + } else { + // This device is a RX node + + uint8_t pipe; + if (radio.available(&pipe)) { // is there a payload? get the pipe number that recieved it + uint8_t bytes = radio.getPayloadSize(); // get the size of the payload + radio.read(&payload, bytes); // fetch payload from FIFO + Serial.print(F("Received ")); + Serial.print(bytes); // print the size of the payload + Serial.print(F(" bytes on pipe ")); + Serial.print(pipe); // print the pipe number + Serial.print(F(": ")); + Serial.println(payload); // print the payload's value + } + } // role + + if (Serial.available()) { + // change the role via the serial monitor + + char c = toupper(Serial.read()); + if (c == 'T' && !role) { + // Become the TX node + + role = true; + Serial.println(F("*** CHANGING TO TRANSMIT ROLE -- PRESS 'R' TO SWITCH BACK")); + radio.stopListening(); + + } else if (c == 'R' && role) { + // Become the RX node + + role = false; + Serial.println(F("*** CHANGING TO RECEIVE ROLE -- PRESS 'T' TO SWITCH BACK")); + radio.startListening(); + } + } + +} // loop diff --git a/examples/rfm7xAndBk242xCompatiblity/rfm7x_config.h b/examples/rfm7xAndBk242xCompatiblity/rfm7x_config.h new file mode 100644 index 000000000..e4de069f0 --- /dev/null +++ b/examples/rfm7xAndBk242xCompatiblity/rfm7x_config.h @@ -0,0 +1,500 @@ +#ifndef RFM7X_CONFIG_H_ +#define RFM7X_CONFIG_H_ + +#define RFM7x_MODULECHIP_USED 3 +// 0 // BK2401 ??? // same as BK2421 without 2 mbps data-rate +// 1 // BK2421 aka RFM70 +// 2 // BK2423 aka RFM73 // usually full component COBs - (VDDPA path present) - mostly 0.6$ "power enhanced" mini-modules on aliexpress +// 3 // BK2425 aka RFM75 // pinout clearly suggests that, it is well known "COB-with-missing-components-module" nrf24l01+ fakes +// 4 // BK2411/BK2412 // those are especially designed as an nrf24L01 (without +) fake (green PCB with 5 row header), but none of them can be found // NOT TESTED +// 5 // BK5811 // 5.1/5.8GHz RF chip // NOT TESTED + +// bk2491 is probably a canceled chip, which name appears as a title of various number of datasheets +// bk2461 // bk2535 // bk2533 // undocumented SOC +// bk2433 // bk2451 // bk2452 // undocumented SOCs with usb +// bk5822/23 // 5.8GHz ASK transciever // used in ETC +// bk5933 // 5.1/5.8GHz undocumented SOC (usb ?) + +/*********************************************************************/ + +//#define RFM7x_USE_UNIVERSAL_SPI_BUFF_RW_FUNCTIONS // buff write and buff read // ?? // not complete +//#define RFM7x_ATOMIC_REG_ACCES // disable interrupts when CSN goes low to prevent race conditions with interrupts // just a global cli, can be prematured to disable only specific sources // not fully tested +//#define RFM7x_FLUSH_TX_AND_RX_WHILE_SWITCHING_MODES // probably may be required by ACK payloads (W_ACK_PAYLOAD command) // not fully tested +#define RFM7x_DO_NOT_INITIALIZE_BANK0 // do not initialize bank0 registers in case of using other libs to do so // 4 (read-only) status registers are still being initialized // addresses are also not initialized +#define RFM7x_USE_PIPE0_ADDRESS_FOR_TX_ADDRESS // initialize TX address with the data from PIPE0_RX_ADDRESS // those have to be the same in AUTO_ACK mode // RFM7x_TX_ADDRESS is ignored + +#define RFM7x_DO_NOT_INITIALIZE_RX_PAYLOAD_LEN_REGS // only 2 bytes gain on avr // by omiting initialization of pyload length registers and dummy bytes +#define RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS // only 8 bytes gain on avr // by omiting initialization of payload length, pipe 2-5 addr, and dummy bytes + +#define RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH // currently workaround rfm7x_reg_buff_write_P() function is used that might make bigger code in some cases + +/**************** hardcoded config of bank0 registers ****************/ + +//comment out to free space in init_struct // LSB byte is first +#define RFM7x_PIPE0_RX_ADDRESS 0x34, 0x43, 0x10, 0x10, 0x01 // have to be the same as TX_ADDRESS in order to communiacate in AUTO_ACK mode. +//#define RFM7x_PIPE1_RX_ADDRESS 0x11, 0x02, 0x03, 0x04, 0x05 +//#define RFM7x_TX_ADDRESS 0x34, 0x43, 0x10, 0x10, 0x01 // have to be the same as PIPE0_RX_ADDRESS in order to communiacate in AUTO_ACK mode. + +// do not comment out config below + +#define RFM7x_PIPE0_RX_ADDRESS_SIZE 5 +#define RFM7x_PIPE1_RX_ADDRESS_SIZE 5 +#define RFM7x_TX_ADDRESS_SIZE 5 +//size of the vectors above + +#define RFM7x_PIPE2_RX_ADDRESS 0xC3 +#define RFM7x_PIPE3_RX_ADDRESS 0xC4 +#define RFM7x_PIPE4_RX_ADDRESS 0xC5 +#define RFM7x_PIPE5_RX_ADDRESS 0xC6 +// for the rest pipes, 4 MSB bytes are the same as PIPE1 address +// not included if RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS is defined + +#define RFM7x_BANK0_CONF_PWR_UP 1 +// usually we want to power chip up during initialization +// in some rare cases (battery operated) it have to be initialized in PWR_DOWN just to save some power +// 1: POWER UP +// 0: POWER DOWN + +#define RFM7x_BANK0_CONF_EN_CRC 1 +// Enable CRC. Forced high if one of the bits in the EN_AA is high +// 0: CRC disabled +// 1: CRC enabled + +#define RFM7x_BANK0_CONF_CRCO 1 +// CRC encoding scheme +// '0' - 1 byte +// '1' - 2 bytes + +#define RFM7x_BANK0_CONF_MASK_RX_DR 1 +// Mask interrupt caused by RX_DR +// 1: Interrupt not reflected on the IRQ pin +// 0: Reflect RX_DR as active low interrupt on the IRQ pin + +#define RFM7x_BANK0_CONF_MASK_TX_DS 1 +// Mask interrupt caused by TX_DS +// 1: Interrupt not reflected on the IRQ pin +// 0: Reflect TX_DS as active low interrupt on the IRQ pin + +#define RFM7x_BANK0_CONF_MASK_MAX_RT 1 +// Mask interrupt caused by MAX_RT +// 1: Interrupt not reflected on the IRQ pin +// 0: Reflect MAX_RT as active low interrupt on the IRQ pin + +#define RFM7x_BANK0_CONF_ENAA_P0 1 +#define RFM7x_BANK0_CONF_ENAA_P1 1 +#define RFM7x_BANK0_CONF_ENAA_P2 1 +#define RFM7x_BANK0_CONF_ENAA_P3 1 +#define RFM7x_BANK0_CONF_ENAA_P4 1 +#define RFM7x_BANK0_CONF_ENAA_P5 1 +// Enable auto acknowledgement data pipe N +// If one of the pipes is cofigured into AA CRC is forced +// All have to disabled for no AA TX mode ???? + +#define RFM7x_BANK0_CONF_ERX_P0 1 +#define RFM7x_BANK0_CONF_ERX_P1 0 +#define RFM7x_BANK0_CONF_ERX_P2 0 +#define RFM7x_BANK0_CONF_ERX_P3 0 +#define RFM7x_BANK0_CONF_ERX_P4 0 +#define RFM7x_BANK0_CONF_ERX_P5 0 +// Enable data pipe N + +#define RFM7x_BANK0_CONF_AW 3 +// RX/TX Address field width +// 0 - Illegal +// 1 - 3 bytes +// 2 - 4 bytes +// 3 - 5 bytes +// LSB byte is used if address width is below 5 bytes + +#define RFM7x_BANK0_CONF_ARD 15 +// Auto Retransmission Delay (Delay defined from end of transmission to start of next transmission) +// according to nrf24l01+ datasheet ARD should be 500us or more if ACK payload mode is used (W_ACK_PAYLOAD command) +// 250kbps mode requires 500us retransmit delay even if ACK payload is not used but is activated +// 0 - Wait 250 us +// 1 - Wait 500 us +// 2 - Wait 750 us +// 15 - Wait 4000 us + +#define RFM7x_BANK0_CONF_ARC 15 +// Auto Retransmission Count +// 0 - Re-Transmit disabled +// 1 - Up to 1 Re-Transmission on fail of AA +// 15 - Up to 15 Re-Transmission on fail of AA + + +#define RFM7x_BANK0_CONF_RF_CH 10 +// select used frequency channel in 1 MHz steps (kb2411 starts at 2397, rest at 2400) +// beken and hoperf datasheets says about 83 channels available, but electrical specification (except bk2411) says about 127 channels + +#define RFM7x_BANK0_CONF_LNA_HCURR 1 +// Setup LNA gain +// 0:Low gain(20dB down) +// 1:High gain + +#define RFM7x_BANK0_CONF_RF_PWR 3 +//bk2421/bk2423 aka rfm70/73 +// 0 - -10 dBm +// 1 - -5 dBm +// 2 - 0 dBm +// 3 - 5 dBm + +//bk2425 aka rfm75 +// have to be set together with txIctrl in bank1 for exact power level, otherwise -1dBm(or undefined as usual) // user_guide_of_RF75 +// 3 - value for 4,-1 dBm power levels +// 2 - value for -7 dBm power level +// 1 - value for -12,-18 dBm power levels +// 0 - value for -18,-25 dBm power levels + +//bk2411/bk2412 +// one of the bits occupies 'PLL_LOCK' location +// 0 - -35 dBm +// 1 - -25 dBm +// 2 - -15 dBm +// 3 - -5 dBm +// 4 - -5 dBm +// 5 - -5 dBm +// 6 - 0 dBm +// 7 - 5 dBm + +//bk5811 +// 0 - -35 dBm +// 1 - -30 dBm +// 2 - -30 dBm +// 3 - -24 dBm +// 4 - -12 dBm +// 5 - -8 dBm +// 6 - -4 dBm +// 7 - 0 dBm + +#define RFM7x_BANK0_CONF_RF_DR 0 +//Air Data Rate +// 0 - 1Mbps +// 1 - 2Mbps +// 2 - 250Kbps // bk2423/bk2425 only +// 3 - 2Mbps // bk2423/bk2425 only + +#define RFM7x_BANK0_CONF_RSSI_EN 1 // bk2411, bk2412, bk5811 only // rest chips have this setting in bank1 +// Enable RSSI measurement +// 0: Disable +// 1: Enable + +#define BK2411_BANK0_CONF_DREG_ON 1 // bk2411 only +// Digital regulator can be shut down or not +// 0: Can be shut down in stand-by I mode +// 1: Always on in any state except power down + +#define RFM7x_PIPE0_RX_PAYLOAD_LEN 0 +#define RFM7x_PIPE1_RX_PAYLOAD_LEN 0 +#define RFM7x_PIPE2_RX_PAYLOAD_LEN 0 +#define RFM7x_PIPE3_RX_PAYLOAD_LEN 0 +#define RFM7x_PIPE4_RX_PAYLOAD_LEN 0 +#define RFM7x_PIPE5_RX_PAYLOAD_LEN 0 +// 0 == dynamic payload ??? // 1-32 == static payload length ?? + +#define RFM7x_BANK0_CONF_DPL_P5 1 +#define RFM7x_BANK0_CONF_DPL_P4 1 +#define RFM7x_BANK0_CONF_DPL_P3 1 +#define RFM7x_BANK0_CONF_DPL_P2 1 +#define RFM7x_BANK0_CONF_DPL_P1 1 +#define RFM7x_BANK0_CONF_DPL_P0 1 +// Enable dynamic payload length data pipe N (Requires EN_DPL and ENAA_PN) + +#define RFM7x_BANK0_CONF_EN_DYN_ACK 1 +// Enables the W_TX_PAYLOAD_NOACK command + +#define RFM7x_BANK0_CONF_EN_ACK_PAY 1 +// Enables Payload with ACK (W_ACK_PAYLOAD command) +// probably may need flushing RX and TX together while switching modes +// according to nrf24l01+ datasheet, 250kbps mode requires 500us retransmit delay even if ACK payload is not used + +#define RFM7x_BANK0_CONF_EN_DPL 1 +// Enables Dynamic Payload Length + +/*********************************************************************/ +// all changes below have to be followed by HARD reset of the module (unconnect power supply and short power rails), +// otherwise module can keep previous contents and work flawlessly long enough to waste you a 'few' hours for debugging when it stops working (going below 0.3V is still not enough) + +// magic values that have to be written into read-only status registers, otherwise chips will refuse to work after some time or a few power cycles + +#define RFM7x_BANK0_REG_STATUS 0x70 +// The default value that comes from all example codes (0x07) might be intended as a fix for hidden silicon bug, or just erratum from 0x70 that should clear all pending flags + +#define RFM7x_BANK0_REG_OBSERVE_TX 0x00 +#define RFM7x_BANK0_REG_CD 0x00 +#define RFM7x_BANK0_REG_FIFO_STATUS 0x00 + +/******** bk2421/01 aka RFM70 - compatibility and sensitivity *******/ + +#define RFM70_BANK1_REG3_MODE 1 +// 0 // default recommended value +// 1 // "In order to smooth the use of RF-2400PA" (Inhaos rebrand of bk2421 + PA) // also "high power mode" for rfm73 +// 2 // datasheet "reset value" + +#define RFM70_BANK1_REG4_MODE 0 +// 0 // recommended datasheet value +// 1 // probably not correct value from early datasheet (v0.4) +// 2 // (0) with (0xD9 -> 0xF9) // found in some codes/libs for rfm70/73 +// 3 // (0) with (0xD9 -> 0xB9) // probably it comes from the early example codes // doesn't work ??????? +// 4 // (0) with (0xD9 -> 0x09) // weird value that gave someone better range +// 5 // "single carrier mode" from datasheet - constant wave mode (after translation from chienglish) // instead of 'PLL_LOCK' ?? // testing purposes only +// 6 // NOT DOCUMENTED NOR TESTED // value for rfm73 in replace manual (rfm70->rfm73) +// 7 // NOT DOCUMENTED NOR TESTED // undocumented "high power mode" up to 15dBm (rfm73/bk2423) +// 8 // NOT DOCUMENTED NOR TESTED // (7) mixed with (6) - (0x0B -> 0x1B), (0x9E -> 0xB6) +// 9 // NOT DOCUMENTED NOR TESTED // (7) mixed with (6) - (0x0B -> 0x1B), (0xBE -> 0xB6), (0x84 -> 0x80) +// 10 // NOT DOCUMENTED NOR TESTED // (7) mixed with (6) - (0x0B -> 0x1B), (0xBE -> 0xB6), (0x84 -> 0x82) +// 11 // "In order to smooth the use of RF-2400PA" (Inhaos rebrand of bk2421 + PA) + +#define RFM70_CONFIG_UNDOCUMENTED_RX_SEN 0 +// Sensitivity in RX mode +// 0: Normal mode +// 1: High sensitivity mode(different CD detection values) // NOT DOCUMENTED NOR TESTED + +#define RFM70_CONFIG_TX_PWR 1 +// RF output power in TX mode: +// 0:Low power(-30dB down) +// 1:High power + +#define RFM70_BANK1_REG5_MODE 1 +// 0 // RSSI disabled +// 1 // RSSI enabled // consumes about 1 mA // bk2421 vs nRF24l01 guide + +#define RFM70_RSSI_THRESHOLD_LEVEL 9 // 0-15 +// 0: -97 dBm, 2 dB/step, 15: -67 dBm // datasheet and bk2421 vs nRF24l01 guide +// 2: -105 dBm, 2 dB/step (at least above 5) 15: -73 dBm // replace manual (rfm70->rfm73) +// who is correct ? + +#define RFM70_BANK1_REGC_MODE 0 +// 0 // default recommended value // 120 us PLL settling time +// 1 // NOT DOCUMENTED NOR TESTED // nrf24L01+ compatible mode from rfm73 // 130 us PLL settling time (may be 200us like in bk2411, or just not work) +// 2 // probably not correct value from early datasheet (v0.4) // also power-up value in rfm73 (70 not tested) + +#define RFM70_BANK1_REGD_MODE 0 +// 0 // recommended datasheet value +// 1 // NOT DOCUMENTED NOR TESTED // value for rfm73, from replace manual (rfm70->rfm73) // (bank1 is so documented that it might be obtained experimentally) + +#define RFM70_BANK1_RAMP_CURVE_MODE 0 +// 0 // rfm70/bk2421 // default recommended datasheet value +// 1 // NOT DOCUMENTED NOR TESTED // rfm73 datasheet and power-up value + +/********************************************************************/ + +/********** bk2423 aka RFM73 - compatibility and sensitivity ********/ + +#define RFM73_BANK1_REG3_MODE 0 +// 0 // default recommended value +// 1 // AN0007 "high power mode" 3-15dBm - may require additional low/band-pass filter for compliance with FCC rules // also "In order to smooth the use of RF-2400PA" (Inhaos rebrand of bk2421 + PA) +// 2 // datasheet "reset value" + +#define RFM73_BANK1_REG4_MODE 1 // literally the worst register - all datasheets/AN's have different "correct" values for this register +// 0 // rfm70/bk2421 and rfm73/bk2423 datasheet values // AN0007 and AN0008 "default setting of reg4" +// 1 // replace manual (rfm70->rfm73), also used in all libraries which are not plain conversion from rfm70 // is said to be 3 dB gain in 1MHz and required for proper operation at 2MHz +// 2 // AN0007 "high power mode" up to 15dBm // RF_PWR in bank 0 should be set to 5dBm // may require additional low/band-pass filter for compliance with FCC rules +// 3 // (0) mixed with (1) // only obvious parts - (0x0B -> 0x1B), (0xBE -> 0xB6) +// 4 // (2) mixed with (1) // only obvious parts - (0x0B -> 0x1B), (0xBE -> 0xB6) +// 5 // (2) mixed with (1) // clear also bit 10 - (0x0B -> 0x1B), (0xBE -> 0xB6), (0x84 -> 0x80) +// 6 // "single carrier mode" from datasheet - constant wave mode (after translation from chienglish) // instead of 'PLL_LOCK' ?? // testing purposes only +// 7 // (4) with (0x84 -> 0x82) +// 8 // (0) with (0xD9 -> 0xF9) // found in some codes/libs for rfm70/73 +// 9 // (0) with (0xD9 -> 0xB9) // probably it comes from the eary example codes // ??doesn't work on rfm70??? +// 10 // (1) with (0xD9 -> 0xB9) +// 11 // (0) with (0xD9 -> 0x09) // weird value for rfm70 that gave someone better range +// 12 // (11) mixed with (3) +// 13 // adapt rfm70 "In order to smooth the use of RF-2400PA" (Inhaos rebrand of bk2421 + PA) +// 14 // (13) mixed with (1) - (0x0B -> 0x1B) +// 15 // (13) mixed with (1) - (0x0B -> 0x1B), (0xBE -> 0xB6) +// 16 // (15) with - (0x9A -> 9C) +// 17 // (15) with - (0x9A -> 9E) + +#define RFM73_CONFIG_RX_SEN 1 +// Sensitivity in RX mode +// 0: Normal mode +// 1: High sensitivity mode(different CD detection values) + +#define RFM73_CONFIG_TX_PWR 1 +// RF output power in TX mode: +// 0:Low power(-30dB down) +// 1:Normal power + +#define RFM73_BANK1_REG5_MODE 1 +// 0 // RSSI disabled +// 1 // RSSI enabled + +#define RFM73_RSSI_THRESHOLD_LEVEL 9 // 0-15 +// in bk2423/rfm73 RSSI level is not linear to threshold level +// RSSI levels are different at 250k/1M and 2M air data rate +// refering to AN0007, high sense mode affects rssi levels, so the default level is in N/A region // actually not true + +#define RFM73_BANK1_REGC_MODE 1 +// 0 // rfm70/bk2421 compatible // 120 us PLL settling time +// 1 // nrf24L01+ compatible // 130 us PLL settling time +// 2 // initial value after power up // 120 us PLL settling time // not used/mentioned anywhere +// 3 // initial value after power up // 130 us PLL settling time // not used/mentioned anywhere + +#define RFM73_CONFIG_COMPATIBLE_MODE 1 +// transmitter and receiver have to use the same mode, otherwise transmitter is seeing 100% packet loss +// This field probably controls the inversion of NO_ACK bit in the air payload in DPL mode +// 0:Static compatible // SI24R1 compatible +// 1:Dynamic compatible // recommended default value + +#define RFM73_BANK1_REGD_MODE 1 +// 0 // rfm70/bk2421 and rfm73/bk2423 datasheet values, also initial value that can be read after module power-up +// 1 // replace manual (rfm70->rfm73), also used in all libraries which are not plain conversion from rfm70 // it is said to be 3 dB gain in 1MHz and required for proper operation at 2MHz + +#define RFM73_BANK1_RAMP_CURVE_MODE 1 +// 0 // value recommended in rfm73/bk2423 datasheets, also the initial value that can be read after module power-up +// 1 // value recommended in rfm70/bk2421 datasheets and replace manual (rfm70->rfm73), also used in all libraries + +/********************************************************************/ + +/********** bk2425 aka RFM75 - compatibility and sensitivity ********/ + +#define RFM75_BANK1_REG3_MODE 0 +// 0 // recommended bk2425/rfm75 value +// 1 // datasheet "reset value" +// 3 // NOT DOCUMENTED NOR TESTED // (0) with undocumented high power mode bits set // no high power ?? +// 4 // adapt rfm73 value from replace manual (rfm70->rfm73) +// 5 // NOT DOCUMENTED NOR TESTED // adapt rfm73 "high power" mode (AN0007) // NOT WORKING + +#define RFM75_BANK1_REG4_MODE 0 +// 0 // recommended value for 1Mbps +// 1 // recommended value for 2Mbps +// 2 // recommended value for 250kbps +// 3 // "single carrier mode" from datasheet - constant wave mode (after translation from chienglish) // instead of 'PLL_LOCK' ?? +// 4 // NOT DOCUMENTED NOR TESTED // (0) with adapted rfm73 "high power" mode (AN0007) // clear undocumented bit 9 // no high power ?? +// 5 // NOT DOCUMENTED NOR TESTED // (1) with adapted rfm73 "high power" mode (AN0007) // clear undocumented bit 9 // no high power ?? +// 6 // NOT DOCUMENTED NOR TESTED // (2) with adapted rfm73 "high power" mode (AN0007) // clear undocumented bit 9 // no high power ?? + +#define RFM75_CONFIG_UNDOCUMENTED_RX_SEN 0 +// Sensitivity in RX mode +// 0: Normal mode +// 1: High sensitivity mode(different CD detection values) // NOT DOCUMENTED NOR TESTED + +#define RFM75_CONFIG_txIctrl 7 // reg4 <29:27> = txIctrl[2:0] in bk2423 // AN0007 +// have to be set together with RF_PWR for exact power level, otherwise -1dBm(or undefined as usual) // user_guide_of_RF75 +// 7 - value for 4 dBm power level +// 3 - value for -12,-18 dBm power levels +// 2 - value for -12 dBm power level +// 0 - value for -1,-7,-18,-25 dBm power levels + +#define RFM75_BANK1_REG5_MODE 2 +// 0 // recommended value for 1Mbps // RSSI disabled +// 1 // recommended value for 2Mbps and 250kbps // RSSI disabled +// 2 // recommended value for 1Mbps // RSSI enabled +// 3 // recommended value for 2Mbps and 250kbps // RSSI enabled +// 4 // NOT DOCUMENTED NOR TESTED // recommended value for 1Mbps // RSSI with selectable threshold +// 5 // NOT DOCUMENTED NOR TESTED // recommended value for 2Mbps and 250kbps // RSSI with selectable threshold +// 6 // rfm73 value adapted for 1Mbps // RSSI disabled +// 7 // rfm73 value adapted for 2Mbps and 250kbps // RSSI disabled +// 8 // rfm73 value adapted for 1Mbps // RSSI with selectable threshold +// 9 // rfm73 value adapted for 2Mbps and 250kbps // RSSI with selectable threshold + +#define RFM75_UNDOCUMENTED_RSSI_THRESHOLD_LEVEL 9 // 0-15? // value is left shifted by 2 into MSB // 9 +// officially there is no RSSI threshold for this chip, but obviously it's so undocumented that it could be implemented + +#define RFM75_BANK1_REGC_MODE 1 +// 0 // rfm70/bk2421 compatible // 120 us PLL settling time +// 1 // nrf24L01+ compatible // 130 us PLL settling time +// 2 // rfm73 adapt // initial value after power up // 120 us PLL settling time // not used/mentioned anywhere +// 3 // rfm73 adapt // initial value after power up // 130 us PLL settling time // not used/mentioned anywhere + +#define RFM75_CONFIG_COMPATIBLE_MODE 0 //0 works when rfm receives and nrf24 transmits +// transmitter and receiver have to use the same mode, otherwise transmitter is seeing 100% packet loss +// This field probably controls the inversion of NO_ACK bit in the air payload in DPL mode +// 0:Static compatible // SI24R1 compatible +// 1:Dynamic compatible // recommended default value + +#define RFM75_BANK1_REGD_MODE 0 +// 0 // recommended bk2425/rfm75 value +// 1 // adapt rfm73 value from replace manual (rfm70->rfm73) + +#define RFM75_BANK1_RAMP_CURVE_MODE 0 +// 0 // recommended bk2425/rfm75 value +// 1 // adapt rfm73 datasheet value + +/*********************************************************************/ + +/************* bk2411/2412 - compatibility and sensitivity ***********/ + +#define BK2411_BANK1_REG3_MODE 0 +// 0 // reccomended value +// 1 // "reset value" + +#define BK2411_BANK1_REG4_MODE 0 +// 0 // reccomended value for 1 mpbs +// 1 // reccomended value for 2 mbps +// 2 // constant wave mode +// 3 // (0) with selectable crystal offset compensation +// 4 // (1) with selectable crystal offset compensation +// 5 // (2) with selectable crystal offset compensation + +#define BK2411_XTALFC 0b1000 // default // signed ??? or unsigned with center at 8 ??? +// Crystal offset compensation, center at 8. +// User can adjust this register to compensate crystal offset + +#define BK2411_RSSI_THRESHOLD_LEVEL 9 // 0-15 +// 0: -97 dBm, 2 dB/step, 15: -67 dBm + +#define BK2411_BANK1_REGC_MODE 0 +// 0 // default recommended value // 300 us PLL, 110 us ramping +// 1 // NOT TESTED // bk2421 compatible // 120 us PLL, 40 us ramping +// 2 // PLL lock and ramping time configurable below + +#define BK2411_TX_LOCK_SEL 1 +// Tx PLL lock time selection +// 0: 120 us, 1: 200 us, 2: 300 us, 3: 500 us + +#define BK2411_TX_RAMP_SEL 10 +// Tx PA ramping time selection +// 0: 10 us, 1: 20us, 2: 30 us, \85 , 15: 160 us + +#define BK2411_BANK1_REGD_MODE 0 +// 0 // reccomended value for 1 mpbs // <100ppm crystal accurancy, GFSK, BT = 1 +// 1 // recommended value for 2 mbps // <5ppm (!) crystal accurancy, FSK +// 2 // (1) with <100ppm crystal accurancy +// 3 // (0) in long payload mode (255 bytes) +// 4 // (1) in long payload mode (255 bytes) +// 5 // (2) in long payload mode (255 bytes) +// 6 // selectable below + +#define BK2411_CYST_ACCU 7 +// Crystal accuracy, the worse accuracy requires the larger value +// Using 7 for crystal accuracy to about 100 PPM +// Using 0 for crystal accuracy better than 5PPM + +#define BK2411_MODU_MOD 0 +// Modulation type +// 0: GFSK mode // cleaner spectrum +// 1: FSK mode // better sensitivity + +#define BK2411_GFSK_BT 1 +// GFSK filter bandwidth ?? // BT = filter\92s -3dB BW / data rate +// 0: BT = 1 // less adjecent bits interference, better sensitivity +// 1: BT = 0.5 // less out of band emmisions + +#define BK2411_LONG_PL 0 +// Enable long payload in normal payload mode +// 0: Normal payload mode +// 1: Enable long payload mode + +#define BK2411_LEN_LONG 255 +// Payload length for maximum 255 bytes payload + +/*********************************************************************/ + +/*************** bk5811 - compatibility and sensitivity **************/ + +#define BK5811_BANK1_DEFAULT_BAND 1 +// reg 0, 2 and 3 +// 0: tune to 5.1GHz band +// 1: tune to 5.8GHz band + +#define BK5811_BANK1_REG4_MODE 0 +// 0: default recommended value +// 1: "single carrier mode" - constant wave mode (after translation from chienglish) + +#define BK5811_RSSI_THRESHOLD_LEVEL 9 // 0-15 +//RSSI Threshold for CD detect +//0: -100 dBm, 2 dB/step, 15: -70 dBm + +/*********************************************************************/ +#endif /* RFM7X_CONFIG_H_ */ diff --git a/examples/rfm7xAndBk242xCompatiblity/rfm7x_hardware.cpp b/examples/rfm7xAndBk242xCompatiblity/rfm7x_hardware.cpp new file mode 100644 index 000000000..925ad4f97 --- /dev/null +++ b/examples/rfm7xAndBk242xCompatiblity/rfm7x_hardware.cpp @@ -0,0 +1,177 @@ +#if defined(ARDUINO) + #include + #include +#elif defined(__AVR_ARCH__) + #include +#else + #include +#endif + +#include "rfm7x_hardware.h" + +void rfm7x_io_init(void) //hardcoded at the moment +{ + RFM7x_CSN_HI; + RFM7x_CE_LOW; + +#if defined(USE_EXAMPLE_SPI_MEGA328) + //set ce to output + //set csn to output +#elif defined(USE_EXAMPLE_SPI_XMEGA) + + //PORTC.DIRSET = PIN4_bm | PIN1_bm; // as output +#elif defined(USE_EXAMPLE_SPI_STM32F0) + + //RCC->AHBENR |= RCC_AHBENR_GPIOAEN; + + //GPIOA->MODER |= (1 << __builtin_ctz(GPIO_MODER_MODER3)) | (1 << __builtin_ctz(GPIO_MODER_MODER4)); // set PA3 and PA4 to output +#elif defined(USE_EXAMPLE_SPI_ARDUINO) + + pinMode(8,OUTPUT); // ce + pinMode(9,OUTPUT); //csn +#else // soft + //set ce to output + //set csn to output +#endif +} + +void spi_init(void) +{ +#if defined(USE_EXAMPLE_SPI_MEGA328) + DDRB |= (1 << PB3) | (1 << PB5); // configure output pins + PORTB |= (1 << PB4); // pullup miso + + SPCR |= (1 << SPE) | (1 << MSTR); + SPSR |= (1 << SPI2X); + +#elif defined(USE_EXAMPLE_SPI_XMEGA) + PORTC.DIRSET = PIN5_bm | PIN7_bm; // sck , mosi + PORTC.PIN6CTRL = PORT_OPC_PULLUP_gc; // pullup miso + SPIC.CTRL = SPI_ENABLE_bm | SPI_MASTER_bm | SPI_MODE_0_gc | SPI_PRESCALER_DIV4_gc; // 32MHz/4 +#elif defined(USE_EXAMPLE_SPI_STM32F0) + + RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; + GPIOA->MODER |= (2 << __builtin_ctz(GPIO_MODER_MODER5))|(2 << __builtin_ctz(GPIO_MODER_MODER6))|(2 << __builtin_ctz(GPIO_MODER_MODER7)); // PA5, PA6, PA7 as alternate + //GPIOA->AFR[0] &= ~((0x0f << __builtin_ctz(GPIO_AFRL_AFR5))|(0x0f << __builtin_ctz(GPIO_AFRL_AFR6))|(0x0f << __builtin_ctz(GPIO_AFRL_AFR7))); + //GPIOA->AFR[0] |= (0 << __builtin_ctz(GPIO_AFRL_AFR5))|(0 << __builtin_ctz(GPIO_AFRL_AFR6))|(0 << __builtin_ctz(GPIO_AFRL_AFR7)); + + GPIOA->OSPEEDR |= (3 << __builtin_ctz(GPIO_OSPEEDR_OSPEEDR5))|(3 << __builtin_ctz(GPIO_OSPEEDR_OSPEEDR7)); // set SCK and MOSI into high speed mode + GPIOA->PUPDR |= (1 << __builtin_ctz(GPIO_PUPDR_PUPDR6)); // pullup miso + + SPI1->CR2 |= SPI_CR2_FRXTH; // RXNE treshold at 1 byte + SPI1->CR1 = SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_SPE | (2 << __builtin_ctz(SPI_CR1_BR)) | SPI_CR1_MSTR; // soft NSS force to master, enable, PCLK/8, master + //SSOE ??? +#elif defined(USE_EXAMPLE_SPI_ARDUINO) + SPI.begin(); + + // necessary? + //SPI.setBitOrder(MSBFIRST); + //SPI.setDataMode(SPI_MODE0); + SPI.setClockDivider(SPI_CLOCK_DIV2); +#else + // can be optimized into single write if port wiring allows + SOFT_SPI_SCK_DIRSET(); + SOFT_SPI_MOSI_DIRSET(); + SOFT_SPI_MISO_DIRSET(); // always input after POR, can be commented out + SOFT_SPI_MISO_PULLUP_SET(); // ?? +#endif +} + +uint8_t spi_rw(uint8_t data) +{ +#if defined(USE_EXAMPLE_SPI_MEGA328) + SPDR = data; + while (!(SPSR & (1 << SPIF))); + + return SPDR; + +#elif defined(USE_EXAMPLE_SPI_XMEGA) + SPIC.DATA = dat; + while(!(SPIC.STATUS & (1<<7))); // no SPIF defined + + return SPIC.DATA; + +#elif defined(USE_EXAMPLE_SPI_STM32F0) + + while( (SPI1->SR & SPI_SR_BSY) ); + *(uint8_t *)&(SPI1->DR) = data; // cast to make 8 bit transfer and thus transmit only 8bit frame + while( !(SPI1->SR & SPI_SR_RXNE) ); + data = SPI1->DR; + return data; +#elif defined(USE_EXAMPLE_SPI_ARDUINO) + uint8_t tmp = SPI.transfer(data); + return tmp; +#else + for(uint_fast8_t i = 0; i < 8; i++) + { + if (data & 0x80) + SOFT_SPI_MOSI_HI(); + else + SOFT_SPI_MOSI_LO(); + + //_delay_us(0.125); + //_delay_us(1); + delayMicroseconds(1); + SOFT_SPI_SCK_HI(); + delayMicroseconds(1); + // _delay_us(1); + + data <<= 1; + + if (SOFT_SPI_MISO_READ()) + data |= 0x01; // data++ + + // _delay_us(0.125); + delayMicroseconds(1); + SOFT_SPI_SCK_LO(); + // _delay_us(0.125); + delayMicroseconds(1); + } + + return data; +#endif +} + +void spi_reg_write(uint8_t reg, uint8_t dat) +{ + spi_rw(reg); + spi_rw(dat); +} + +uint8_t spi_reg_read(uint8_t reg) +{ + uint8_t tmp; + + spi_rw(reg); + tmp = spi_rw(0); + + return tmp; // spi_rw(spi_rw(reg)) +} + +void spi_reg_buff_write(uint8_t reg, uint8_t *buff, uint8_t len) +{ + spi_rw(reg); + + for(uint8_t i=0; i + +//#define USE_EXAMPLE_SPI_MEGA328 +//#define USE_EXAMPLE_SPI_XMEGA +//#define USE_EXAMPLE_SPI_STM32F0 +#define USE_EXAMPLE_SPI_ARDUINO +//else soft + +//haedcoded at the moment +#define RFM7x_CSN_LOW digitalWrite(8, LOW) +#define RFM7x_CSN_HI digitalWrite(8, HIGH) + +#define RFM7x_CE_LOW digitalWrite(7, LOW) +#define RFM7x_CE_HI digitalWrite(7, HIGH) + +#if !defined(USE_EXAMPLE_SPI_MEGA328) && !defined(USE_EXAMPLE_SPI_XMEGA) && !defined(USE_EXAMPLE_SPI_STM32F0) && !defined(USE_EXAMPLE_SPI_ARDUINO) +// tiny 2313 in this case + +#define SOFT_SPI_MOSI_DIRSET() DDRB |= (1 << PB5) +#define SOFT_SPI_MISO_DIRSET() DDRB &= ~(1 << PB6) +#define SOFT_SPI_SCK_DIRSET() DDRB |= (1 << PB7) +#define SOFT_SPI_MISO_PULLUP_SET() PORTB |= (1 << PB6) + +#define SOFT_SPI_MOSI_HI() PORTB |= (1 << PB5) +#define SOFT_SPI_MOSI_LO() PORTB &= ~(1 << PB5) + +#define SOFT_SPI_SCK_HI() PORTB |= (1 << PB7) +#define SOFT_SPI_SCK_LO() PORTB &= ~(1 << PB7) + +#define SOFT_SPI_MISO_READ() PINB &(1 << PB6) +#endif + +//define here your functions if needed (also add extern declaration above) +#define rfm7x_spi_rw(__data) spi_rw(__data) +#define rfm7x_buff_write(__buff,__len) spi_buff_write(__buff,__len) +#define rfm7x_buff_read(__buff,__len) spi_buff_read(__buff,__len) + +#ifdef __cplusplus + extern "C" { +#endif + + void rfm7x_io_init(void); // initialize CE and CSN outputs + + void spi_init(void); + + uint8_t spi_rw(uint8_t data); + + //universal spi functions (no CSN/SS handling) + void spi_reg_write(uint8_t reg, uint8_t dat); + uint8_t spi_reg_read(uint8_t reg); + + void spi_reg_buff_write(uint8_t reg, uint8_t *buff, uint8_t len); + void spi_buff_write(uint8_t *buff, uint8_t len); + + void spi_reg_buff_read(uint8_t reg, uint8_t *buff, uint8_t len); + void spi_buff_read(uint8_t *buff, uint8_t len); + +#ifdef __cplusplus + } +#endif + +#endif // RFM7X_HARDWARE_H_ From 37bb377eb2b1834e03e0415a273c9574ac09b802 Mon Sep 17 00:00:00 2001 From: Tony Date: Fri, 26 Mar 2021 15:31:16 +0100 Subject: [PATCH 2/5] applied auto-formatting --- examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp | 1733 +++++++++-------- examples/rfm7xAndBk242xCompatiblity/rfm7x.h | 926 ++++----- .../rfm7xAndBk242xCompatiblity.ino | 113 +- .../rfm7xAndBk242xCompatiblity/rfm7x_config.h | 73 +- .../rfm7x_hardware.cpp | 227 +-- .../rfm7x_hardware.h | 36 +- 6 files changed, 1563 insertions(+), 1545 deletions(-) diff --git a/examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp b/examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp index e11b0db63..8c687dd37 100644 --- a/examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp +++ b/examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp @@ -6,886 +6,901 @@ //************************************************************** #if defined(__AVR_ARCH__) - #include - #include - #include - #include +#include +#include +#include +#include - #define CRITICAL_SECTION ATOMIC_BLOCK(ATOMIC_RESTORESTATE) +#define CRITICAL_SECTION ATOMIC_BLOCK(ATOMIC_RESTORESTATE) #else - #include - - // workaround for ATOMIC_BLOCK - __attribute__((always_inline)) - inline int __int_disable_irq(void) - { - int primask; - asm volatile("mrs %0, PRIMASK\n" : "=r"(primask)); - asm volatile("cpsid i\n"); - return primask & 1; - } - - __attribute__((always_inline)) - inline void __int_restore_irq(int *primask) - { - if (!(*primask)) - { - asm volatile ("" ::: "memory"); - asm volatile("cpsie i\n"); - } - } - - #define CRITICAL_SECTION for(int primask_save __attribute__((__cleanup__(__int_restore_irq))) = __int_disable_irq(), __ToDo = 1; __ToDo; __ToDo = 0) +#include + +// workaround for ATOMIC_BLOCK +__attribute__((always_inline)) inline int __int_disable_irq(void) +{ + int primask; + asm volatile("mrs %0, PRIMASK\n" + : "=r"(primask)); + asm volatile("cpsid i\n"); + return primask & 1; +} + +__attribute__((always_inline)) inline void __int_restore_irq(int* primask) +{ + if (!(*primask)) { + asm volatile("" :: + : "memory"); + asm volatile("cpsie i\n"); + } +} + +#define CRITICAL_SECTION for (int primask_save __attribute__((__cleanup__(__int_restore_irq))) = __int_disable_irq(), __ToDo = 1; __ToDo; __ToDo = 0) #endif +#include "rfm7x.h" #include #include -#include "rfm7x.h" -#if defined(__AVR_ARCH__)&&!defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - const __flash uint8_t rfm7x_init_struct[] = +#if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) +const __flash uint8_t rfm7x_init_struct[] = #else - const uint8_t rfm7x_init_struct[] = // generic for all architectures // table will be placed in SRAM if your mcu doesn't have unified memory space (flash + ram) -#endif - { - ////////////////////////////////////////// bank 1 initialization registers ////////////////////////////////////////// - - RFM7x_BANK1_REG0, - RFM7x_BANK1_REG1, - RFM7x_BANK1_REG2, - RFM7x_BANK1_REG3, - RFM7x_BANK1_REG4, - RFM7x_BANK1_REG5, - RFM7x_BANK1_REG6, - RFM7x_BANK1_REG7, - RFM7x_BANK1_REG8, - RFM7x_BANK1_REG9, - RFM7x_BANK1_REGA, - RFM7x_BANK1_REGB, - RFM7x_BANK1_REGC, - RFM7x_BANK1_REGD, - RFM7x_BANK1_RAMP_CURVE, - - ////////////////////////////////////////// bank 0 initialization registers ////////////////////////////////////////// +const uint8_t rfm7x_init_struct[] = // generic for all architectures // table will be placed in SRAM if your mcu doesn't have unified memory space (flash + ram) +#endif +{ + ////////////////////////////////////////// bank 1 initialization registers ////////////////////////////////////////// + + RFM7x_BANK1_REG0, + RFM7x_BANK1_REG1, + RFM7x_BANK1_REG2, + RFM7x_BANK1_REG3, + RFM7x_BANK1_REG4, + RFM7x_BANK1_REG5, + RFM7x_BANK1_REG6, + RFM7x_BANK1_REG7, + RFM7x_BANK1_REG8, + RFM7x_BANK1_REG9, + RFM7x_BANK1_REGA, + RFM7x_BANK1_REGB, + RFM7x_BANK1_REGC, + RFM7x_BANK1_REGD, + RFM7x_BANK1_RAMP_CURVE, + +////////////////////////////////////////// bank 0 initialization registers ////////////////////////////////////////// #ifndef RFM7x_DO_NOT_INITIALIZE_BANK0 - RFM7x_BANK0_REG_CONFIG, // PTX/PRX mode - doesn't care, it will be set later with rest commands - RFM7x_BANK0_REG_EN_AA, - RFM7x_BANK0_REG_EN_RXADDR, - RFM7x_BANK0_REG_SETUP_AW, - RFM7x_BANK0_REG_SETUP_RETR, - RFM7x_BANK0_REG_RF_CH, - RFM7x_BANK0_REG_RF_SETUP, - - RFM7x_BANK0_REG_STATUS, // status register that have to be initialized - not documented - RFM7x_BANK0_REG_OBSERVE_TX, // status register that have to be initialized - not documented - RFM7x_BANK0_REG_CD, // status register that have to be initialized - not documented - - #ifndef RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS - 0xE7, // pipe0 default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined - 0xC2, // pipe1 default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined - - RFM7x_PIPE2_RX_ADDRESS, // pipe 2 address // LSB only - RFM7x_PIPE3_RX_ADDRESS, // pipe 3 address // LSB only - RFM7x_PIPE4_RX_ADDRESS, // pipe 4 address // LSB only - RFM7x_PIPE5_RX_ADDRESS, // pipe 5 address // LSB only - #endif - - #if !defined(RFM7x_DO_NOT_INITIALIZE_RX_PAYLOAD_LEN_REGS)&&!defined(RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS) - 0xE7, // TX default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined - - RFM7x_PIPE0_RX_PAYLOAD_LEN, // pipe 0 - payload length // 0 equals to dynamic payload ?? - RFM7x_PIPE1_RX_PAYLOAD_LEN, // pipe 1 - payload length // 0 equals to dynamic payload ?? - RFM7x_PIPE2_RX_PAYLOAD_LEN, // pipe 2 - payload length // 0 equals to dynamic payload ?? - RFM7x_PIPE3_RX_PAYLOAD_LEN, // pipe 3 - payload length // 0 equals to dynamic payload ?? - RFM7x_PIPE4_RX_PAYLOAD_LEN, // pipe 4 - payload length // 0 equals to dynamic payload ?? - RFM7x_PIPE5_RX_PAYLOAD_LEN, // pipe 5 - payload length // 0 equals to dynamic payload ?? - - RFM7x_BANK0_REG_FIFO_STATUS, // status register that have to be initialized - not documented - #endif - - //0x00, // dummy - //0x00, // dummy - //0x00, // dummy - //0x00, // dummy - - //RFM7x_BANK0_REG_DYNPD, - //RFM7x_BANK0_REG_FEATURE, - - #if defined(RFM7x_TX_ADDRESS)&&!defined(RFM7x_USE_PIPE0_ADDRESS_FOR_TX_ADDRESS) - RFM7x_TX_ADDRESS, - #endif - #ifdef RFM7x_PIPE0_RX_ADDRESS - RFM7x_PIPE0_RX_ADDRESS, - #endif - #ifdef RFM7x_PIPE1_RX_ADDRESS - RFM7x_PIPE1_RX_ADDRESS, - #endif - + RFM7x_BANK0_REG_CONFIG, // PTX/PRX mode - doesn't care, it will be set later with rest commands + RFM7x_BANK0_REG_EN_AA, + RFM7x_BANK0_REG_EN_RXADDR, + RFM7x_BANK0_REG_SETUP_AW, + RFM7x_BANK0_REG_SETUP_RETR, + RFM7x_BANK0_REG_RF_CH, + RFM7x_BANK0_REG_RF_SETUP, + + RFM7x_BANK0_REG_STATUS, // status register that have to be initialized - not documented + RFM7x_BANK0_REG_OBSERVE_TX, // status register that have to be initialized - not documented + RFM7x_BANK0_REG_CD, // status register that have to be initialized - not documented + +#ifndef RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS + 0xE7, // pipe0 default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined + 0xC2, // pipe1 default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined + + RFM7x_PIPE2_RX_ADDRESS, // pipe 2 address // LSB only + RFM7x_PIPE3_RX_ADDRESS, // pipe 3 address // LSB only + RFM7x_PIPE4_RX_ADDRESS, // pipe 4 address // LSB only + RFM7x_PIPE5_RX_ADDRESS, // pipe 5 address // LSB only +#endif + +#if !defined(RFM7x_DO_NOT_INITIALIZE_RX_PAYLOAD_LEN_REGS) && !defined(RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS) + 0xE7, // TX default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined + + RFM7x_PIPE0_RX_PAYLOAD_LEN, // pipe 0 - payload length // 0 equals to dynamic payload ?? + RFM7x_PIPE1_RX_PAYLOAD_LEN, // pipe 1 - payload length // 0 equals to dynamic payload ?? + RFM7x_PIPE2_RX_PAYLOAD_LEN, // pipe 2 - payload length // 0 equals to dynamic payload ?? + RFM7x_PIPE3_RX_PAYLOAD_LEN, // pipe 3 - payload length // 0 equals to dynamic payload ?? + RFM7x_PIPE4_RX_PAYLOAD_LEN, // pipe 4 - payload length // 0 equals to dynamic payload ?? + RFM7x_PIPE5_RX_PAYLOAD_LEN, // pipe 5 - payload length // 0 equals to dynamic payload ?? + + RFM7x_BANK0_REG_FIFO_STATUS, // status register that have to be initialized - not documented +#endif + +//0x00, // dummy +//0x00, // dummy +//0x00, // dummy +//0x00, // dummy + +//RFM7x_BANK0_REG_DYNPD, +//RFM7x_BANK0_REG_FEATURE, + +#if defined(RFM7x_TX_ADDRESS) && !defined(RFM7x_USE_PIPE0_ADDRESS_FOR_TX_ADDRESS) + RFM7x_TX_ADDRESS, +#endif +#ifdef RFM7x_PIPE0_RX_ADDRESS + RFM7x_PIPE0_RX_ADDRESS, +#endif +#ifdef RFM7x_PIPE1_RX_ADDRESS + RFM7x_PIPE1_RX_ADDRESS, +#endif + #endif //RFM7x_DO_NOT_INITIALIZE_BANK0 - }; - - void rfm7x_init(void) - { - #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION - #endif - { - #if defined(__AVR_ARCH__)&&!defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - const __flash uint8_t *p_init_struct = rfm7x_init_struct; - #else - const uint8_t *p_init_struct = rfm7x_init_struct; - #endif - - if((0x80 & rfm7x_reg_read(RFM7x_REG_STATUS)) == 0) - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // select bank 1 - - for(uint_fast8_t i=0; i rfm75 migration) says that it should be executed after every PWR_UP, not only during initialization + + // 4. RFM75 PowerUP after the first packet of data sent unsuccessful solution + // RFM75 from the POWER DOWN state to switch to POWER UP state, send the first packet is not successful, the reason + // Is the PLL is not locked, the solution is as follows: + // Before transmitting data normally, please follow the following procedure: + // Power up = 1 + // Wait for 2ms + // Operate the bank1 register, writing a 1 to bit 25 of register 04 + // Wait 20us + // Operate the bank1 register, writing a 0 to bit 25 of register 04 + // Wait for 0.5ms. + // Then normal launch. + + // AN0008 + // 9. Toggle REG4<25?26>, write 1 to bit25, bit 26, then write 0 to them. + +#ifdef RFM7x_ATOMIC_REG_ACCES + CRITICAL_SECTION +#endif + { + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 + +#if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) + rfm7x_reg_buff_write_P(0x04, rfm7x_REG4_toggle_struct, 4); + _delay_us(20); // if not required then this function may not be required, so better to leave it here + rfm7x_reg_buff_write_P(0x04, &rfm7x_init_struct[16], 4); #else - const uint8_t rfm7x_REG4_toggle_struct[] = -#endif - { - 0x06 | RFM7x_BANK1_REG4 // 0x06 will be or'ed with first element (bits 25,26 set) - }; - - void rfm7x_toggle_reg4(void) // MIGHT NOT BE THE CASE FOR BK2411/BK2412/BK5811 - { - // one of the chinese documents (rfm73 -> rfm75 migration) says that it should be executed after every PWR_UP, not only during initialization - - // 4. RFM75 PowerUP after the first packet of data sent unsuccessful solution - // RFM75 from the POWER DOWN state to switch to POWER UP state, send the first packet is not successful, the reason - // Is the PLL is not locked, the solution is as follows: - // Before transmitting data normally, please follow the following procedure: - // Power up = 1 - // Wait for 2ms - // Operate the bank1 register, writing a 1 to bit 25 of register 04 - // Wait 20us - // Operate the bank1 register, writing a 0 to bit 25 of register 04 - // Wait for 0.5ms. - // Then normal launch. - - // AN0008 - // 9. Toggle REG4<25?26>, write 1 to bit25, bit 26, then write 0 to them. - - #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION - #endif - { - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 - - #if defined(__AVR_ARCH__)&&!defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - rfm7x_reg_buff_write_P(0x04,rfm7x_REG4_toggle_struct,4); - _delay_us(20); // if not required then this function may not be required, so better to leave it here - rfm7x_reg_buff_write_P(0x04,&rfm7x_init_struct[16],4); - #else - rfm7x_reg_buff_write(0x04,(uint8_t*)rfm7x_REG4_toggle_struct,4); - //_delay_us(20); // if not required then this function may not be required, so better to leave it here - rfm7x_reg_buff_write(0x04,(uint8_t*)&rfm7x_init_struct[16],4); - #endif - - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 - } - } - - void rfm7x_cmd_write(uint8_t reg, uint8_t dat) - { - #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION - #endif - { - RFM7x_CSN_LOW; - rfm7x_spi_rw(reg); - rfm7x_spi_rw(dat); - RFM7x_CSN_HI; - } - } - - uint8_t rfm7x_cmd_read(uint8_t reg) - { - uint8_t tmp; - - #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION - #endif - { - RFM7x_CSN_LOW; - rfm7x_spi_rw(reg); - tmp = rfm7x_spi_rw(0); // rfm7x_spi_rw(rfm7x_spi_rw()) - RFM7x_CSN_HI; - } - - return tmp; - } + rfm7x_reg_buff_write(0x04, (uint8_t*)rfm7x_REG4_toggle_struct, 4); + //_delay_us(20); // if not required then this function may not be required, so better to leave it here + rfm7x_reg_buff_write(0x04, (uint8_t*)&rfm7x_init_struct[16], 4); +#endif + + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 + } +} + +void rfm7x_cmd_write(uint8_t reg, uint8_t dat) +{ +#ifdef RFM7x_ATOMIC_REG_ACCES + CRITICAL_SECTION +#endif + { + RFM7x_CSN_LOW; + rfm7x_spi_rw(reg); + rfm7x_spi_rw(dat); + RFM7x_CSN_HI; + } +} + +uint8_t rfm7x_cmd_read(uint8_t reg) +{ + uint8_t tmp; + +#ifdef RFM7x_ATOMIC_REG_ACCES + CRITICAL_SECTION +#endif + { + RFM7x_CSN_LOW; + rfm7x_spi_rw(reg); + tmp = rfm7x_spi_rw(0); // rfm7x_spi_rw(rfm7x_spi_rw()) + RFM7x_CSN_HI; + } + + return tmp; +} #ifdef RFM7x_USE_UNIVERSAL_SPI_BUFF_RW_FUNCTIONS - void rfm7x_cmd_buff_write(uint8_t reg, uint8_t *buff, uint8_t len) - { - #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION - #endif - { - RFM7x_CSN_LOW; - rfm7x_spi_rw(reg); - rfm7x_buff_write(buff, len); - RFM7x_CSN_HI; - } - } - - void rfm7x_cmd_buff_read(uint8_t reg, uint8_t *buff, uint8_t len) - { - #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION - #endif - { - RFM7x_CSN_LOW; - rfm7x_spi_rw(reg); - rfm7x_buff_read(buff, len); - RFM7x_CSN_HI; - } - } +void rfm7x_cmd_buff_write(uint8_t reg, uint8_t* buff, uint8_t len) +{ +#ifdef RFM7x_ATOMIC_REG_ACCES + CRITICAL_SECTION +#endif + { + RFM7x_CSN_LOW; + rfm7x_spi_rw(reg); + rfm7x_buff_write(buff, len); + RFM7x_CSN_HI; + } +} + +void rfm7x_cmd_buff_read(uint8_t reg, uint8_t* buff, uint8_t len) +{ +#ifdef RFM7x_ATOMIC_REG_ACCES + CRITICAL_SECTION +#endif + { + RFM7x_CSN_LOW; + rfm7x_spi_rw(reg); + rfm7x_buff_read(buff, len); + RFM7x_CSN_HI; + } +} +#else +void rfm7x_cmd_buff_write(uint8_t reg, uint8_t* buff, uint8_t len) +{ +#ifdef RFM7x_ATOMIC_REG_ACCES + CRITICAL_SECTION +#endif + { + RFM7x_CSN_LOW; + + rfm7x_spi_rw(reg); + + for (uint_fast8_t i = 0; i < len; i++) + rfm7x_spi_rw(buff[i]); + + RFM7x_CSN_HI; + } +} + +void rfm7x_cmd_buff_read(uint8_t reg, uint8_t* buff, uint8_t len) +{ +#ifdef RFM7x_ATOMIC_REG_ACCES + CRITICAL_SECTION +#endif + { + RFM7x_CSN_LOW; + + rfm7x_spi_rw(reg); + + for (uint_fast8_t i = 0; i < len; i++) + buff[i] = rfm7x_spi_rw(0); + + RFM7x_CSN_HI; + } +} +#endif + +#if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) // temporary workaround ?? +void rfm7x_cmd_buff_write_P(uint8_t reg, const __flash uint8_t* buff, uint8_t len) // __memx ???? +{ +#ifdef RFM7x_ATOMIC_REG_ACCES + CRITICAL_SECTION +#endif + { + RFM7x_CSN_LOW; + + rfm7x_spi_rw(reg); + + for (uint_fast8_t i = 0; i < len; i++) + rfm7x_spi_rw(buff[i]); + + RFM7x_CSN_HI; + } +} +#endif + +uint8_t rfm7x_is_present(void) +{ + uint8_t tmp1, tmp2; + tmp1 = rfm7x_reg_read(RFM7x_REG_STATUS); + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); + tmp2 = rfm7x_reg_read(RFM7x_REG_STATUS); + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); + return (tmp1 ^ tmp2) == 0x80; +} + +void rfm7x_power_up(void) +{ + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); + tmp |= 0x02; // set PWR_UP bit + rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); +} + +void rfm7x_power_down(void) +{ + RFM7x_CE_LOW; + + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); + tmp &= 0xFD; // clear PWR_UP bit + rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); +} + +void rfm7x_mode_receive(void) +{ + RFM7x_CE_LOW; + uint8_t tmp; + + //tmp = rfm7x_reg_read(RFM7x_REG_STATUS); + // handle requests here ?? + //rfm7x_reg_write(RFM7x_REG_STATUS, tmp); // clear interrupt requests + + rfm7x_reg_write(RFM7x_REG_STATUS, 0x70); // clear interrupt requests + + tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); + tmp |= 0x01; // set RX bit + rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); + +#ifdef RFM7x_FLUSH_TX_AND_RX_WHILE_SWITCHING_MODES + rfm7x_cmd_write(RFM7x_CMD_FLUSH_TX, 0); +#endif + rfm7x_cmd_write(RFM7x_CMD_FLUSH_RX, 0); // it have to be flushed, otherwise doesn't work + + RFM7x_CE_HI; +} + +void rfm7x_mode_transmit(void) +{ + RFM7x_CE_LOW; + uint8_t tmp; + + //tmp = rfm7x_reg_read(RFM7x_REG_STATUS); + // handle requests here ?? + //rfm7x_reg_write(RFM7x_REG_STATUS, tmp); // clear interrupt requests + + rfm7x_reg_write(RFM7x_REG_STATUS, 0x70); // clear interrupt requests, otherwise further communication is not possible if MAX_RT is asserted + + tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); + tmp &= 0xFE; // clear RX bit + rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); + +#ifdef RFM7x_FLUSH_TX_AND_RX_WHILE_SWITCHING_MODES + rfm7x_cmd_write(RFM7x_CMD_FLUSH_RX, 0); +#endif + rfm7x_cmd_write(RFM7x_CMD_FLUSH_TX, 0); // it have to be flushed, otherwise chip doesn't work + + RFM7x_CE_HI; +} + +uint8_t rfm7x_receive(uint8_t* buff) +{ + uint8_t p = rfm7x_receive_next_pipe(); + + if (p == 0x07) + return 0; + + uint8_t len = rfm7x_receive_next_length(); + + rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); + + return len; +} + +void rfm7x_receive_nocheck(uint8_t* buff) +{ + uint8_t len = rfm7x_receive_next_length(); + rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); +} + +uint8_t rfm7x_receive_p_(uint8_t* pipe, uint8_t* buff) +{ + uint8_t p = rfm7x_receive_next_pipe(); + + if (p == 0x07) + return 0; + + *pipe = p; + uint8_t len = rfm7x_receive_next_length(); + + rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); + + return len; +} + +uint8_t rfm7x_receive_s(uint8_t* buff, uint8_t length) +{ + uint8_t p = rfm7x_receive_next_pipe(); + + if (p == 0x07) + return p; + + rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, length); + + return p; +} + +uint8_t rfm7x_receive_f(uint8_t* buff, uint8_t* pipe, uint8_t* length) +{ + uint8_t p = rfm7x_receive_next_pipe(); + + if (p == 0x07) + return 0; + + uint8_t len = rfm7x_receive_next_length(); + + *pipe = p; + *length = len; + + rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); + + return 1; +} + +void rfm7x_set_rssi_threshold_step(uint8_t level) +{ +#ifdef RFM7x_ATOMIC_REG_ACCES + CRITICAL_SECTION +#endif + { + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 + + RFM7x_CSN_LOW; + rfm7x_spi_rw(0x05 | 0x20); + +#if (RFM7x_MODULECHIP_USED == 2) + uint8_t tmp; + + switch (level) { + case 0: + tmp = 0x00; + break; + case 1: + tmp = 0x02; + break; + case 2: + tmp = 0x01; + break; + case 3: + tmp = 0x03; + break; + case 4: + tmp = 0x08; + break; + case 5: + tmp = 0x0A; + break; + case 6: + tmp = 0x09; + break; + case 7: + tmp = 0x0B; + break; + case 8: + tmp = 0x04; + break; + case 9: + tmp = 0x06; + break; + case 10: + tmp = 0x05; + break; + case 11: + tmp = 0x07; + break; + case 12: + tmp = 0x0C; + break; + case 13: + tmp = 0x0E; + break; + case 14: + tmp = 0x0D; + break; + case 15: + tmp = 0x0F; + break; + default: + tmp = level; + break; + } + + rfm7x_spi_rw(tmp << 2); #else - void rfm7x_cmd_buff_write(uint8_t reg, uint8_t *buff, uint8_t len) - { - #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION - #endif - { - RFM7x_CSN_LOW; - - rfm7x_spi_rw(reg); - - for(uint_fast8_t i=0; i> 2) << 4); // to optimize ? - rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); - - #endif - } - - void rfm7x_set_lna_gain(uint8_t enable) - { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); - - if(enable) - tmp |= RFM7x_RF_SETUP_LNA_HCURR; - else - tmp &= ~(RFM7x_RF_SETUP_LNA_HCURR); - - rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); - } - - void rfm7x_set_datarate(uint8_t datarate) - { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); - - #if (RFM7x_MODULECHIP_USED == 0)|(RFM7x_MODULECHIP_USED == 1)|(RFM7x_MODULECHIP_USED == 4)|(RFM7x_MODULECHIP_USED == 5) // bk2401/bk2421/bk2411/bk2412/bk5811 - tmp &= ~(RFM7x_RF_SETUP_RF_DR_HIGH); - - if(datarate & 0x01) - tmp |= RFM7x_RF_SETUP_RF_DR_HIGH; - - //tmp |= ((datarate & 0x01) << 3); - #elif (RFM7x_MODULECHIP_USED == 2)|(RFM7x_MODULECHIP_USED == 3) // bk2423/bk2425 - tmp &= ~(RFM7x_RF_SETUP_RF_DR_HIGH|RFM7x_RF_SETUP_RF_DR_LOW); - - if(datarate & 0x01) - tmp |= RFM7x_RF_SETUP_RF_DR_HIGH; - - if(datarate & 0x02) - tmp |= RFM7x_RF_SETUP_RF_DR_LOW; - - //tmp |= ((datarate & 0x01) << 3)|(((datarate >> 1) & 0x01) << 5); - #endif - - rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); - } - -#if (RFM7x_MODULECHIP_USED == 4)||(RFM7x_MODULECHIP_USED == 5) - void rfm7x_enable_rssi_measurements(uint8_t enable) - { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); - - if(enable) - tmp |= RFM7x_RF_SETUP_RSSI_EN; - else - tmp &= ~(RFM7x_RF_SETUP_RSSI_EN); - - rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); - } + rfm7x_spi_rw(level << 2); +#endif + rfm7x_spi_rw(rfm7x_init_struct[21]); + rfm7x_spi_rw(rfm7x_init_struct[22]); + rfm7x_spi_rw(rfm7x_init_struct[23]); + RFM7x_CSN_HI; + + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 + } +} + +void rfm7x_set_crc_length(uint8_t len) +{ + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); + + tmp &= ~(RFM7x_CONFIG_EN_CRC | RFM7x_CONFIG_CRCO); // clear EN_CRC and CRCO + + if (len == 0) { + rfm7x_reg_write(RFM7x_REG_EN_AA, 0); // Auto ACK have to be disabled before disabling CRC + rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); + } else { + tmp |= (RFM7x_CONFIG_EN_CRC); // set EN_CRC + + if (len & 0x02) // if 2 byte encoding scheme is selected, set CRCO + tmp |= (RFM7x_CONFIG_CRCO); + + //rfm7x_reg_write(RFM7x_REG_EN_AA, 0x3f); //???? + rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); + } +} + +void rfm7x_set_tx_pwr(uint8_t level) +{ + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); + +#if (RFM7x_MODULECHIP_USED == 0) | (RFM7x_MODULECHIP_USED == 1) | (RFM7x_MODULECHIP_USED == 2) // bk2401//bk2421/bk2423 + + tmp |= (level << 1); + rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); + +#elif (RFM7x_MODULECHIP_USED == 3) // bk2425 + + uint8_t txictrl_tmp = 0; + + switch (level) { + default: + case 0: // -25 dBm + case 1: // -18 dBm + break; + case 2: // -12 dBm + level -= 1; + txictrl_tmp = 1; + break; + + case 3: // -7 dBm + level -= 1; + txictrl_tmp = 2; + break; + + case 4: // -1 dBm + level -= 1; + break; + + case 5: // 4 dBm + level -= 2; + txictrl_tmp = 7; + break; + } + + tmp |= (level << 1); + rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); + +#ifdef RFM7x_ATOMIC_REG_ACCES + CRITICAL_SECTION +#endif + { + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 + + RFM7x_CSN_LOW; + rfm7x_spi_rw(0x04 | 0x20); + rfm7x_spi_rw((rfm7x_init_struct[16] & 0x38) | txictrl_tmp); + rfm7x_spi_rw(rfm7x_init_struct[17]); + rfm7x_spi_rw(rfm7x_init_struct[18]); + rfm7x_spi_rw(rfm7x_init_struct[19]); + RFM7x_CSN_HI; + + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 + } + +#elif (RFM7x_MODULECHIP_USED == 4) | (RFM7x_MODULECHIP_USED == 5) // bk2411//bk2412//bk5811 + + tmp |= ((level & 0x03) << 1) | ((level >> 2) << 4); // to optimize ? + rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); + +#endif +} + +void rfm7x_set_lna_gain(uint8_t enable) +{ + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); + + if (enable) + tmp |= RFM7x_RF_SETUP_LNA_HCURR; + else + tmp &= ~(RFM7x_RF_SETUP_LNA_HCURR); + + rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); +} + +void rfm7x_set_datarate(uint8_t datarate) +{ + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); + +#if (RFM7x_MODULECHIP_USED == 0) | (RFM7x_MODULECHIP_USED == 1) | (RFM7x_MODULECHIP_USED == 4) | (RFM7x_MODULECHIP_USED == 5) // bk2401/bk2421/bk2411/bk2412/bk5811 + tmp &= ~(RFM7x_RF_SETUP_RF_DR_HIGH); + + if (datarate & 0x01) + tmp |= RFM7x_RF_SETUP_RF_DR_HIGH; + + //tmp |= ((datarate & 0x01) << 3); +#elif (RFM7x_MODULECHIP_USED == 2) | (RFM7x_MODULECHIP_USED == 3) // bk2423/bk2425 + tmp &= ~(RFM7x_RF_SETUP_RF_DR_HIGH | RFM7x_RF_SETUP_RF_DR_LOW); + + if (datarate & 0x01) + tmp |= RFM7x_RF_SETUP_RF_DR_HIGH; + + if (datarate & 0x02) + tmp |= RFM7x_RF_SETUP_RF_DR_LOW; + + //tmp |= ((datarate & 0x01) << 3)|(((datarate >> 1) & 0x01) << 5); +#endif + + rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); +} + +#if (RFM7x_MODULECHIP_USED == 4) || (RFM7x_MODULECHIP_USED == 5) +void rfm7x_enable_rssi_measurements(uint8_t enable) +{ + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); + + if (enable) + tmp |= RFM7x_RF_SETUP_RSSI_EN; + else + tmp &= ~(RFM7x_RF_SETUP_RSSI_EN); + + rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); +} #endif #if (RFM7x_MODULECHIP_USED == 4) - void rfm7x_dreg_enable(uint8_t enable) - { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); - - if(enable) - tmp |= BK2411_RF_SETUP_DREG_ON; - else - tmp &= ~(BK2411_RF_SETUP_DREG_ON); - - rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); - } -#endif - - void rfm7x_enable_pipe_autoack(uint8_t pipe, uint8_t enabled) - { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_EN_AA); - - tmp &= ~(1 << pipe); - - if(enabled) - tmp |= (1 << pipe); - - rfm7x_reg_write(RFM7x_REG_EN_AA, tmp); - } - - void rfm7x_enable_pipe_receive(uint8_t pipe, uint8_t enabled) - { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_EN_RXADDR); - - tmp &= ~(1 << pipe); - - if(enabled) - tmp |= (1 << pipe); - - rfm7x_reg_write(RFM7x_REG_EN_RXADDR, tmp); - } - - void rfm7x_enable_dynamic_payload_feature(uint8_t enable) - { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); - - tmp &= ~(RFM7x_FEATURE_EN_DPL); - - if(enable) - tmp |= RFM7x_FEATURE_EN_DPL; - - rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); - } - - void rfm7x_enable_ack_payload_feature(uint8_t enable) - { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); - - tmp &= ~(RFM7x_FEATURE_EN_ACK_PAY); - - if(enable) - tmp |= RFM7x_FEATURE_EN_ACK_PAY; - - rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); - } - - void rfm7x_enable_noack_payload_feature(uint8_t enable) - { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); - - tmp &= ~(RFM7x_FEATURE_EN_DYN_ACK); - - if(enable) - tmp |= RFM7x_FEATURE_EN_DYN_ACK; - - rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); - } - - void rfm7x_set_transmit_address(uint8_t* addr) - { - uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); - size += 2; - rfm7x_reg_buff_write(RFM7x_REG_TX_ADDR, addr, size); - } - - void rfm7x_open_writing_pipe(uint64_t addr) - { - uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); - size += 2; - - //initialize also RX0 ? - rfm7x_reg_buff_write(RFM7x_REG_TX_ADDR, (uint8_t *)&addr, size); // just push that onto the stack, forget about shifts - } - - //pipe 1 and 2 (??) - void rfm7x_set_receive_address(uint8_t pipe, uint8_t* addr) - { - uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); - size += 2; - rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P0+pipe, addr, size); - } - - void rfm7x_open_reading_pipe(uint8_t pipe, uint64_t addr) - { - rfm7x_enable_pipe_receive(pipe, 1); - - if(pipe >= 2) - { - rfm7x_reg_write(RFM7x_REG_RX_ADDR_P0+pipe, (addr & 0xff)); - } - else - { - uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); - size += 2; - - rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P0+pipe, (uint8_t *)&addr, size); // just push that onto the stack, forget about shifts // LE archs only ? - } - } +void rfm7x_dreg_enable(uint8_t enable) +{ + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); + + if (enable) + tmp |= BK2411_RF_SETUP_DREG_ON; + else + tmp &= ~(BK2411_RF_SETUP_DREG_ON); + + rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); +} +#endif + +void rfm7x_enable_pipe_autoack(uint8_t pipe, uint8_t enabled) +{ + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_EN_AA); + + tmp &= ~(1 << pipe); + + if (enabled) + tmp |= (1 << pipe); + + rfm7x_reg_write(RFM7x_REG_EN_AA, tmp); +} + +void rfm7x_enable_pipe_receive(uint8_t pipe, uint8_t enabled) +{ + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_EN_RXADDR); + + tmp &= ~(1 << pipe); + + if (enabled) + tmp |= (1 << pipe); + + rfm7x_reg_write(RFM7x_REG_EN_RXADDR, tmp); +} + +void rfm7x_enable_dynamic_payload_feature(uint8_t enable) +{ + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); + + tmp &= ~(RFM7x_FEATURE_EN_DPL); + + if (enable) + tmp |= RFM7x_FEATURE_EN_DPL; + + rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); +} + +void rfm7x_enable_ack_payload_feature(uint8_t enable) +{ + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); + + tmp &= ~(RFM7x_FEATURE_EN_ACK_PAY); + + if (enable) + tmp |= RFM7x_FEATURE_EN_ACK_PAY; + + rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); +} + +void rfm7x_enable_noack_payload_feature(uint8_t enable) +{ + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); + + tmp &= ~(RFM7x_FEATURE_EN_DYN_ACK); + + if (enable) + tmp |= RFM7x_FEATURE_EN_DYN_ACK; + + rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); +} + +void rfm7x_set_transmit_address(uint8_t* addr) +{ + uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); + size += 2; + rfm7x_reg_buff_write(RFM7x_REG_TX_ADDR, addr, size); +} + +void rfm7x_open_writing_pipe(uint64_t addr) +{ + uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); + size += 2; + + //initialize also RX0 ? + rfm7x_reg_buff_write(RFM7x_REG_TX_ADDR, (uint8_t*)&addr, size); // just push that onto the stack, forget about shifts +} + +//pipe 1 and 2 (??) +void rfm7x_set_receive_address(uint8_t pipe, uint8_t* addr) +{ + uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); + size += 2; + rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P0 + pipe, addr, size); +} + +void rfm7x_open_reading_pipe(uint8_t pipe, uint64_t addr) +{ + rfm7x_enable_pipe_receive(pipe, 1); + + if (pipe >= 2) { + rfm7x_reg_write(RFM7x_REG_RX_ADDR_P0 + pipe, (addr & 0xff)); + } else { + uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); + size += 2; + + rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P0 + pipe, (uint8_t*)&addr, size); // just push that onto the stack, forget about shifts // LE archs only ? + } +} #if (RFM7x_MODULECHIP_USED == 5) -#if defined(__AVR_ARCH__)&&!defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - const __flash uint8_t rfm7x_swapbandtune_struct[] = +#if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) +const __flash uint8_t rfm7x_swapbandtune_struct[] = +#else +const uint8_t rfm7x_swapbandtune_struct[] = // generic for all architectures // table will be placed in SRAM if your mcu doesn't have unified memory space (flash + ram) +#endif + { +#if (BK5811_BANK1_DEFAULT_BAND == 0) // 5.1GHz in rfm7x_init_struct + + 0x04, 0x05, 0x78, 0x32, // reg 0 + 0xC0, 0x05, 0xAE, 0x00, // reg 1 // dummy + 0xE8, 0x80, 0x0C, 0xD2, // reg 2 + 0x19, 0x0D, 0x7D, 0x6D // reg 3 + +#else //(BK5811_BANK1_DEFAULT_BAND == 1) // 5.8GHz in rfm7x_init_struct + + 0x04, 0x05, 0x78, 0x33, // reg 0 + 0xC0, 0x05, 0xAE, 0x00, // reg 1 // dummy + 0xE8, 0x80, 0x8C, 0xD3, // reg 2 + 0x18, 0x0D, 0x7D, 0x6C // reg 3 +#endif + }; + +void bk5811_set_frequency_band(uint8_t range) +{ +#if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) + const __flash uint8_t* p_swapband_struct; #else - const uint8_t rfm7x_swapbandtune_struct[] = // generic for all architectures // table will be placed in SRAM if your mcu doesn't have unified memory space (flash + ram) -#endif - { - #if (BK5811_BANK1_DEFAULT_BAND == 0) // 5.1GHz in rfm7x_init_struct - - 0x04, 0x05, 0x78, 0x32, // reg 0 - 0xC0, 0x05, 0xAE, 0x00, // reg 1 // dummy - 0xE8, 0x80, 0x0C, 0xD2, // reg 2 - 0x19, 0x0D, 0x7D, 0x6D // reg 3 - - #else //(BK5811_BANK1_DEFAULT_BAND == 1) // 5.8GHz in rfm7x_init_struct - - 0x04, 0x05, 0x78, 0x33, // reg 0 - 0xC0, 0x05, 0xAE, 0x00, // reg 1 // dummy - 0xE8, 0x80, 0x8C, 0xD3, // reg 2 - 0x18, 0x0D, 0x7D, 0x6C // reg 3 - #endif - }; - - void bk5811_set_frequency_band(uint8_t range) - { - #if defined(__AVR_ARCH__)&&!defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - const __flash uint8_t *p_swapband_struct; - #else - const uint8_t *p_swapband_struct; - #endif - - #if (BK5811_BANK1_DEFAULT_BAND == 0) // 5.1GHz in rfm7x_init_struct - if(range) - p_swapband_struct = rfm7x_init_struct; - else - p_swapband_struct = rfm7x_swapbandtune_struct; - #else //(BK5811_BANK1_DEFAULT_BAND == 1) // 5.8GHz in rfm7x_init_struct - if(range) - p_swapband_struct = rfm7x_swapbandtune_struct; - else - p_swapband_struct = rfm7x_init_struct; - #endif - - #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION - #endif - { - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 - - for(uint_fast8_t i=0; i<4; i++) - { - #if defined(__AVR_ARCH__)&&!defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - rfm7x_reg_buff_write_P(i,p_swapband_struct+i*4, 4); - #else - rfm7x_reg_buff_write(i,p_swapband_struct+i*4, 4); - #endif - } - - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 - } - - } + const uint8_t* p_swapband_struct; +#endif + +#if (BK5811_BANK1_DEFAULT_BAND == 0) // 5.1GHz in rfm7x_init_struct + if (range) + p_swapband_struct = rfm7x_init_struct; + else + p_swapband_struct = rfm7x_swapbandtune_struct; +#else //(BK5811_BANK1_DEFAULT_BAND == 1) // 5.8GHz in rfm7x_init_struct + if (range) + p_swapband_struct = rfm7x_swapbandtune_struct; + else + p_swapband_struct = rfm7x_init_struct; +#endif + +#ifdef RFM7x_ATOMIC_REG_ACCES + CRITICAL_SECTION +#endif + { + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 + + for (uint_fast8_t i = 0; i < 4; i++) { +#if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) + rfm7x_reg_buff_write_P(i, p_swapband_struct + i * 4, 4); +#else + rfm7x_reg_buff_write(i, p_swapband_struct + i * 4, 4); +#endif + } + + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 + } +} #endif diff --git a/examples/rfm7xAndBk242xCompatiblity/rfm7x.h b/examples/rfm7xAndBk242xCompatiblity/rfm7x.h index 543ec6455..cd321bc27 100644 --- a/examples/rfm7xAndBk242xCompatiblity/rfm7x.h +++ b/examples/rfm7xAndBk242xCompatiblity/rfm7x.h @@ -11,80 +11,80 @@ #include "rfm7x_hardware.h" #ifdef __cplusplus - extern "C" { -#endif - -#define RFM7x_CMD_READ_REG 0x00 -#define RFM7x_CMD_WRITE_REG 0x20 -#define RFM7x_CMD_R_RX_PAYLOAD 0x61 -#define RFM7x_CMD_W_TX_PAYLOAD 0xA0 -#define RFM7x_CMD_FLUSH_TX 0xE1 -#define RFM7x_CMD_FLUSH_RX 0xE2 -#define RFM7x_CMD_REUSE_TX_PL 0xE3 -#define RFM7x_CMD_W_TX_PAYLOAD_NOACK 0xB0 -#define RFM7x_CMD_W_ACK_PAYLOAD 0xA8 -#define RFM7x_CMD_ACTIVATE 0x50 -#define RFM7x_CMD_R_RX_PL_WID 0x60 -#define RFM7x_CMD_NOP 0xFF - -#define RFM7x_REG_CONFIG 0x00 // 'Config' -#define RFM7x_REG_EN_AA 0x01 // 'Enable Auto Acknowledgment' -#define RFM7x_REG_EN_RXADDR 0x02 // 'Enabled RX addresses' -#define RFM7x_REG_SETUP_AW 0x03 // 'Setup address width' -#define RFM7x_REG_SETUP_RETR 0x04 // 'Setup Auto. Retrans' -#define RFM7x_REG_RF_CH 0x05 // 'RF channel' -#define RFM7x_REG_RF_SETUP 0x06 // 'RF setup' -#define RFM7x_REG_STATUS 0x07 // 'Status' -#define RFM7x_REG_OBSERVE_TX 0x08 // 'Observe TX' -#define RFM7x_REG_CD 0x09 // 'Carrier Detect' -#define RFM7x_REG_RX_ADDR_P0 0x0A // 'RX address pipe0' -#define RFM7x_REG_RX_ADDR_P1 0x0B // 'RX address pipe1' -#define RFM7x_REG_RX_ADDR_P2 0x0C // 'RX address pipe2' -#define RFM7x_REG_RX_ADDR_P3 0x0D // 'RX address pipe3' -#define RFM7x_REG_RX_ADDR_P4 0x0E // 'RX address pipe4' -#define RFM7x_REG_RX_ADDR_P5 0x0F // 'RX address pipe5' -#define RFM7x_REG_TX_ADDR 0x10 // 'TX address' -#define RFM7x_REG_RX_PW_P0 0x11 // 'RX payload width, pipe0' -#define RFM7x_REG_RX_PW_P1 0x12 // 'RX payload width, pipe1' -#define RFM7x_REG_RX_PW_P2 0x13 // 'RX payload width, pipe2' -#define RFM7x_REG_RX_PW_P3 0x14 // 'RX payload width, pipe3' -#define RFM7x_REG_RX_PW_P4 0x15 // 'RX payload width, pipe4' -#define RFM7x_REG_RX_PW_P5 0x16 // 'RX payload width, pipe5' -#define RFM7x_REG_FIFO_STATUS 0x17 // 'FIFO Status Register' -#define RFM7x_REG_DYNPD 0x1c // 'Enable dynamic payload length' -#define RFM7x_REG_FEATURE 0x1d // 'Feature' register address +extern "C" { +#endif + +#define RFM7x_CMD_READ_REG 0x00 +#define RFM7x_CMD_WRITE_REG 0x20 +#define RFM7x_CMD_R_RX_PAYLOAD 0x61 +#define RFM7x_CMD_W_TX_PAYLOAD 0xA0 +#define RFM7x_CMD_FLUSH_TX 0xE1 +#define RFM7x_CMD_FLUSH_RX 0xE2 +#define RFM7x_CMD_REUSE_TX_PL 0xE3 +#define RFM7x_CMD_W_TX_PAYLOAD_NOACK 0xB0 +#define RFM7x_CMD_W_ACK_PAYLOAD 0xA8 +#define RFM7x_CMD_ACTIVATE 0x50 +#define RFM7x_CMD_R_RX_PL_WID 0x60 +#define RFM7x_CMD_NOP 0xFF + +#define RFM7x_REG_CONFIG 0x00 // 'Config' +#define RFM7x_REG_EN_AA 0x01 // 'Enable Auto Acknowledgment' +#define RFM7x_REG_EN_RXADDR 0x02 // 'Enabled RX addresses' +#define RFM7x_REG_SETUP_AW 0x03 // 'Setup address width' +#define RFM7x_REG_SETUP_RETR 0x04 // 'Setup Auto. Retrans' +#define RFM7x_REG_RF_CH 0x05 // 'RF channel' +#define RFM7x_REG_RF_SETUP 0x06 // 'RF setup' +#define RFM7x_REG_STATUS 0x07 // 'Status' +#define RFM7x_REG_OBSERVE_TX 0x08 // 'Observe TX' +#define RFM7x_REG_CD 0x09 // 'Carrier Detect' +#define RFM7x_REG_RX_ADDR_P0 0x0A // 'RX address pipe0' +#define RFM7x_REG_RX_ADDR_P1 0x0B // 'RX address pipe1' +#define RFM7x_REG_RX_ADDR_P2 0x0C // 'RX address pipe2' +#define RFM7x_REG_RX_ADDR_P3 0x0D // 'RX address pipe3' +#define RFM7x_REG_RX_ADDR_P4 0x0E // 'RX address pipe4' +#define RFM7x_REG_RX_ADDR_P5 0x0F // 'RX address pipe5' +#define RFM7x_REG_TX_ADDR 0x10 // 'TX address' +#define RFM7x_REG_RX_PW_P0 0x11 // 'RX payload width, pipe0' +#define RFM7x_REG_RX_PW_P1 0x12 // 'RX payload width, pipe1' +#define RFM7x_REG_RX_PW_P2 0x13 // 'RX payload width, pipe2' +#define RFM7x_REG_RX_PW_P3 0x14 // 'RX payload width, pipe3' +#define RFM7x_REG_RX_PW_P4 0x15 // 'RX payload width, pipe4' +#define RFM7x_REG_RX_PW_P5 0x16 // 'RX payload width, pipe5' +#define RFM7x_REG_FIFO_STATUS 0x17 // 'FIFO Status Register' +#define RFM7x_REG_DYNPD 0x1c // 'Enable dynamic payload length' +#define RFM7x_REG_FEATURE 0x1d // 'Feature' register address // Status Register -#define RFM7x_STATUS_IRQ_RX_DR 0x40 -#define RFM7x_STATUS_IRQ_TX_DS 0x20 -#define RFM7x_STATUS_IRQ_MAX_RT 0x10 -#define RFM7x_STATUS_IRQ_TX_FULL 0x01 -#define RFM7x_STATUS_RBANK 0x80 -#define RFM7x_STATUS_RX_PIPE_NUM 0x0E +#define RFM7x_STATUS_IRQ_RX_DR 0x40 +#define RFM7x_STATUS_IRQ_TX_DS 0x20 +#define RFM7x_STATUS_IRQ_MAX_RT 0x10 +#define RFM7x_STATUS_IRQ_TX_FULL 0x01 +#define RFM7x_STATUS_RBANK 0x80 +#define RFM7x_STATUS_RX_PIPE_NUM 0x0E // FIFO Status Register -#define RFM7x_FIFO_STATUS_TX_REUSE 0x40 -#define RFM7x_FIFO_STATUS_TX_FULL 0x20 -#define RFM7x_FIFO_STATUS_TX_EMPTY 0x10 -#define RFM7x_FIFO_STATUS_RX_FULL 0x02 -#define RFM7x_FIFO_STATUS_RX_EMPTY 0x01 +#define RFM7x_FIFO_STATUS_TX_REUSE 0x40 +#define RFM7x_FIFO_STATUS_TX_FULL 0x20 +#define RFM7x_FIFO_STATUS_TX_EMPTY 0x10 +#define RFM7x_FIFO_STATUS_RX_FULL 0x02 +#define RFM7x_FIFO_STATUS_RX_EMPTY 0x01 // Config Register -#define RFM7x_CONFIG_MASK_RX_DR 0x40 // Mask interrupt caused by RX_DR when 1 -#define RFM7x_CONFIG_MASK_TX_DS 0x20 // Mask interrupt caused by TX_DS when 1 -#define RFM7x_CONFIG_MASK_MAX_RT 0x10 // Mask interrupt caused by MAX_RT when 1 -#define RFM7x_CONFIG_EN_CRC 0x08 -#define RFM7x_CONFIG_CRCO 0x04 -#define RFM7x_CONFIG_POWER 0x02 // 1 - Power up ; 0 - Power down -#define RFM7x_CONFIG_PRIM_RX 0x01 // 1 - Receiver ; 0 - Transmitter +#define RFM7x_CONFIG_MASK_RX_DR 0x40 // Mask interrupt caused by RX_DR when 1 +#define RFM7x_CONFIG_MASK_TX_DS 0x20 // Mask interrupt caused by TX_DS when 1 +#define RFM7x_CONFIG_MASK_MAX_RT 0x10 // Mask interrupt caused by MAX_RT when 1 +#define RFM7x_CONFIG_EN_CRC 0x08 +#define RFM7x_CONFIG_CRCO 0x04 +#define RFM7x_CONFIG_POWER 0x02 // 1 - Power up ; 0 - Power down +#define RFM7x_CONFIG_PRIM_RX 0x01 // 1 - Receiver ; 0 - Transmitter //RF config register -#define RFM7x_RF_SETUP_LNA_HCURR 0x01 -#define RFM7x_RF_SETUP_RF_DR_HIGH 0x08 // not high -#define RFM7x_RF_SETUP_RF_DR_LOW 0x20 // and not low // doesn't exists in bk2421/bk2411 -#define RFM7x_RF_SETUP_PLL_LOCK 0x10 // doesn't exists in bk2421/bk2411 -#define BK2411_RF_SETUP_DREG_ON 0x20 // "Digital regulator can be shut down or not " -#define RFM7x_RF_SETUP_RSSI_EN 0x40 // bk2411/12/5811 only +#define RFM7x_RF_SETUP_LNA_HCURR 0x01 +#define RFM7x_RF_SETUP_RF_DR_HIGH 0x08 // not high +#define RFM7x_RF_SETUP_RF_DR_LOW 0x20 // and not low // doesn't exists in bk2421/bk2411 +#define RFM7x_RF_SETUP_PLL_LOCK 0x10 // doesn't exists in bk2421/bk2411 +#define BK2411_RF_SETUP_DREG_ON 0x20 // "Digital regulator can be shut down or not " +#define RFM7x_RF_SETUP_RSSI_EN 0x40 // bk2411/12/5811 only //RF_PWR mask ?? //EN_AA @@ -94,56 +94,56 @@ //DYNPD // Feature Register -#define RFM7x_FEATURE_EN_DPL 0x04 -#define RFM7x_FEATURE_EN_ACK_PAY 0x02 -#define RFM7x_FEATURE_EN_DYN_ACK 0x01 +#define RFM7x_FEATURE_EN_DPL 0x04 +#define RFM7x_FEATURE_EN_ACK_PAY 0x02 +#define RFM7x_FEATURE_EN_DYN_ACK 0x01 ////////////////////////////////////////////////////////////////// -#define RFM7x_BANK0_REG_CONFIG ((RFM7x_BANK0_CONF_PWR_UP << 1)|(RFM7x_BANK0_CONF_CRCO << 2)|(RFM7x_BANK0_CONF_EN_CRC << 3)|(RFM7x_BANK0_CONF_MASK_MAX_RT << 4)|(RFM7x_BANK0_CONF_MASK_TX_DS << 5)|(RFM7x_BANK0_CONF_MASK_RX_DR << 6)) -#define RFM7x_BANK0_REG_EN_AA ((RFM7x_BANK0_CONF_ENAA_P0 << 0)|(RFM7x_BANK0_CONF_ENAA_P1 << 1)|(RFM7x_BANK0_CONF_ENAA_P2 << 2)|(RFM7x_BANK0_CONF_ENAA_P3 << 3)|(RFM7x_BANK0_CONF_ENAA_P4 << 4)|(RFM7x_BANK0_CONF_ENAA_P5 << 5)) -#define RFM7x_BANK0_REG_EN_RXADDR ((RFM7x_BANK0_CONF_ERX_P0 << 0)|(RFM7x_BANK0_CONF_ERX_P1 << 1)|(RFM7x_BANK0_CONF_ERX_P2 << 2)|(RFM7x_BANK0_CONF_ERX_P3 << 3)|(RFM7x_BANK0_CONF_ERX_P4 << 4)|(RFM7x_BANK0_CONF_ERX_P5 << 5)) -#define RFM7x_BANK0_REG_SETUP_AW ((RFM7x_BANK0_CONF_AW)) -#define RFM7x_BANK0_REG_SETUP_RETR ((RFM7x_BANK0_CONF_ARC)|(RFM7x_BANK0_CONF_ARD << 4)) -#define RFM7x_BANK0_REG_RF_CH (RFM7x_BANK0_CONF_RF_CH) +#define RFM7x_BANK0_REG_CONFIG ((RFM7x_BANK0_CONF_PWR_UP << 1) | (RFM7x_BANK0_CONF_CRCO << 2) | (RFM7x_BANK0_CONF_EN_CRC << 3) | (RFM7x_BANK0_CONF_MASK_MAX_RT << 4) | (RFM7x_BANK0_CONF_MASK_TX_DS << 5) | (RFM7x_BANK0_CONF_MASK_RX_DR << 6)) +#define RFM7x_BANK0_REG_EN_AA ((RFM7x_BANK0_CONF_ENAA_P0 << 0) | (RFM7x_BANK0_CONF_ENAA_P1 << 1) | (RFM7x_BANK0_CONF_ENAA_P2 << 2) | (RFM7x_BANK0_CONF_ENAA_P3 << 3) | (RFM7x_BANK0_CONF_ENAA_P4 << 4) | (RFM7x_BANK0_CONF_ENAA_P5 << 5)) +#define RFM7x_BANK0_REG_EN_RXADDR ((RFM7x_BANK0_CONF_ERX_P0 << 0) | (RFM7x_BANK0_CONF_ERX_P1 << 1) | (RFM7x_BANK0_CONF_ERX_P2 << 2) | (RFM7x_BANK0_CONF_ERX_P3 << 3) | (RFM7x_BANK0_CONF_ERX_P4 << 4) | (RFM7x_BANK0_CONF_ERX_P5 << 5)) +#define RFM7x_BANK0_REG_SETUP_AW ((RFM7x_BANK0_CONF_AW)) +#define RFM7x_BANK0_REG_SETUP_RETR ((RFM7x_BANK0_CONF_ARC) | (RFM7x_BANK0_CONF_ARD << 4)) +#define RFM7x_BANK0_REG_RF_CH (RFM7x_BANK0_CONF_RF_CH) #if (RFM7x_MODULECHIP_USED == 4) // bk2411, bk2412 - #define RFM7x_BANK0_REG_RF_SETUP ((RFM7x_BANK0_CONF_LNA_HCURR)|((RFM7x_BANK0_CONF_RF_PWR & 0x03) << 1)|((RFM7x_BANK0_CONF_RF_PWR >> 2) << 4)|(RFM7x_BANK0_CONF_RF_DR << 3)|(BK2411_BANK0_CONF_DREG_ON << 5)|(RFM7x_BANK0_CONF_RSSI_EN << 6)) +#define RFM7x_BANK0_REG_RF_SETUP ((RFM7x_BANK0_CONF_LNA_HCURR) | ((RFM7x_BANK0_CONF_RF_PWR & 0x03) << 1) | ((RFM7x_BANK0_CONF_RF_PWR >> 2) << 4) | (RFM7x_BANK0_CONF_RF_DR << 3) | (BK2411_BANK0_CONF_DREG_ON << 5) | (RFM7x_BANK0_CONF_RSSI_EN << 6)) #elif (RFM7x_MODULECHIP_USED == 5) // bk5811 - #define RFM7x_BANK0_REG_RF_SETUP ((RFM7x_BANK0_CONF_LNA_HCURR)|((RFM7x_BANK0_CONF_RF_PWR & 0x03) << 1)|((RFM7x_BANK0_CONF_RF_PWR >> 2) << 4)|(RFM7x_BANK0_CONF_RF_DR << 3)|(RFM7x_BANK0_CONF_RSSI_EN << 6)) +#define RFM7x_BANK0_REG_RF_SETUP ((RFM7x_BANK0_CONF_LNA_HCURR) | ((RFM7x_BANK0_CONF_RF_PWR & 0x03) << 1) | ((RFM7x_BANK0_CONF_RF_PWR >> 2) << 4) | (RFM7x_BANK0_CONF_RF_DR << 3) | (RFM7x_BANK0_CONF_RSSI_EN << 6)) #else - #define RFM7x_BANK0_REG_RF_SETUP ((RFM7x_BANK0_CONF_LNA_HCURR)|(RFM7x_BANK0_CONF_RF_PWR << 1)|((RFM7x_BANK0_CONF_RF_DR & 0x01) << 3)|((RFM7x_BANK0_CONF_RF_DR >> 1) << 5)) +#define RFM7x_BANK0_REG_RF_SETUP ((RFM7x_BANK0_CONF_LNA_HCURR) | (RFM7x_BANK0_CONF_RF_PWR << 1) | ((RFM7x_BANK0_CONF_RF_DR & 0x01) << 3) | ((RFM7x_BANK0_CONF_RF_DR >> 1) << 5)) #endif -#define RFM7x_BANK0_REG_DYNPD ((RFM7x_BANK0_CONF_DPL_P0 << 0)|(RFM7x_BANK0_CONF_DPL_P1 << 1)|(RFM7x_BANK0_CONF_DPL_P2 << 2)|(RFM7x_BANK0_CONF_DPL_P3 << 3)|(RFM7x_BANK0_CONF_DPL_P4 << 4)|(RFM7x_BANK0_CONF_DPL_P5 << 5)) -#define RFM7x_BANK0_REG_FEATURE ((RFM7x_BANK0_CONF_EN_DYN_ACK)|(RFM7x_BANK0_CONF_EN_ACK_PAY << 1)|(RFM7x_BANK0_CONF_EN_DPL << 2)) - +#define RFM7x_BANK0_REG_DYNPD ((RFM7x_BANK0_CONF_DPL_P0 << 0) | (RFM7x_BANK0_CONF_DPL_P1 << 1) | (RFM7x_BANK0_CONF_DPL_P2 << 2) | (RFM7x_BANK0_CONF_DPL_P3 << 3) | (RFM7x_BANK0_CONF_DPL_P4 << 4) | (RFM7x_BANK0_CONF_DPL_P5 << 5)) +#define RFM7x_BANK0_REG_FEATURE ((RFM7x_BANK0_CONF_EN_DYN_ACK) | (RFM7x_BANK0_CONF_EN_ACK_PAY << 1) | (RFM7x_BANK0_CONF_EN_DPL << 2)) + #ifdef RFM7x_USE_PIPE0_ADDRESS_FOR_TX_ADDRESS - #ifdef RFM7x_TX_ADDRESS_SIZE - #undef RFM7x_TX_ADDRESS_SIZE - #endif +#ifdef RFM7x_TX_ADDRESS_SIZE +#undef RFM7x_TX_ADDRESS_SIZE +#endif - #define RFM7x_TX_ADDRESS_SIZE RFM7x_PIPE0_RX_ADDRESS_SIZE +#define RFM7x_TX_ADDRESS_SIZE RFM7x_PIPE0_RX_ADDRESS_SIZE #endif - #define RFM7x_BANK0_ENTRIES_BASE 10 +#define RFM7x_BANK0_ENTRIES_BASE 10 #if !defined(RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS) - #define RFM7x_BANK0_ENTRIES_RX_ADDR 6 +#define RFM7x_BANK0_ENTRIES_RX_ADDR 6 #else - #define RFM7x_BANK0_ENTRIES_RX_ADDR 0 +#define RFM7x_BANK0_ENTRIES_RX_ADDR 0 #endif -#if !defined(RFM7x_DO_NOT_INITIALIZE_RX_PAYLOAD_LEN_REGS)&&!defined(RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS) - #define RFM7x_BANK0_ENTRIES_RX_LEN 8 +#if !defined(RFM7x_DO_NOT_INITIALIZE_RX_PAYLOAD_LEN_REGS) && !defined(RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS) +#define RFM7x_BANK0_ENTRIES_RX_LEN 8 #else - #define RFM7x_BANK0_ENTRIES_RX_LEN 0 +#define RFM7x_BANK0_ENTRIES_RX_LEN 0 #endif #ifdef RFM7x_DO_NOT_INITIALIZE_BANK0 - #define RFM7x_BANK0_ENTRIES 0 +#define RFM7x_BANK0_ENTRIES 0 #else - #define RFM7x_BANK0_ENTRIES (RFM7x_BANK0_ENTRIES_BASE + RFM7x_BANK0_ENTRIES_RX_ADDR + RFM7x_BANK0_ENTRIES_RX_LEN) +#define RFM7x_BANK0_ENTRIES (RFM7x_BANK0_ENTRIES_BASE + RFM7x_BANK0_ENTRIES_RX_ADDR + RFM7x_BANK0_ENTRIES_RX_LEN) #endif ////////////////////////////////////////// bank 1 initialization registers ////////////////////////////////////////// @@ -157,348 +157,348 @@ #if (RFM7x_MODULECHIP_USED == 0 || RFM7x_MODULECHIP_USED == 1) // BK2421 aka RFM70 + BK2401 - #define RFM7x_BANK1_REG0 0x40, 0x4B, 0x01, 0xE2 - #define RFM7x_BANK1_REG1 0xC0, 0x4B, 0x00, 0x00 - #define RFM7x_BANK1_REG2 0xD0, 0xFC, 0x8C, 0x02 - - #if (RFM70_BANK1_REG3_MODE == 0) - #define RFM7x_BANK1_REG3 0x99, 0x00, 0x39, 0x41 - #elif (RFM70_BANK1_REG3_MODE == 1) - #define RFM7x_BANK1_REG3 0xF9, 0x00, 0x39, 0x41 - #elif (RFM70_BANK1_REG3_MODE == 2) - #define RFM7x_BANK1_REG3 0x03, 0x00, 0x12, 0x00 - #endif - - #if (RFM70_BANK1_REG4_MODE == 0) - #define RFM7x_BANK1_REG4 0xD9, 0x8E|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x86, 0x0B - #elif (RFM70_BANK1_REG4_MODE == 1) - #define RFM7x_BANK1_REG4 0xC9, 0x8E|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x86, 0x0B - #elif (RFM70_BANK1_REG4_MODE == 2) - #define RFM7x_BANK1_REG4 0xF9, 0x8E|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x86, 0x0B - #elif (RFM70_BANK1_REG4_MODE == 3) - #define RFM7x_BANK1_REG4 0xB9, 0x8E|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x86, 0x0B - #elif (RFM70_BANK1_REG4_MODE == 4) - #define RFM7x_BANK1_REG4 0x09, 0x8E|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x86, 0x0B - #elif (RFM70_BANK1_REG4_MODE == 5) - #define RFM7x_BANK1_REG4 0xD9, 0x8E|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x86, 0x21 - #elif (RFM70_BANK1_REG4_MODE == 6) - #define RFM7x_BANK1_REG4 0xD9, 0x86|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x82, 0x1B - #elif (RFM70_BANK1_REG4_MODE == 7) - #define RFM7x_BANK1_REG4 0xF9, 0x8E|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x84, 0x0B - #elif (RFM70_BANK1_REG4_MODE == 8) - #define RFM7x_BANK1_REG4 0xF9, 0x86|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x84, 0x1B - #elif (RFM70_BANK1_REG4_MODE == 9) - #define RFM7x_BANK1_REG4 0xF9, 0x86|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x80, 0x1B - #elif (RFM70_BANK1_REG4_MODE == 10) - #define RFM7x_BANK1_REG4 0xF9, 0x86|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x82, 0x1B - #elif (RFM70_BANK1_REG4_MODE == 11) - #define RFM7x_BANK1_REG4 0xC1, 0x8E|(RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5)|(RFM70_CONFIG_TX_PWR << 4), 0x9A, 0x0B - #endif - - #if (RFM70_BANK1_REG5_MODE == 0) - #define RFM7x_BANK1_REG5 0x24, 0x06, 0x7F, 0xA6 - #elif (RFM70_BANK1_REG5_MODE == 1) - #define RFM7x_BANK1_REG5 (RFM73_RSSI_THRESHOLD_LEVEL << 2), 0x02, 0x7F, 0xA6 - #endif - - #define RFM7x_BANK1_REG6 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REG7 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REG8 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REG9 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REGA 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REGB 0x00, 0x00, 0x00, 0x00 - - #if (RFM70_BANK1_REGC_MODE == 0) - #define RFM7x_BANK1_REGC 0x00, 0x12, 0x73, 0x00 - #elif (RFM70_BANK1_REGC_MODE == 1) - #define RFM7x_BANK1_REGC 0x00, 0x12, 0x73, 0x05 - #elif (RFM70_BANK1_REGC_MODE == 2) - #define RFM7x_BANK1_REGC 0x00, 0x1a, 0x73, 0x00 - #endif - - #if (RFM70_BANK1_REGD_MODE == 0) - #define RFM7x_BANK1_REGD 0x36, 0xB4, 0x80, 0x00 - #elif (RFM70_BANK1_REGD_MODE == 1) - #define RFM7x_BANK1_REGD 0x46, 0xB4, 0x80, 0x00 - #endif - - #if (RFM70_BANK1_RAMP_CURVE_MODE == 0) - #define RFM7x_BANK1_RAMP_CURVE 0x41, 0x20, 0x08, 0x04, 0x81, 0x20, 0xCF, 0xF7, 0xFE, 0xFF, 0xFF - #elif (RFM70_BANK1_RAMP_CURVE_MODE == 1) - #define RFM7x_BANK1_RAMP_CURVE 0x41, 0x10, 0x04, 0x82, 0x20, 0x08, 0x08, 0xF2, 0x7D, 0xEF, 0xFF - #endif +#define RFM7x_BANK1_REG0 0x40, 0x4B, 0x01, 0xE2 +#define RFM7x_BANK1_REG1 0xC0, 0x4B, 0x00, 0x00 +#define RFM7x_BANK1_REG2 0xD0, 0xFC, 0x8C, 0x02 + +#if (RFM70_BANK1_REG3_MODE == 0) +#define RFM7x_BANK1_REG3 0x99, 0x00, 0x39, 0x41 +#elif (RFM70_BANK1_REG3_MODE == 1) +#define RFM7x_BANK1_REG3 0xF9, 0x00, 0x39, 0x41 +#elif (RFM70_BANK1_REG3_MODE == 2) +#define RFM7x_BANK1_REG3 0x03, 0x00, 0x12, 0x00 +#endif + +#if (RFM70_BANK1_REG4_MODE == 0) +#define RFM7x_BANK1_REG4 0xD9, 0x8E | (RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5) | (RFM70_CONFIG_TX_PWR << 4), 0x86, 0x0B +#elif (RFM70_BANK1_REG4_MODE == 1) +#define RFM7x_BANK1_REG4 0xC9, 0x8E | (RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5) | (RFM70_CONFIG_TX_PWR << 4), 0x86, 0x0B +#elif (RFM70_BANK1_REG4_MODE == 2) +#define RFM7x_BANK1_REG4 0xF9, 0x8E | (RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5) | (RFM70_CONFIG_TX_PWR << 4), 0x86, 0x0B +#elif (RFM70_BANK1_REG4_MODE == 3) +#define RFM7x_BANK1_REG4 0xB9, 0x8E | (RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5) | (RFM70_CONFIG_TX_PWR << 4), 0x86, 0x0B +#elif (RFM70_BANK1_REG4_MODE == 4) +#define RFM7x_BANK1_REG4 0x09, 0x8E | (RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5) | (RFM70_CONFIG_TX_PWR << 4), 0x86, 0x0B +#elif (RFM70_BANK1_REG4_MODE == 5) +#define RFM7x_BANK1_REG4 0xD9, 0x8E | (RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5) | (RFM70_CONFIG_TX_PWR << 4), 0x86, 0x21 +#elif (RFM70_BANK1_REG4_MODE == 6) +#define RFM7x_BANK1_REG4 0xD9, 0x86 | (RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5) | (RFM70_CONFIG_TX_PWR << 4), 0x82, 0x1B +#elif (RFM70_BANK1_REG4_MODE == 7) +#define RFM7x_BANK1_REG4 0xF9, 0x8E | (RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5) | (RFM70_CONFIG_TX_PWR << 4), 0x84, 0x0B +#elif (RFM70_BANK1_REG4_MODE == 8) +#define RFM7x_BANK1_REG4 0xF9, 0x86 | (RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5) | (RFM70_CONFIG_TX_PWR << 4), 0x84, 0x1B +#elif (RFM70_BANK1_REG4_MODE == 9) +#define RFM7x_BANK1_REG4 0xF9, 0x86 | (RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5) | (RFM70_CONFIG_TX_PWR << 4), 0x80, 0x1B +#elif (RFM70_BANK1_REG4_MODE == 10) +#define RFM7x_BANK1_REG4 0xF9, 0x86 | (RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5) | (RFM70_CONFIG_TX_PWR << 4), 0x82, 0x1B +#elif (RFM70_BANK1_REG4_MODE == 11) +#define RFM7x_BANK1_REG4 0xC1, 0x8E | (RFM70_CONFIG_UNDOCUMENTED_RX_SEN << 5) | (RFM70_CONFIG_TX_PWR << 4), 0x9A, 0x0B +#endif + +#if (RFM70_BANK1_REG5_MODE == 0) +#define RFM7x_BANK1_REG5 0x24, 0x06, 0x7F, 0xA6 +#elif (RFM70_BANK1_REG5_MODE == 1) +#define RFM7x_BANK1_REG5 (RFM73_RSSI_THRESHOLD_LEVEL << 2), 0x02, 0x7F, 0xA6 +#endif + +#define RFM7x_BANK1_REG6 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REG7 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REG8 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REG9 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REGA 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REGB 0x00, 0x00, 0x00, 0x00 + +#if (RFM70_BANK1_REGC_MODE == 0) +#define RFM7x_BANK1_REGC 0x00, 0x12, 0x73, 0x00 +#elif (RFM70_BANK1_REGC_MODE == 1) +#define RFM7x_BANK1_REGC 0x00, 0x12, 0x73, 0x05 +#elif (RFM70_BANK1_REGC_MODE == 2) +#define RFM7x_BANK1_REGC 0x00, 0x1a, 0x73, 0x00 +#endif + +#if (RFM70_BANK1_REGD_MODE == 0) +#define RFM7x_BANK1_REGD 0x36, 0xB4, 0x80, 0x00 +#elif (RFM70_BANK1_REGD_MODE == 1) +#define RFM7x_BANK1_REGD 0x46, 0xB4, 0x80, 0x00 +#endif + +#if (RFM70_BANK1_RAMP_CURVE_MODE == 0) +#define RFM7x_BANK1_RAMP_CURVE 0x41, 0x20, 0x08, 0x04, 0x81, 0x20, 0xCF, 0xF7, 0xFE, 0xFF, 0xFF +#elif (RFM70_BANK1_RAMP_CURVE_MODE == 1) +#define RFM7x_BANK1_RAMP_CURVE 0x41, 0x10, 0x04, 0x82, 0x20, 0x08, 0x08, 0xF2, 0x7D, 0xEF, 0xFF +#endif #elif (RFM7x_MODULECHIP_USED == 2) // BK2423 aka RFM73 - #define RFM7x_BANK1_REG0 0x40, 0x4B, 0x01, 0xE2 - #define RFM7x_BANK1_REG1 0xC0, 0x4B, 0x00, 0x00 - #define RFM7x_BANK1_REG2 0xD0, 0xFC, 0x8C, 0x02 - - #if (RFM73_BANK1_REG3_MODE == 0) - #define RFM7x_BANK1_REG3 0x99, 0x00, 0x39, 0x41 - #elif (RFM73_BANK1_REG3_MODE == 1) - #define RFM7x_BANK1_REG3 0xF9, 0x00, 0x39, 0x41 - #elif (RFM73_BANK1_REG3_MODE == 2) - #define RFM7x_BANK1_REG3 0x03, 0x00, 0x12, 0x00 - #endif - - #if (RFM73_BANK1_REG4_MODE == 0) - #define RFM7x_BANK1_REG4 0xD9, 0x8E|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x86, 0x0B - #elif (RFM73_BANK1_REG4_MODE == 1) - #define RFM7x_BANK1_REG4 0xD9, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x82, 0x1B - #elif (RFM73_BANK1_REG4_MODE == 2) - #define RFM7x_BANK1_REG4 0xF9, 0x8E|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x84, 0x0B - #elif (RFM73_BANK1_REG4_MODE == 3) - #define RFM7x_BANK1_REG4 0xD9, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x86, 0x1B - #elif (RFM73_BANK1_REG4_MODE == 4) - #define RFM7x_BANK1_REG4 0xF9, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x84, 0x1B - #elif (RFM73_BANK1_REG4_MODE == 5) - #define RFM7x_BANK1_REG4 0xF9, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x80, 0x1B - #elif (RFM73_BANK1_REG4_MODE == 6) - #define RFM7x_BANK1_REG4 0xD9, 0x8E|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x86, 0x21 - #elif (RFM73_BANK1_REG4_MODE == 7) - #define RFM7x_BANK1_REG4 0xF9, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x82, 0x1B - #elif (RFM73_BANK1_REG4_MODE == 8) - #define RFM7x_BANK1_REG4 0xF9, 0x8E|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x86, 0x0B - #elif (RFM73_BANK1_REG4_MODE == 9) - #define RFM7x_BANK1_REG4 0xB9, 0x8E|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x86, 0x0B - #elif (RFM73_BANK1_REG4_MODE == 10) - #define RFM7x_BANK1_REG4 0xB9, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x82, 0x1B - #elif (RFM73_BANK1_REG4_MODE == 11) - #define RFM7x_BANK1_REG4 0x09, 0x8E|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x86, 0x0B - #elif (RFM73_BANK1_REG4_MODE == 12) - #define RFM7x_BANK1_REG4 0x09, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x82, 0x1B - #elif (RFM73_BANK1_REG4_MODE == 13) - #define RFM7x_BANK1_REG4 0xC1, 0x8E|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x9A, 0x0B - #elif (RFM73_BANK1_REG4_MODE == 14) - #define RFM7x_BANK1_REG4 0xC1, 0x8E|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x9A, 0x1B - #elif (RFM73_BANK1_REG4_MODE == 15) - #define RFM7x_BANK1_REG4 0xC1, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x9A, 0x1B - #elif (RFM73_BANK1_REG4_MODE == 16) - #define RFM7x_BANK1_REG4 0xC1, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x9C, 0x1B - #elif (RFM73_BANK1_REG4_MODE == 17) - #define RFM7x_BANK1_REG4 0xC1, 0x86|(RFM73_CONFIG_RX_SEN << 5)|(RFM73_CONFIG_TX_PWR << 4), 0x9E, 0x1B - #endif - - #if (RFM73_BANK1_REG5_MODE == 0) - #define RFM7x_BANK1_REG5 0x24, 0x06, 0x7F, 0xA6 - #elif (RFM73_BANK1_REG5_MODE == 1) - #define RFM7x_BANK1_REG5 (RFM73_RSSI_THRESHOLD_LEVEL << 2), 0x02, 0x7F, 0xA6 - #endif - - #define RFM7x_BANK1_REG6 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REG7 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REG8 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REG9 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REGA 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REGB 0x00, 0x00, 0x00, 0x00 - - #if (RFM73_BANK1_REGC_MODE == 0) - #define RFM7x_BANK1_REGC 0x00, 0x10|(RFM73_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x00 - #elif (RFM73_BANK1_REGC_MODE == 1) - #define RFM7x_BANK1_REGC 0x00, 0x10|(RFM73_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x05 - #elif (RFM73_BANK1_REGC_MODE == 2) - #define RFM7x_BANK1_REGC 0x00, 0x18|(RFM73_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x00 - #elif (RFM73_BANK1_REGC_MODE == 3) - #define RFM7x_BANK1_REGC 0x00, 0x18|(RFM73_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x05 - #endif - - #if (RFM73_BANK1_REGD_MODE == 0) - #define RFM7x_BANK1_REGD 0x36, 0xB4, 0x80, 0x00 - #elif (RFM73_BANK1_REGD_MODE == 1) - #define RFM7x_BANK1_REGD 0x46, 0xB4, 0x80, 0x00 - #endif - - #if (RFM73_BANK1_RAMP_CURVE_MODE == 0) - #define RFM7x_BANK1_RAMP_CURVE 0x41, 0x10, 0x04, 0x82, 0x20, 0x08, 0x08, 0xF2, 0x7D, 0xEF, 0xFF - #elif (RFM73_BANK1_RAMP_CURVE_MODE == 1) - #define RFM7x_BANK1_RAMP_CURVE 0x41, 0x20, 0x08, 0x04, 0x81, 0x20, 0xCF, 0xF7, 0xFE, 0xFF, 0xFF - #endif +#define RFM7x_BANK1_REG0 0x40, 0x4B, 0x01, 0xE2 +#define RFM7x_BANK1_REG1 0xC0, 0x4B, 0x00, 0x00 +#define RFM7x_BANK1_REG2 0xD0, 0xFC, 0x8C, 0x02 + +#if (RFM73_BANK1_REG3_MODE == 0) +#define RFM7x_BANK1_REG3 0x99, 0x00, 0x39, 0x41 +#elif (RFM73_BANK1_REG3_MODE == 1) +#define RFM7x_BANK1_REG3 0xF9, 0x00, 0x39, 0x41 +#elif (RFM73_BANK1_REG3_MODE == 2) +#define RFM7x_BANK1_REG3 0x03, 0x00, 0x12, 0x00 +#endif + +#if (RFM73_BANK1_REG4_MODE == 0) +#define RFM7x_BANK1_REG4 0xD9, 0x8E | (RFM73_CONFIG_RX_SEN << 5) | (RFM73_CONFIG_TX_PWR << 4), 0x86, 0x0B +#elif (RFM73_BANK1_REG4_MODE == 1) +#define RFM7x_BANK1_REG4 0xD9, 0x86 | (RFM73_CONFIG_RX_SEN << 5) | (RFM73_CONFIG_TX_PWR << 4), 0x82, 0x1B +#elif (RFM73_BANK1_REG4_MODE == 2) +#define RFM7x_BANK1_REG4 0xF9, 0x8E | (RFM73_CONFIG_RX_SEN << 5) | (RFM73_CONFIG_TX_PWR << 4), 0x84, 0x0B +#elif (RFM73_BANK1_REG4_MODE == 3) +#define RFM7x_BANK1_REG4 0xD9, 0x86 | (RFM73_CONFIG_RX_SEN << 5) | (RFM73_CONFIG_TX_PWR << 4), 0x86, 0x1B +#elif (RFM73_BANK1_REG4_MODE == 4) +#define RFM7x_BANK1_REG4 0xF9, 0x86 | (RFM73_CONFIG_RX_SEN << 5) | (RFM73_CONFIG_TX_PWR << 4), 0x84, 0x1B +#elif (RFM73_BANK1_REG4_MODE == 5) +#define RFM7x_BANK1_REG4 0xF9, 0x86 | (RFM73_CONFIG_RX_SEN << 5) | (RFM73_CONFIG_TX_PWR << 4), 0x80, 0x1B +#elif (RFM73_BANK1_REG4_MODE == 6) +#define RFM7x_BANK1_REG4 0xD9, 0x8E | (RFM73_CONFIG_RX_SEN << 5) | (RFM73_CONFIG_TX_PWR << 4), 0x86, 0x21 +#elif (RFM73_BANK1_REG4_MODE == 7) +#define RFM7x_BANK1_REG4 0xF9, 0x86 | (RFM73_CONFIG_RX_SEN << 5) | (RFM73_CONFIG_TX_PWR << 4), 0x82, 0x1B +#elif (RFM73_BANK1_REG4_MODE == 8) +#define RFM7x_BANK1_REG4 0xF9, 0x8E | (RFM73_CONFIG_RX_SEN << 5) | (RFM73_CONFIG_TX_PWR << 4), 0x86, 0x0B +#elif (RFM73_BANK1_REG4_MODE == 9) +#define RFM7x_BANK1_REG4 0xB9, 0x8E | (RFM73_CONFIG_RX_SEN << 5) | (RFM73_CONFIG_TX_PWR << 4), 0x86, 0x0B +#elif (RFM73_BANK1_REG4_MODE == 10) +#define RFM7x_BANK1_REG4 0xB9, 0x86 | (RFM73_CONFIG_RX_SEN << 5) | (RFM73_CONFIG_TX_PWR << 4), 0x82, 0x1B +#elif (RFM73_BANK1_REG4_MODE == 11) +#define RFM7x_BANK1_REG4 0x09, 0x8E | (RFM73_CONFIG_RX_SEN << 5) | (RFM73_CONFIG_TX_PWR << 4), 0x86, 0x0B +#elif (RFM73_BANK1_REG4_MODE == 12) +#define RFM7x_BANK1_REG4 0x09, 0x86 | (RFM73_CONFIG_RX_SEN << 5) | (RFM73_CONFIG_TX_PWR << 4), 0x82, 0x1B +#elif (RFM73_BANK1_REG4_MODE == 13) +#define RFM7x_BANK1_REG4 0xC1, 0x8E | (RFM73_CONFIG_RX_SEN << 5) | (RFM73_CONFIG_TX_PWR << 4), 0x9A, 0x0B +#elif (RFM73_BANK1_REG4_MODE == 14) +#define RFM7x_BANK1_REG4 0xC1, 0x8E | (RFM73_CONFIG_RX_SEN << 5) | (RFM73_CONFIG_TX_PWR << 4), 0x9A, 0x1B +#elif (RFM73_BANK1_REG4_MODE == 15) +#define RFM7x_BANK1_REG4 0xC1, 0x86 | (RFM73_CONFIG_RX_SEN << 5) | (RFM73_CONFIG_TX_PWR << 4), 0x9A, 0x1B +#elif (RFM73_BANK1_REG4_MODE == 16) +#define RFM7x_BANK1_REG4 0xC1, 0x86 | (RFM73_CONFIG_RX_SEN << 5) | (RFM73_CONFIG_TX_PWR << 4), 0x9C, 0x1B +#elif (RFM73_BANK1_REG4_MODE == 17) +#define RFM7x_BANK1_REG4 0xC1, 0x86 | (RFM73_CONFIG_RX_SEN << 5) | (RFM73_CONFIG_TX_PWR << 4), 0x9E, 0x1B +#endif + +#if (RFM73_BANK1_REG5_MODE == 0) +#define RFM7x_BANK1_REG5 0x24, 0x06, 0x7F, 0xA6 +#elif (RFM73_BANK1_REG5_MODE == 1) +#define RFM7x_BANK1_REG5 (RFM73_RSSI_THRESHOLD_LEVEL << 2), 0x02, 0x7F, 0xA6 +#endif + +#define RFM7x_BANK1_REG6 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REG7 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REG8 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REG9 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REGA 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REGB 0x00, 0x00, 0x00, 0x00 + +#if (RFM73_BANK1_REGC_MODE == 0) +#define RFM7x_BANK1_REGC 0x00, 0x10 | (RFM73_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x00 +#elif (RFM73_BANK1_REGC_MODE == 1) +#define RFM7x_BANK1_REGC 0x00, 0x10 | (RFM73_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x05 +#elif (RFM73_BANK1_REGC_MODE == 2) +#define RFM7x_BANK1_REGC 0x00, 0x18 | (RFM73_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x00 +#elif (RFM73_BANK1_REGC_MODE == 3) +#define RFM7x_BANK1_REGC 0x00, 0x18 | (RFM73_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x05 +#endif + +#if (RFM73_BANK1_REGD_MODE == 0) +#define RFM7x_BANK1_REGD 0x36, 0xB4, 0x80, 0x00 +#elif (RFM73_BANK1_REGD_MODE == 1) +#define RFM7x_BANK1_REGD 0x46, 0xB4, 0x80, 0x00 +#endif + +#if (RFM73_BANK1_RAMP_CURVE_MODE == 0) +#define RFM7x_BANK1_RAMP_CURVE 0x41, 0x10, 0x04, 0x82, 0x20, 0x08, 0x08, 0xF2, 0x7D, 0xEF, 0xFF +#elif (RFM73_BANK1_RAMP_CURVE_MODE == 1) +#define RFM7x_BANK1_RAMP_CURVE 0x41, 0x20, 0x08, 0x04, 0x81, 0x20, 0xCF, 0xF7, 0xFE, 0xFF, 0xFF +#endif #elif (RFM7x_MODULECHIP_USED == 3) // bk2425 aka RFM75 - #define RFM7x_BANK1_REG0 0x40, 0x4B, 0x01, 0xE2 - #define RFM7x_BANK1_REG1 0xC0, 0x4B, 0x00, 0x00 - #define RFM7x_BANK1_REG2 0xD0, 0xFC, 0x8C, 0x02 - - #if (RFM75_BANK1_REG3_MODE == 0) - #define RFM7x_BANK1_REG3 0x99, 0x00, 0x39, 0x21 - #elif (RFM75_BANK1_REG3_MODE == 1) - #define RFM7x_BANK1_REG3 0x03, 0x00, 0x12, 0x00 - #elif (RFM75_BANK1_REG3_MODE == 2) - #define RFM7x_BANK1_REG3 0xF9, 0x00, 0x39, 0x21 - #elif (RFM75_BANK1_REG3_MODE == 3) - #define RFM7x_BANK1_REG3 0x99, 0x00, 0x39, 0x41 - #elif (RFM75_BANK1_REG3_MODE == 4) - #define RFM7x_BANK1_REG3 0xF9, 0x00, 0x39, 0x41 - #endif - - #if (RFM75_BANK1_REG4_MODE == 0) - #define RFM7x_BANK1_REG4 0xC1|(RFM75_CONFIG_txIctrl << 3), 0x96|(RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x82, 0x1B - #elif (RFM75_BANK1_REG4_MODE == 1) - #define RFM7x_BANK1_REG4 0xC1|(RFM75_CONFIG_txIctrl << 3), 0x96|(RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x82, 0xDB - #elif (RFM75_BANK1_REG4_MODE == 2) - #define RFM7x_BANK1_REG4 0xC1|(RFM75_CONFIG_txIctrl << 3), 0x96|(RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x8A, 0xDB - #elif (RFM75_BANK1_REG4_MODE == 3) - #define RFM7x_BANK1_REG4 0xC1|(RFM75_CONFIG_txIctrl << 3), 0x96|(RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x82, 0x21 - #elif (RFM75_BANK1_REG4_MODE == 4) - #define RFM7x_BANK1_REG4 0xC1|(RFM75_CONFIG_txIctrl << 3), 0x96|(RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x80, 0x1B - #elif (RFM75_BANK1_REG4_MODE == 5) - #define RFM7x_BANK1_REG4 0xC1|(RFM75_CONFIG_txIctrl << 3), 0x96|(RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x80, 0xDB - #elif (RFM75_BANK1_REG4_MODE == 6) - #define RFM7x_BANK1_REG4 0xC1|(RFM75_CONFIG_txIctrl << 3), 0x96|(RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x88, 0xDB - #endif - - #if (RFM75_BANK1_REG5_MODE == 0) - #define RFM7x_BANK1_REG5 0x24, 0x06, 0x0F, 0xA6 - #elif (RFM75_BANK1_REG5_MODE == 1) - #define RFM7x_BANK1_REG5 0x24, 0x06, 0x0F, 0xB6 - #elif (RFM75_BANK1_REG5_MODE == 2) - #define RFM7x_BANK1_REG5 0x24, 0x02, 0x0F, 0xA6 - #elif (RFM75_BANK1_REG5_MODE == 3) - #define RFM7x_BANK1_REG5 0x24, 0x02, 0x0F, 0xB6 - #elif (RFM75_BANK1_REG5_MODE == 4) - #define RFM7x_BANK1_REG5 (RFM75_UNDOCUMENTED_RSSI_THRESHOLD_LEVEL << 2), 0x02, 0x0F, 0xA6 - #elif (RFM75_BANK1_REG5_MODE == 5) - #define RFM7x_BANK1_REG5 (RFM75_UNDOCUMENTED_RSSI_THRESHOLD_LEVEL << 2), 0x02, 0x0F, 0xB6 - #elif (RFM75_BANK1_REG5_MODE == 6) - #define RFM7x_BANK1_REG5 0x24, 0x06, 0x7F, 0xA6 - #elif (RFM75_BANK1_REG5_MODE == 7) - #define RFM7x_BANK1_REG5 0x24, 0x06, 0x7F, 0xB6 - #elif (RFM75_BANK1_REG5_MODE == 8) - #define RFM7x_BANK1_REG5 (RFM75_UNDOCUMENTED_RSSI_THRESHOLD_LEVEL << 2), 0x02, 0x7F, 0xA6 - #elif (RFM75_BANK1_REG5_MODE == 9) - #define RFM7x_BANK1_REG5 (RFM75_UNDOCUMENTED_RSSI_THRESHOLD_LEVEL << 2), 0x02, 0x7F, 0xB6 - #endif - - #define RFM7x_BANK1_REG6 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REG7 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REG8 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REG9 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REGA 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REGB 0x00, 0x00, 0x00, 0x00 - - #if (RFM75_BANK1_REGC_MODE == 0) - #define RFM7x_BANK1_REGC 0x00, 0x10|(RFM75_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x00 - #elif (RFM75_BANK1_REGC_MODE == 1) - #define RFM7x_BANK1_REGC 0x00, 0x10|(RFM75_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x05 - #elif (RFM75_BANK1_REGC_MODE == 2) - #define RFM7x_BANK1_REGC 0x00, 0x18|(RFM75_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x00 - #elif (RFM75_BANK1_REGC_MODE == 3) - #define RFM7x_BANK1_REGC 0x00, 0x18|(RFM75_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x05 - #endif - - #if (RFM75_BANK1_REGD_MODE == 0) - #define RFM7x_BANK1_REGD 0x36, 0xB4, 0x80, 0x00 - #elif (RFM75_BANK1_REGD_MODE == 1) - #define RFM7x_BANK1_REGD 0x46, 0xB4, 0x80, 0x00 - #endif - - #if (RFM75_BANK1_RAMP_CURVE_MODE == 0) - #define RFM7x_BANK1_RAMP_CURVE 0x41, 0x20, 0x08, 0x04, 0x81, 0x20, 0xCF, 0xF7, 0xFE, 0xFF, 0xFF - #elif (RFM75_BANK1_RAMP_CURVE_MODE == 1) - #define RFM7x_BANK1_RAMP_CURVE 0x41, 0x10, 0x04, 0x82, 0x20, 0x08, 0x08, 0xF2, 0x7D, 0xEF, 0xFF - #endif +#define RFM7x_BANK1_REG0 0x40, 0x4B, 0x01, 0xE2 +#define RFM7x_BANK1_REG1 0xC0, 0x4B, 0x00, 0x00 +#define RFM7x_BANK1_REG2 0xD0, 0xFC, 0x8C, 0x02 + +#if (RFM75_BANK1_REG3_MODE == 0) +#define RFM7x_BANK1_REG3 0x99, 0x00, 0x39, 0x21 +#elif (RFM75_BANK1_REG3_MODE == 1) +#define RFM7x_BANK1_REG3 0x03, 0x00, 0x12, 0x00 +#elif (RFM75_BANK1_REG3_MODE == 2) +#define RFM7x_BANK1_REG3 0xF9, 0x00, 0x39, 0x21 +#elif (RFM75_BANK1_REG3_MODE == 3) +#define RFM7x_BANK1_REG3 0x99, 0x00, 0x39, 0x41 +#elif (RFM75_BANK1_REG3_MODE == 4) +#define RFM7x_BANK1_REG3 0xF9, 0x00, 0x39, 0x41 +#endif + +#if (RFM75_BANK1_REG4_MODE == 0) +#define RFM7x_BANK1_REG4 0xC1 | (RFM75_CONFIG_txIctrl << 3), 0x96 | (RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x82, 0x1B +#elif (RFM75_BANK1_REG4_MODE == 1) +#define RFM7x_BANK1_REG4 0xC1 | (RFM75_CONFIG_txIctrl << 3), 0x96 | (RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x82, 0xDB +#elif (RFM75_BANK1_REG4_MODE == 2) +#define RFM7x_BANK1_REG4 0xC1 | (RFM75_CONFIG_txIctrl << 3), 0x96 | (RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x8A, 0xDB +#elif (RFM75_BANK1_REG4_MODE == 3) +#define RFM7x_BANK1_REG4 0xC1 | (RFM75_CONFIG_txIctrl << 3), 0x96 | (RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x82, 0x21 +#elif (RFM75_BANK1_REG4_MODE == 4) +#define RFM7x_BANK1_REG4 0xC1 | (RFM75_CONFIG_txIctrl << 3), 0x96 | (RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x80, 0x1B +#elif (RFM75_BANK1_REG4_MODE == 5) +#define RFM7x_BANK1_REG4 0xC1 | (RFM75_CONFIG_txIctrl << 3), 0x96 | (RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x80, 0xDB +#elif (RFM75_BANK1_REG4_MODE == 6) +#define RFM7x_BANK1_REG4 0xC1 | (RFM75_CONFIG_txIctrl << 3), 0x96 | (RFM75_CONFIG_UNDOCUMENTED_RX_SEN << 5), 0x88, 0xDB +#endif + +#if (RFM75_BANK1_REG5_MODE == 0) +#define RFM7x_BANK1_REG5 0x24, 0x06, 0x0F, 0xA6 +#elif (RFM75_BANK1_REG5_MODE == 1) +#define RFM7x_BANK1_REG5 0x24, 0x06, 0x0F, 0xB6 +#elif (RFM75_BANK1_REG5_MODE == 2) +#define RFM7x_BANK1_REG5 0x24, 0x02, 0x0F, 0xA6 +#elif (RFM75_BANK1_REG5_MODE == 3) +#define RFM7x_BANK1_REG5 0x24, 0x02, 0x0F, 0xB6 +#elif (RFM75_BANK1_REG5_MODE == 4) +#define RFM7x_BANK1_REG5 (RFM75_UNDOCUMENTED_RSSI_THRESHOLD_LEVEL << 2), 0x02, 0x0F, 0xA6 +#elif (RFM75_BANK1_REG5_MODE == 5) +#define RFM7x_BANK1_REG5 (RFM75_UNDOCUMENTED_RSSI_THRESHOLD_LEVEL << 2), 0x02, 0x0F, 0xB6 +#elif (RFM75_BANK1_REG5_MODE == 6) +#define RFM7x_BANK1_REG5 0x24, 0x06, 0x7F, 0xA6 +#elif (RFM75_BANK1_REG5_MODE == 7) +#define RFM7x_BANK1_REG5 0x24, 0x06, 0x7F, 0xB6 +#elif (RFM75_BANK1_REG5_MODE == 8) +#define RFM7x_BANK1_REG5 (RFM75_UNDOCUMENTED_RSSI_THRESHOLD_LEVEL << 2), 0x02, 0x7F, 0xA6 +#elif (RFM75_BANK1_REG5_MODE == 9) +#define RFM7x_BANK1_REG5 (RFM75_UNDOCUMENTED_RSSI_THRESHOLD_LEVEL << 2), 0x02, 0x7F, 0xB6 +#endif + +#define RFM7x_BANK1_REG6 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REG7 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REG8 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REG9 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REGA 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REGB 0x00, 0x00, 0x00, 0x00 + +#if (RFM75_BANK1_REGC_MODE == 0) +#define RFM7x_BANK1_REGC 0x00, 0x10 | (RFM75_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x00 +#elif (RFM75_BANK1_REGC_MODE == 1) +#define RFM7x_BANK1_REGC 0x00, 0x10 | (RFM75_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x05 +#elif (RFM75_BANK1_REGC_MODE == 2) +#define RFM7x_BANK1_REGC 0x00, 0x18 | (RFM75_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x00 +#elif (RFM75_BANK1_REGC_MODE == 3) +#define RFM7x_BANK1_REGC 0x00, 0x18 | (RFM75_CONFIG_COMPATIBLE_MODE << 1), 0x73, 0x05 +#endif + +#if (RFM75_BANK1_REGD_MODE == 0) +#define RFM7x_BANK1_REGD 0x36, 0xB4, 0x80, 0x00 +#elif (RFM75_BANK1_REGD_MODE == 1) +#define RFM7x_BANK1_REGD 0x46, 0xB4, 0x80, 0x00 +#endif + +#if (RFM75_BANK1_RAMP_CURVE_MODE == 0) +#define RFM7x_BANK1_RAMP_CURVE 0x41, 0x20, 0x08, 0x04, 0x81, 0x20, 0xCF, 0xF7, 0xFE, 0xFF, 0xFF +#elif (RFM75_BANK1_RAMP_CURVE_MODE == 1) +#define RFM7x_BANK1_RAMP_CURVE 0x41, 0x10, 0x04, 0x82, 0x20, 0x08, 0x08, 0xF2, 0x7D, 0xEF, 0xFF +#endif #elif (RFM7x_MODULECHIP_USED == 4) // bk2411/2412 - #define RFM7x_BANK1_REG0 0x41, 0x4B, 0x01, 0xF2 - #define RFM7x_BANK1_REG1 0xC0, 0x4B, 0x06, 0x30 - #define RFM7x_BANK1_REG2 0xA0, 0xFC, 0xC4, 0x00 - - #if (BK2411_BANK1_REG3_MODE == 0) - #define RFM7x_BANK1_REG3 0x17, 0x00, 0x35, 0x60 - #elif (BK2411_BANK1_REG3_MODE == 1) - #define RFM7x_BANK1_REG3 0x03, 0x00, 0x12, 0x00 - #endif - - #if (BK2411_BANK1_REG4_MODE == 0) - #define RFM7x_BANK1_REG4 0x41, 0x99, 0x00, 0x0B - #elif (BK2411_BANK1_REG4_MODE == 1) - #define RFM7x_BANK1_REG4 0x41, 0x99, 0x10, 0x0B - #elif (BK2411_BANK1_REG4_MODE == 2) - #define RFM7x_BANK1_REG4 0x41, 0x11, 0x04, 0x21 - #elif (BK2411_BANK1_REG4_MODE == 3) - #define RFM7x_BANK1_REG4 0x41, 0x98|(BK2411_XTALFC >> 3), 0x00|(BK2411_XTALFC << 5), 0x0B - #elif (BK2411_BANK1_REG4_MODE == 4) - #define RFM7x_BANK1_REG4 0x41, 0x98|(BK2411_XTALFC >> 3), 0x10|(BK2411_XTALFC << 5), 0x0B - #elif (BK2411_BANK1_REG4_MODE == 5) - #define RFM7x_BANK1_REG4 0x41, 0x10|(BK2411_XTALFC >> 3), 0x04|(BK2411_XTALFC << 5), 0x21 - #endif - - #define RFM7x_BANK1_REG5 (BK2411_RSSI_THRESHOLD_LEVEL << 2), 0x01, 0x17, 0xBE - #define RFM7x_BANK1_REG6 0x00, 0x00, 0x40, 0x00 - #define RFM7x_BANK1_REG7 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REG8 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REG9 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REGA 0xF6, 0x4E, 0xF5, 0xF6 - #define RFM7x_BANK1_REGB 0x5C, 0x18, 0x51, 0xD6 - - #if (BK2411_BANK1_REGC_MODE == 0) - #define RFM7x_BANK1_REGC 0x40, 0x55, 0x00, 0x2D - #elif (BK2411_BANK1_REGC_MODE == 1) - #define RFM7x_BANK1_REGC 0x60, 0x50, 0x00, 0x2D - #elif (BK2411_BANK1_REGC_MODE == 2) - #define RFM7x_BANK1_REGC 0x00|(BK2411_TX_RAMP_SEL << 5), 0x50|(BK2411_TX_LOCK_SEL << 1)|(BK2411_TX_RAMP_SEL >> 3), 0x00, 0x2D - #endif - - #if (BK2411_BANK1_REGD_MODE == 0) - #define RFM7x_BANK1_REGD 0x00, 0x70, 0x00, 0x00 - #elif (BK2411_BANK1_REGD_MODE == 1) - #define RFM7x_BANK1_REGD 0x00, 0x04, 0x00, 0x00 - #elif (BK2411_BANK1_REGD_MODE == 2) - #define RFM7x_BANK1_REGD 0x00, 0x74, 0x00, 0x00 - #elif (BK2411_BANK1_REGD_MODE == 3) - #define RFM7x_BANK1_REGD 0xFF, 0x71, 0x00, 0x00 - #elif (BK2411_BANK1_REGD_MODE == 4) - #define RFM7x_BANK1_REGD 0xFF, 0x05, 0x00, 0x00 - #elif (BK2411_BANK1_REGD_MODE == 5) - #define RFM7x_BANK1_REGD 0xFF, 0x75, 0x00, 0x00 - #elif (BK2411_BANK1_REGD_MODE == 3) - #define RFM7x_BANK1_REGD (BK2411_LEN_LONG), (BK2411_LONG_PL)|(BK2411_GFSK_BT << 1)|(BK2411_MODU_MOD << 2)|(BK2411_CYST_ACCU <<4), 0x00, 0x00 - #endif - - #define RFM7x_BANK1_RAMP_CURVE 0x41, 0x10, 0x08, 0x82, 0x40, 0x10, 0x08, 0xF2, 0x7C, 0xEF, 0xCF +#define RFM7x_BANK1_REG0 0x41, 0x4B, 0x01, 0xF2 +#define RFM7x_BANK1_REG1 0xC0, 0x4B, 0x06, 0x30 +#define RFM7x_BANK1_REG2 0xA0, 0xFC, 0xC4, 0x00 + +#if (BK2411_BANK1_REG3_MODE == 0) +#define RFM7x_BANK1_REG3 0x17, 0x00, 0x35, 0x60 +#elif (BK2411_BANK1_REG3_MODE == 1) +#define RFM7x_BANK1_REG3 0x03, 0x00, 0x12, 0x00 +#endif + +#if (BK2411_BANK1_REG4_MODE == 0) +#define RFM7x_BANK1_REG4 0x41, 0x99, 0x00, 0x0B +#elif (BK2411_BANK1_REG4_MODE == 1) +#define RFM7x_BANK1_REG4 0x41, 0x99, 0x10, 0x0B +#elif (BK2411_BANK1_REG4_MODE == 2) +#define RFM7x_BANK1_REG4 0x41, 0x11, 0x04, 0x21 +#elif (BK2411_BANK1_REG4_MODE == 3) +#define RFM7x_BANK1_REG4 0x41, 0x98 | (BK2411_XTALFC >> 3), 0x00 | (BK2411_XTALFC << 5), 0x0B +#elif (BK2411_BANK1_REG4_MODE == 4) +#define RFM7x_BANK1_REG4 0x41, 0x98 | (BK2411_XTALFC >> 3), 0x10 | (BK2411_XTALFC << 5), 0x0B +#elif (BK2411_BANK1_REG4_MODE == 5) +#define RFM7x_BANK1_REG4 0x41, 0x10 | (BK2411_XTALFC >> 3), 0x04 | (BK2411_XTALFC << 5), 0x21 +#endif + +#define RFM7x_BANK1_REG5 (BK2411_RSSI_THRESHOLD_LEVEL << 2), 0x01, 0x17, 0xBE +#define RFM7x_BANK1_REG6 0x00, 0x00, 0x40, 0x00 +#define RFM7x_BANK1_REG7 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REG8 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REG9 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REGA 0xF6, 0x4E, 0xF5, 0xF6 +#define RFM7x_BANK1_REGB 0x5C, 0x18, 0x51, 0xD6 + +#if (BK2411_BANK1_REGC_MODE == 0) +#define RFM7x_BANK1_REGC 0x40, 0x55, 0x00, 0x2D +#elif (BK2411_BANK1_REGC_MODE == 1) +#define RFM7x_BANK1_REGC 0x60, 0x50, 0x00, 0x2D +#elif (BK2411_BANK1_REGC_MODE == 2) +#define RFM7x_BANK1_REGC 0x00 | (BK2411_TX_RAMP_SEL << 5), 0x50 | (BK2411_TX_LOCK_SEL << 1) | (BK2411_TX_RAMP_SEL >> 3), 0x00, 0x2D +#endif + +#if (BK2411_BANK1_REGD_MODE == 0) +#define RFM7x_BANK1_REGD 0x00, 0x70, 0x00, 0x00 +#elif (BK2411_BANK1_REGD_MODE == 1) +#define RFM7x_BANK1_REGD 0x00, 0x04, 0x00, 0x00 +#elif (BK2411_BANK1_REGD_MODE == 2) +#define RFM7x_BANK1_REGD 0x00, 0x74, 0x00, 0x00 +#elif (BK2411_BANK1_REGD_MODE == 3) +#define RFM7x_BANK1_REGD 0xFF, 0x71, 0x00, 0x00 +#elif (BK2411_BANK1_REGD_MODE == 4) +#define RFM7x_BANK1_REGD 0xFF, 0x05, 0x00, 0x00 +#elif (BK2411_BANK1_REGD_MODE == 5) +#define RFM7x_BANK1_REGD 0xFF, 0x75, 0x00, 0x00 +#elif (BK2411_BANK1_REGD_MODE == 3) +#define RFM7x_BANK1_REGD (BK2411_LEN_LONG), (BK2411_LONG_PL) | (BK2411_GFSK_BT << 1) | (BK2411_MODU_MOD << 2) | (BK2411_CYST_ACCU << 4), 0x00, 0x00 +#endif + +#define RFM7x_BANK1_RAMP_CURVE 0x41, 0x10, 0x08, 0x82, 0x40, 0x10, 0x08, 0xF2, 0x7C, 0xEF, 0xCF #elif (RFM7x_MODULECHIP_USED == 5) // bk5811 - #if (BK5811_BANK1_DEFAULT_BAND == 0) - #define RFM7x_BANK1_REG0 0x04, 0x05, 0x78, 0x33 - #elif (BK5811_BANK1_DEFAULT_BAND == 1) - #define RFM7x_BANK1_REG0 0x04, 0x05, 0x78, 0x32 - #endif - - #define RFM7x_BANK1_REG1 0xC0, 0x05, 0xAE, 0x00 - - #if (BK5811_BANK1_DEFAULT_BAND == 0) - #define RFM7x_BANK1_REG2 0xE8, 0x80, 0x8C, 0xD3 - #elif (BK5811_BANK1_DEFAULT_BAND == 1) - #define RFM7x_BANK1_REG2 0xE8, 0x80, 0x0C, 0xD2 - #endif - - #if (BK5811_BANK1_DEFAULT_BAND == 0) - #define RFM7x_BANK1_REG3 0x18, 0x0D, 0x7D, 0x6C - #elif (BK5811_BANK1_DEFAULT_BAND == 1) - #define RFM7x_BANK1_REG3 0x19, 0x0D, 0x7D, 0x6D - #endif - - #if (BK5811_BANK1_REG4_MODE == 0) - #define RFM7x_BANK1_REG4 0xE9, 0x8E, 0x82, 0x1B - #elif (BK5811_BANK1_REG4_MODE == 1) - #define RFM7x_BANK1_REG4 0xE9, 0x8E, 0x82, 0x21 - #endif - - #define RFM7x_BANK1_REG5 (BK5811_RSSI_THRESHOLD_LEVEL << 2), 0x10, 0xFF, 0xA6 - #define RFM7x_BANK1_REG6 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REG7 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REG8 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REG9 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REGA 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REGB 0x00, 0x00, 0x00, 0x00 - #define RFM7x_BANK1_REGC 0x00, 0x12, 0x73, 0x00 - #define RFM7x_BANK1_REGD 0x36, 0xB4, 0x80, 0x00 - - #define RFM7x_BANK1_RAMP_CURVE 0x41, 0x20, 0x08, 0x04, 0x81, 0x20, 0xCF, 0xF7, 0xFE, 0xFF, 0xFF +#if (BK5811_BANK1_DEFAULT_BAND == 0) +#define RFM7x_BANK1_REG0 0x04, 0x05, 0x78, 0x33 +#elif (BK5811_BANK1_DEFAULT_BAND == 1) +#define RFM7x_BANK1_REG0 0x04, 0x05, 0x78, 0x32 +#endif + +#define RFM7x_BANK1_REG1 0xC0, 0x05, 0xAE, 0x00 + +#if (BK5811_BANK1_DEFAULT_BAND == 0) +#define RFM7x_BANK1_REG2 0xE8, 0x80, 0x8C, 0xD3 +#elif (BK5811_BANK1_DEFAULT_BAND == 1) +#define RFM7x_BANK1_REG2 0xE8, 0x80, 0x0C, 0xD2 +#endif + +#if (BK5811_BANK1_DEFAULT_BAND == 0) +#define RFM7x_BANK1_REG3 0x18, 0x0D, 0x7D, 0x6C +#elif (BK5811_BANK1_DEFAULT_BAND == 1) +#define RFM7x_BANK1_REG3 0x19, 0x0D, 0x7D, 0x6D +#endif + +#if (BK5811_BANK1_REG4_MODE == 0) +#define RFM7x_BANK1_REG4 0xE9, 0x8E, 0x82, 0x1B +#elif (BK5811_BANK1_REG4_MODE == 1) +#define RFM7x_BANK1_REG4 0xE9, 0x8E, 0x82, 0x21 +#endif + +#define RFM7x_BANK1_REG5 (BK5811_RSSI_THRESHOLD_LEVEL << 2), 0x10, 0xFF, 0xA6 +#define RFM7x_BANK1_REG6 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REG7 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REG8 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REG9 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REGA 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REGB 0x00, 0x00, 0x00, 0x00 +#define RFM7x_BANK1_REGC 0x00, 0x12, 0x73, 0x00 +#define RFM7x_BANK1_REGD 0x36, 0xB4, 0x80, 0x00 + +#define RFM7x_BANK1_RAMP_CURVE 0x41, 0x20, 0x08, 0x04, 0x81, 0x20, 0xCF, 0xF7, 0xFE, 0xFF, 0xFF #endif ////////////////////////////////////////////////////////////////// @@ -520,27 +520,27 @@ void rfm7x_init(void); // one of the chinese AN's (rfm73 -> rfm75) says that it should be executed after every PWR_UP, not only during initialization void rfm7x_toggle_reg4(void); // MIGHT NOT BE THE CASE FOR BK2411/BK2412/BK5811 -#define rfm7x_reg_write(__reg,__dat) rfm7x_cmd_write(RFM7x_CMD_WRITE_REG|(__reg),__dat) -#define rfm7x_reg_read(__reg) rfm7x_cmd_read(RFM7x_CMD_READ_REG|(__reg)) +#define rfm7x_reg_write(__reg, __dat) rfm7x_cmd_write(RFM7x_CMD_WRITE_REG | (__reg), __dat) +#define rfm7x_reg_read(__reg) rfm7x_cmd_read(RFM7x_CMD_READ_REG | (__reg)) void rfm7x_cmd_write(uint8_t reg, uint8_t dat); uint8_t rfm7x_cmd_read(uint8_t reg); -#define rfm7x_reg_buff_write(__reg,__buff,__len) rfm7x_cmd_buff_write(RFM7x_CMD_WRITE_REG|(__reg),__buff,__len) -#define rfm7x_reg_buff_read(__reg,__buff,__len) rfm7x_cmd_buff_read(RFM7x_CMD_READ_REG|(__reg),__buff,__len) +#define rfm7x_reg_buff_write(__reg, __buff, __len) rfm7x_cmd_buff_write(RFM7x_CMD_WRITE_REG | (__reg), __buff, __len) +#define rfm7x_reg_buff_read(__reg, __buff, __len) rfm7x_cmd_buff_read(RFM7x_CMD_READ_REG | (__reg), __buff, __len) + +void rfm7x_cmd_buff_write(uint8_t reg, uint8_t* buff, uint8_t len); +void rfm7x_cmd_buff_read(uint8_t reg, uint8_t* buff, uint8_t len); -void rfm7x_cmd_buff_write(uint8_t reg, uint8_t *buff, uint8_t len); -void rfm7x_cmd_buff_read(uint8_t reg, uint8_t *buff, uint8_t len); +#if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) // temporary workaround ?? +#define rfm7x_reg_buff_write_P(__reg, __buff, __len) rfm7x_cmd_buff_write_P(RFM7x_CMD_WRITE_REG | (__reg), __buff, __len) -#if defined(__AVR_ARCH__)&&!defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) // temporary workaround ?? - #define rfm7x_reg_buff_write_P(__reg,__buff,__len) rfm7x_cmd_buff_write_P(RFM7x_CMD_WRITE_REG|(__reg),__buff,__len) - -#ifdef __cplusplus - void rfm7x_cmd_buff_write_P(uint8_t reg, const uint8_t* buff, uint8_t len); +#ifdef __cplusplus +void rfm7x_cmd_buff_write_P(uint8_t reg, const uint8_t* buff, uint8_t len); #else - void rfm7x_cmd_buff_write_P(uint8_t reg, const __flash uint8_t* buff, uint8_t len); +void rfm7x_cmd_buff_write_P(uint8_t reg, const __flash uint8_t* buff, uint8_t len); #endif - + #endif uint8_t rfm7x_is_present(void); @@ -555,32 +555,32 @@ inline void rfm7x_mode_standby(void) { RFM7x_CE_LOW; } inline uint8_t rfm7x_tx_fifo_full(void) { return (rfm7x_reg_read(RFM7x_REG_FIFO_STATUS) & RFM7x_FIFO_STATUS_TX_FULL) != 0; } inline uint8_t rfm7x_tx_fifo_empty(void) { return (rfm7x_reg_read(RFM7x_REG_FIFO_STATUS) & RFM7x_FIFO_STATUS_TX_EMPTY) != 0; } - + inline uint8_t rfm7x_rx_fifo_full(void) { return (rfm7x_reg_read(RFM7x_REG_FIFO_STATUS) & RFM7x_FIFO_STATUS_RX_FULL) != 0; } inline uint8_t rfm7x_rx_fifo_empty(void) { return (rfm7x_reg_read(RFM7x_REG_FIFO_STATUS) & RFM7x_FIFO_STATUS_RX_EMPTY) != 0; } inline uint8_t rfm7x_receive_next_pipe(void) { return (rfm7x_reg_read(RFM7x_REG_STATUS) >> 1) & 0x07; } inline uint8_t rfm7x_receive_next_length(void) { return rfm7x_cmd_read(RFM7x_CMD_R_RX_PL_WID); } -uint8_t rfm7x_receive(uint8_t *buff); // returns received length // 0x00 - nothing received, or empty packet -void rfm7x_receive_nocheck(uint8_t *buff); +uint8_t rfm7x_receive(uint8_t* buff); // returns received length // 0x00 - nothing received, or empty packet +void rfm7x_receive_nocheck(uint8_t* buff); -uint8_t rfm7x_receive_p_(uint8_t *pipe, uint8_t *buff); // returns received length // 0x00 - nothing received -static inline uint8_t rfm7x_receive_p(uint8_t *buff, uint8_t *pipe) __attribute__((always_inline)); -static inline uint8_t rfm7x_receive_p(uint8_t *buff, uint8_t *pipe) { return rfm7x_receive_p_(pipe, buff); } +uint8_t rfm7x_receive_p_(uint8_t* pipe, uint8_t* buff); // returns received length // 0x00 - nothing received +static inline uint8_t rfm7x_receive_p(uint8_t* buff, uint8_t* pipe) __attribute__((always_inline)); +static inline uint8_t rfm7x_receive_p(uint8_t* buff, uint8_t* pipe) { return rfm7x_receive_p_(pipe, buff); } -inline void rfm7x_receive_nocheck_s(uint8_t *buff, uint8_t length) { rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, length); } -uint8_t rfm7x_receive_s(uint8_t *buff, uint8_t length); // returns number of received pipe // 0x07 - nothing received +inline void rfm7x_receive_nocheck_s(uint8_t* buff, uint8_t length) { rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, length); } +uint8_t rfm7x_receive_s(uint8_t* buff, uint8_t length); // returns number of received pipe // 0x07 - nothing received -uint8_t rfm7x_receive_f(uint8_t *buff, uint8_t *pipe, uint8_t *length); +uint8_t rfm7x_receive_f(uint8_t* buff, uint8_t* pipe, uint8_t* length); -inline void rfm7x_transmit(uint8_t *buff, uint8_t length) { rfm7x_cmd_buff_write(RFM7x_CMD_W_TX_PAYLOAD, buff, length); } -inline void rfm7x_transmit_noack(uint8_t *buff, uint8_t length) { rfm7x_cmd_buff_write(RFM7x_CMD_W_TX_PAYLOAD_NOACK, buff, length); } +inline void rfm7x_transmit(uint8_t* buff, uint8_t length) { rfm7x_cmd_buff_write(RFM7x_CMD_W_TX_PAYLOAD, buff, length); } +inline void rfm7x_transmit_noack(uint8_t* buff, uint8_t length) { rfm7x_cmd_buff_write(RFM7x_CMD_W_TX_PAYLOAD_NOACK, buff, length); } // used in RX mode // transmit message while ACK'ing received packet on selected pipe -inline void rfm7x_rx_ack_transmit(uint8_t pipe, uint8_t *buff, uint8_t length) { rfm7x_cmd_buff_write(RFM7x_CMD_W_ACK_PAYLOAD | pipe, buff, length); } +inline void rfm7x_rx_ack_transmit(uint8_t pipe, uint8_t* buff, uint8_t length) { rfm7x_cmd_buff_write(RFM7x_CMD_W_ACK_PAYLOAD | pipe, buff, length); } -//uint8_t rfm7x_available(uint8_t *pipe); // normal receive mode // +//uint8_t rfm7x_available(uint8_t *pipe); // normal receive mode // // reset irq flags?? void rfm7x_set_rssi_threshold_step(uint8_t level); // usually linear scale from 0 (-97/100dBm) to 15 (-67/70dBm) // bk2423 is also linearized by this function, some levels may be out of useable range (over -105dBm) @@ -632,23 +632,23 @@ void rfm7x_set_lna_gain(uint8_t enable); // 3 - 2mbps // only 73/75 (treat as reserved) void rfm7x_set_datarate(uint8_t datarate); -#if (RFM7x_MODULECHIP_USED == 4)||(RFM7x_MODULECHIP_USED == 5) - void rfm7x_enable_rssi_measurements(uint8_t enable); +#if (RFM7x_MODULECHIP_USED == 4) || (RFM7x_MODULECHIP_USED == 5) +void rfm7x_enable_rssi_measurements(uint8_t enable); #endif #if (RFM7x_MODULECHIP_USED == 4) - //enable on-chip "digital regulator" - void rfm7x_dreg_enable(uint8_t enable); +//enable on-chip "digital regulator" +void rfm7x_dreg_enable(uint8_t enable); #endif //250us steps -inline void rfm7x_set_retransmits(uint8_t retransmits, uint8_t delay) { rfm7x_reg_write(RFM7x_REG_SETUP_RETR, (retransmits)|(delay<<4)); } +inline void rfm7x_set_retransmits(uint8_t retransmits, uint8_t delay) { rfm7x_reg_write(RFM7x_REG_SETUP_RETR, (retransmits) | (delay << 4)); } -// 3 to 5 bytes (2 byte width is reserved) -inline void rfm7x_set_addres_width(uint8_t width) { rfm7x_reg_write(RFM7x_REG_SETUP_AW, width-2); } +// 3 to 5 bytes (2 byte width is reserved) +inline void rfm7x_set_addres_width(uint8_t width) { rfm7x_reg_write(RFM7x_REG_SETUP_AW, width - 2); } //0-32 -inline void rfm7x_set_rx_pyaload_size(uint8_t pipe, uint8_t size) { rfm7x_reg_write(RFM7x_REG_RX_PW_P0+pipe, size); } +inline void rfm7x_set_rx_pyaload_size(uint8_t pipe, uint8_t size) { rfm7x_reg_write(RFM7x_REG_RX_PW_P0 + pipe, size); } //void rfm7x_set_receiving_pipes(uint8_t mask); //void rfm7x_set_autoack_pipes(uint8_t mask); @@ -668,7 +668,7 @@ void rfm7x_open_writing_pipe(uint64_t addr); //pipe 1 and 2 (??) void rfm7x_set_receive_address(uint8_t pipe, uint8_t* addr); // LSB first -inline void rfm7x_set_receive_address_pn(uint8_t pipe, uint8_t LSB_addr) { rfm7x_reg_write(RFM7x_REG_RX_ADDR_P0+pipe, LSB_addr); } +inline void rfm7x_set_receive_address_pn(uint8_t pipe, uint8_t LSB_addr) { rfm7x_reg_write(RFM7x_REG_RX_ADDR_P0 + pipe, LSB_addr); } //all pipes void rfm7x_open_reading_pipe(uint8_t pipe, uint64_t addr); @@ -676,17 +676,17 @@ void rfm7x_open_reading_pipe(uint8_t pipe, uint64_t addr); //observe tx // lost packet reset -// irq ? +// irq ? //status flags #if (RFM7x_MODULECHIP_USED == 5) - // 0: 5.1GHz band - // 1: 5.8GHz band - void bk5811_set_frequency_band(uint8_t range); +// 0: 5.1GHz band +// 1: 5.8GHz band +void bk5811_set_frequency_band(uint8_t range); #endif #ifdef __cplusplus - } +} #endif #endif /* RFM7x_H_ */ diff --git a/examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino b/examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino index 2544d7f5d..947b6d1d4 100644 --- a/examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino +++ b/examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino @@ -21,7 +21,7 @@ RF24 radio(7, 8); // using pin 7 for the CE pin, and pin 8 for the CSN pin // Let these addresses be used for the pair -uint8_t address[][6] = {"1Node", "2Node"}; +uint8_t address[][6] = { "1Node", "2Node" }; // It is very helpful to think of an address as a path instead of as // an identifying device destination @@ -30,79 +30,80 @@ uint8_t address[][6] = {"1Node", "2Node"}; bool radioNumber = 1; // 0 uses address[0] to transmit, 1 uses address[1] to transmit // Used to control whether this node is sending or receiving -bool role = false; // true = TX role, false = RX role +bool role = false; // true = TX role, false = RX role // For this example, we'll be using a payload containing // a single float number that will be incremented // on every successful transmission float payload = 0.0; -void setup() { +void setup() +{ - Serial.begin(115200); - while (!Serial) { - // some boards need to wait to ensure access to serial over USB - } + Serial.begin(115200); + while (!Serial) { + // some boards need to wait to ensure access to serial over USB + } - // initialize the transceiver on the SPI bus - if (!radio.begin()) { - Serial.println(F("radio hardware is not responding!!")); - while (1) {} // hold in infinite loop - } + // initialize the transceiver on the SPI bus + if (!radio.begin()) { + Serial.println(F("radio hardware is not responding!!")); + while (1) { } // hold in infinite loop + } - rfm7x_io_init(); - spi_init(); - if (rfm7x_is_present()) { - Serial.println("RFM7X connected, initializing"); - //this code initializes the required registers for the clones. Especially bank1 - rfm7x_init(); - delay(2); - rfm7x_toggle_reg4(); - delay(1); - } + rfm7x_io_init(); + spi_init(); + if (rfm7x_is_present()) { + Serial.println("RFM7X connected, initializing"); + //this code initializes the required registers for the clones. Especially bank1 + rfm7x_init(); + delay(2); + rfm7x_toggle_reg4(); + delay(1); + } - // print example's introductory prompt - Serial.println(F("RF24/examples/rfm7xAndBk242xCompatiblity")); + // print example's introductory prompt + Serial.println(F("RF24/examples/rfm7xAndBk242xCompatiblity")); - // To set the radioNumber via the Serial monitor on startup - Serial.println(F("Which radio is this? Enter '0' or '1'. Defaults to '0'")); - while (!Serial.available()) { - // wait for user input - } - char input = Serial.parseInt(); - radioNumber = input == 1; - Serial.print(F("radioNumber = ")); - Serial.println((int)radioNumber); + // To set the radioNumber via the Serial monitor on startup + Serial.println(F("Which radio is this? Enter '0' or '1'. Defaults to '0'")); + while (!Serial.available()) { + // wait for user input + } + char input = Serial.parseInt(); + radioNumber = input == 1; + Serial.print(F("radioNumber = ")); + Serial.println((int)radioNumber); - // role variable is hardcoded to RX behavior, inform the user of this - Serial.println(F("*** PRESS 'T' to begin transmitting to the other node")); + // role variable is hardcoded to RX behavior, inform the user of this + Serial.println(F("*** PRESS 'T' to begin transmitting to the other node")); - // Set the PA Level low to try preventing power supply related problems - // because these examples are likely run with nodes in close proximity to - // each other. - radio.setPALevel(RF24_PA_LOW); // RF24_PA_MAX is default. + // Set the PA Level low to try preventing power supply related problems + // because these examples are likely run with nodes in close proximity to + // each other. + radio.setPALevel(RF24_PA_LOW); // RF24_PA_MAX is default. - // save on transmission time by setting the radio to only transmit the - // number of bytes we need to transmit a float - radio.setPayloadSize(sizeof(payload)); // float datatype occupies 4 bytes + // save on transmission time by setting the radio to only transmit the + // number of bytes we need to transmit a float + radio.setPayloadSize(sizeof(payload)); // float datatype occupies 4 bytes - // set the TX address of the RX node into the TX pipe - radio.openWritingPipe(address[radioNumber]); // always uses pipe 0 + // set the TX address of the RX node into the TX pipe + radio.openWritingPipe(address[radioNumber]); // always uses pipe 0 - // set the RX address of the TX node into a RX pipe - radio.openReadingPipe(1, address[!radioNumber]); // using pipe 1 + // set the RX address of the TX node into a RX pipe + radio.openReadingPipe(1, address[!radioNumber]); // using pipe 1 - // additional setup specific to the node's role - if (role) { - radio.stopListening(); // put radio in TX mode - } else { - radio.startListening(); // put radio in RX mode - } + // additional setup specific to the node's role + if (role) { + radio.stopListening(); // put radio in TX mode + } else { + radio.startListening(); // put radio in RX mode + } - // For debugging info - // printf_begin(); // needed only once for printing details - // radio.printDetails(); // (smaller) function that prints raw register values - // radio.printPrettyDetails(); // (larger) function that prints human readable data + // For debugging info + // printf_begin(); // needed only once for printing details + // radio.printDetails(); // (smaller) function that prints raw register values + // radio.printPrettyDetails(); // (larger) function that prints human readable data } // setup diff --git a/examples/rfm7xAndBk242xCompatiblity/rfm7x_config.h b/examples/rfm7xAndBk242xCompatiblity/rfm7x_config.h index e4de069f0..269229fbb 100644 --- a/examples/rfm7xAndBk242xCompatiblity/rfm7x_config.h +++ b/examples/rfm7xAndBk242xCompatiblity/rfm7x_config.h @@ -3,12 +3,12 @@ #define RFM7x_MODULECHIP_USED 3 // 0 // BK2401 ??? // same as BK2421 without 2 mbps data-rate -// 1 // BK2421 aka RFM70 +// 1 // BK2421 aka RFM70 // 2 // BK2423 aka RFM73 // usually full component COBs - (VDDPA path present) - mostly 0.6$ "power enhanced" mini-modules on aliexpress // 3 // BK2425 aka RFM75 // pinout clearly suggests that, it is well known "COB-with-missing-components-module" nrf24l01+ fakes // 4 // BK2411/BK2412 // those are especially designed as an nrf24L01 (without +) fake (green PCB with 5 row header), but none of them can be found // NOT TESTED // 5 // BK5811 // 5.1/5.8GHz RF chip // NOT TESTED - + // bk2491 is probably a canceled chip, which name appears as a title of various number of datasheets // bk2461 // bk2535 // bk2533 // undocumented SOC // bk2433 // bk2451 // bk2452 // undocumented SOCs with usb @@ -24,20 +24,20 @@ #define RFM7x_USE_PIPE0_ADDRESS_FOR_TX_ADDRESS // initialize TX address with the data from PIPE0_RX_ADDRESS // those have to be the same in AUTO_ACK mode // RFM7x_TX_ADDRESS is ignored #define RFM7x_DO_NOT_INITIALIZE_RX_PAYLOAD_LEN_REGS // only 2 bytes gain on avr // by omiting initialization of pyload length registers and dummy bytes -#define RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS // only 8 bytes gain on avr // by omiting initialization of payload length, pipe 2-5 addr, and dummy bytes +#define RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS // only 8 bytes gain on avr // by omiting initialization of payload length, pipe 2-5 addr, and dummy bytes #define RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH // currently workaround rfm7x_reg_buff_write_P() function is used that might make bigger code in some cases /**************** hardcoded config of bank0 registers ****************/ //comment out to free space in init_struct // LSB byte is first -#define RFM7x_PIPE0_RX_ADDRESS 0x34, 0x43, 0x10, 0x10, 0x01 // have to be the same as TX_ADDRESS in order to communiacate in AUTO_ACK mode. +#define RFM7x_PIPE0_RX_ADDRESS 0x34, 0x43, 0x10, 0x10, 0x01 // have to be the same as TX_ADDRESS in order to communiacate in AUTO_ACK mode. //#define RFM7x_PIPE1_RX_ADDRESS 0x11, 0x02, 0x03, 0x04, 0x05 //#define RFM7x_TX_ADDRESS 0x34, 0x43, 0x10, 0x10, 0x01 // have to be the same as PIPE0_RX_ADDRESS in order to communiacate in AUTO_ACK mode. // do not comment out config below -#define RFM7x_PIPE0_RX_ADDRESS_SIZE 5 +#define RFM7x_PIPE0_RX_ADDRESS_SIZE 5 #define RFM7x_PIPE1_RX_ADDRESS_SIZE 5 #define RFM7x_TX_ADDRESS_SIZE 5 //size of the vectors above @@ -52,20 +52,20 @@ #define RFM7x_BANK0_CONF_PWR_UP 1 // usually we want to power chip up during initialization // in some rare cases (battery operated) it have to be initialized in PWR_DOWN just to save some power -// 1: POWER UP -// 0: POWER DOWN +// 1: POWER UP +// 0: POWER DOWN #define RFM7x_BANK0_CONF_EN_CRC 1 // Enable CRC. Forced high if one of the bits in the EN_AA is high // 0: CRC disabled // 1: CRC enabled -#define RFM7x_BANK0_CONF_CRCO 1 +#define RFM7x_BANK0_CONF_CRCO 1 // CRC encoding scheme // '0' - 1 byte // '1' - 2 bytes -#define RFM7x_BANK0_CONF_MASK_RX_DR 1 +#define RFM7x_BANK0_CONF_MASK_RX_DR 1 // Mask interrupt caused by RX_DR // 1: Interrupt not reflected on the IRQ pin // 0: Reflect RX_DR as active low interrupt on the IRQ pin @@ -108,7 +108,7 @@ #define RFM7x_BANK0_CONF_ARD 15 // Auto Retransmission Delay (Delay defined from end of transmission to start of next transmission) -// according to nrf24l01+ datasheet ARD should be 500us or more if ACK payload mode is used (W_ACK_PAYLOAD command) +// according to nrf24l01+ datasheet ARD should be 500us or more if ACK payload mode is used (W_ACK_PAYLOAD command) // 250kbps mode requires 500us retransmit delay even if ACK payload is not used but is activated // 0 - Wait 250 us // 1 - Wait 500 us @@ -121,7 +121,6 @@ // 1 - Up to 1 Re-Transmission on fail of AA // 15 - Up to 15 Re-Transmission on fail of AA - #define RFM7x_BANK0_CONF_RF_CH 10 // select used frequency channel in 1 MHz steps (kb2411 starts at 2397, rest at 2400) // beken and hoperf datasheets says about 83 channels available, but electrical specification (except bk2411) says about 127 channels @@ -216,11 +215,11 @@ // magic values that have to be written into read-only status registers, otherwise chips will refuse to work after some time or a few power cycles -#define RFM7x_BANK0_REG_STATUS 0x70 +#define RFM7x_BANK0_REG_STATUS 0x70 // The default value that comes from all example codes (0x07) might be intended as a fix for hidden silicon bug, or just erratum from 0x70 that should clear all pending flags -#define RFM7x_BANK0_REG_OBSERVE_TX 0x00 -#define RFM7x_BANK0_REG_CD 0x00 +#define RFM7x_BANK0_REG_OBSERVE_TX 0x00 +#define RFM7x_BANK0_REG_CD 0x00 #define RFM7x_BANK0_REG_FIFO_STATUS 0x00 /******** bk2421/01 aka RFM70 - compatibility and sensitivity *******/ @@ -239,7 +238,7 @@ // 5 // "single carrier mode" from datasheet - constant wave mode (after translation from chienglish) // instead of 'PLL_LOCK' ?? // testing purposes only // 6 // NOT DOCUMENTED NOR TESTED // value for rfm73 in replace manual (rfm70->rfm73) // 7 // NOT DOCUMENTED NOR TESTED // undocumented "high power mode" up to 15dBm (rfm73/bk2423) -// 8 // NOT DOCUMENTED NOR TESTED // (7) mixed with (6) - (0x0B -> 0x1B), (0x9E -> 0xB6) +// 8 // NOT DOCUMENTED NOR TESTED // (7) mixed with (6) - (0x0B -> 0x1B), (0x9E -> 0xB6) // 9 // NOT DOCUMENTED NOR TESTED // (7) mixed with (6) - (0x0B -> 0x1B), (0xBE -> 0xB6), (0x84 -> 0x80) // 10 // NOT DOCUMENTED NOR TESTED // (7) mixed with (6) - (0x0B -> 0x1B), (0xBE -> 0xB6), (0x84 -> 0x82) // 11 // "In order to smooth the use of RF-2400PA" (Inhaos rebrand of bk2421 + PA) @@ -270,28 +269,28 @@ #define RFM70_BANK1_REGD_MODE 0 // 0 // recommended datasheet value -// 1 // NOT DOCUMENTED NOR TESTED // value for rfm73, from replace manual (rfm70->rfm73) // (bank1 is so documented that it might be obtained experimentally) +// 1 // NOT DOCUMENTED NOR TESTED // value for rfm73, from replace manual (rfm70->rfm73) // (bank1 is so documented that it might be obtained experimentally) #define RFM70_BANK1_RAMP_CURVE_MODE 0 // 0 // rfm70/bk2421 // default recommended datasheet value -// 1 // NOT DOCUMENTED NOR TESTED // rfm73 datasheet and power-up value +// 1 // NOT DOCUMENTED NOR TESTED // rfm73 datasheet and power-up value /********************************************************************/ /********** bk2423 aka RFM73 - compatibility and sensitivity ********/ #define RFM73_BANK1_REG3_MODE 0 -// 0 // default recommended value +// 0 // default recommended value // 1 // AN0007 "high power mode" 3-15dBm - may require additional low/band-pass filter for compliance with FCC rules // also "In order to smooth the use of RF-2400PA" (Inhaos rebrand of bk2421 + PA) // 2 // datasheet "reset value" #define RFM73_BANK1_REG4_MODE 1 // literally the worst register - all datasheets/AN's have different "correct" values for this register // 0 // rfm70/bk2421 and rfm73/bk2423 datasheet values // AN0007 and AN0008 "default setting of reg4" -// 1 // replace manual (rfm70->rfm73), also used in all libraries which are not plain conversion from rfm70 // is said to be 3 dB gain in 1MHz and required for proper operation at 2MHz +// 1 // replace manual (rfm70->rfm73), also used in all libraries which are not plain conversion from rfm70 // is said to be 3 dB gain in 1MHz and required for proper operation at 2MHz // 2 // AN0007 "high power mode" up to 15dBm // RF_PWR in bank 0 should be set to 5dBm // may require additional low/band-pass filter for compliance with FCC rules // 3 // (0) mixed with (1) // only obvious parts - (0x0B -> 0x1B), (0xBE -> 0xB6) // 4 // (2) mixed with (1) // only obvious parts - (0x0B -> 0x1B), (0xBE -> 0xB6) -// 5 // (2) mixed with (1) // clear also bit 10 - (0x0B -> 0x1B), (0xBE -> 0xB6), (0x84 -> 0x80) +// 5 // (2) mixed with (1) // clear also bit 10 - (0x0B -> 0x1B), (0xBE -> 0xB6), (0x84 -> 0x80) // 6 // "single carrier mode" from datasheet - constant wave mode (after translation from chienglish) // instead of 'PLL_LOCK' ?? // testing purposes only // 7 // (4) with (0x84 -> 0x82) // 8 // (0) with (0xD9 -> 0xF9) // found in some codes/libs for rfm70/73 @@ -319,7 +318,7 @@ // 0 // RSSI disabled // 1 // RSSI enabled -#define RFM73_RSSI_THRESHOLD_LEVEL 9 // 0-15 +#define RFM73_RSSI_THRESHOLD_LEVEL 9 // 0-15 // in bk2423/rfm73 RSSI level is not linear to threshold level // RSSI levels are different at 250k/1M and 2M air data rate // refering to AN0007, high sense mode affects rssi levels, so the default level is in N/A region // actually not true @@ -338,18 +337,18 @@ #define RFM73_BANK1_REGD_MODE 1 // 0 // rfm70/bk2421 and rfm73/bk2423 datasheet values, also initial value that can be read after module power-up -// 1 // replace manual (rfm70->rfm73), also used in all libraries which are not plain conversion from rfm70 // it is said to be 3 dB gain in 1MHz and required for proper operation at 2MHz +// 1 // replace manual (rfm70->rfm73), also used in all libraries which are not plain conversion from rfm70 // it is said to be 3 dB gain in 1MHz and required for proper operation at 2MHz #define RFM73_BANK1_RAMP_CURVE_MODE 1 // 0 // value recommended in rfm73/bk2423 datasheets, also the initial value that can be read after module power-up -// 1 // value recommended in rfm70/bk2421 datasheets and replace manual (rfm70->rfm73), also used in all libraries +// 1 // value recommended in rfm70/bk2421 datasheets and replace manual (rfm70->rfm73), also used in all libraries /********************************************************************/ /********** bk2425 aka RFM75 - compatibility and sensitivity ********/ #define RFM75_BANK1_REG3_MODE 0 -// 0 // recommended bk2425/rfm75 value +// 0 // recommended bk2425/rfm75 value // 1 // datasheet "reset value" // 3 // NOT DOCUMENTED NOR TESTED // (0) with undocumented high power mode bits set // no high power ?? // 4 // adapt rfm73 value from replace manual (rfm70->rfm73) @@ -358,7 +357,7 @@ #define RFM75_BANK1_REG4_MODE 0 // 0 // recommended value for 1Mbps // 1 // recommended value for 2Mbps -// 2 // recommended value for 250kbps +// 2 // recommended value for 250kbps // 3 // "single carrier mode" from datasheet - constant wave mode (after translation from chienglish) // instead of 'PLL_LOCK' ?? // 4 // NOT DOCUMENTED NOR TESTED // (0) with adapted rfm73 "high power" mode (AN0007) // clear undocumented bit 9 // no high power ?? // 5 // NOT DOCUMENTED NOR TESTED // (1) with adapted rfm73 "high power" mode (AN0007) // clear undocumented bit 9 // no high power ?? @@ -388,8 +387,8 @@ // 8 // rfm73 value adapted for 1Mbps // RSSI with selectable threshold // 9 // rfm73 value adapted for 2Mbps and 250kbps // RSSI with selectable threshold -#define RFM75_UNDOCUMENTED_RSSI_THRESHOLD_LEVEL 9 // 0-15? // value is left shifted by 2 into MSB // 9 -// officially there is no RSSI threshold for this chip, but obviously it's so undocumented that it could be implemented +#define RFM75_UNDOCUMENTED_RSSI_THRESHOLD_LEVEL 9 // 0-15? // value is left shifted by 2 into MSB // 9 +// officially there is no RSSI threshold for this chip, but obviously it's so undocumented that it could be implemented #define RFM75_BANK1_REGC_MODE 1 // 0 // rfm70/bk2421 compatible // 120 us PLL settling time @@ -397,7 +396,7 @@ // 2 // rfm73 adapt // initial value after power up // 120 us PLL settling time // not used/mentioned anywhere // 3 // rfm73 adapt // initial value after power up // 130 us PLL settling time // not used/mentioned anywhere -#define RFM75_CONFIG_COMPATIBLE_MODE 0 //0 works when rfm receives and nrf24 transmits +#define RFM75_CONFIG_COMPATIBLE_MODE 0 //0 works when rfm receives and nrf24 transmits // transmitter and receiver have to use the same mode, otherwise transmitter is seeing 100% packet loss // This field probably controls the inversion of NO_ACK bit in the air payload in DPL mode // 0:Static compatible // SI24R1 compatible @@ -409,7 +408,7 @@ #define RFM75_BANK1_RAMP_CURVE_MODE 0 // 0 // recommended bk2425/rfm75 value -// 1 // adapt rfm73 datasheet value +// 1 // adapt rfm73 datasheet value /*********************************************************************/ @@ -431,15 +430,15 @@ // Crystal offset compensation, center at 8. // User can adjust this register to compensate crystal offset -#define BK2411_RSSI_THRESHOLD_LEVEL 9 // 0-15 -// 0: -97 dBm, 2 dB/step, 15: -67 dBm +#define BK2411_RSSI_THRESHOLD_LEVEL 9 // 0-15 +// 0: -97 dBm, 2 dB/step, 15: -67 dBm #define BK2411_BANK1_REGC_MODE 0 // 0 // default recommended value // 300 us PLL, 110 us ramping // 1 // NOT TESTED // bk2421 compatible // 120 us PLL, 40 us ramping // 2 // PLL lock and ramping time configurable below -#define BK2411_TX_LOCK_SEL 1 +#define BK2411_TX_LOCK_SEL 1 // Tx PLL lock time selection // 0: 120 us, 1: 200 us, 2: 300 us, 3: 500 us @@ -448,8 +447,8 @@ // 0: 10 us, 1: 20us, 2: 30 us, \85 , 15: 160 us #define BK2411_BANK1_REGD_MODE 0 -// 0 // reccomended value for 1 mpbs // <100ppm crystal accurancy, GFSK, BT = 1 -// 1 // recommended value for 2 mbps // <5ppm (!) crystal accurancy, FSK +// 0 // reccomended value for 1 mpbs // <100ppm crystal accurancy, GFSK, BT = 1 +// 1 // recommended value for 2 mbps // <5ppm (!) crystal accurancy, FSK // 2 // (1) with <100ppm crystal accurancy // 3 // (0) in long payload mode (255 bytes) // 4 // (1) in long payload mode (255 bytes) @@ -466,7 +465,7 @@ // 0: GFSK mode // cleaner spectrum // 1: FSK mode // better sensitivity -#define BK2411_GFSK_BT 1 +#define BK2411_GFSK_BT 1 // GFSK filter bandwidth ?? // BT = filter\92s -3dB BW / data rate // 0: BT = 1 // less adjecent bits interference, better sensitivity // 1: BT = 0.5 // less out of band emmisions @@ -483,13 +482,13 @@ /*************** bk5811 - compatibility and sensitivity **************/ -#define BK5811_BANK1_DEFAULT_BAND 1 +#define BK5811_BANK1_DEFAULT_BAND 1 // reg 0, 2 and 3 // 0: tune to 5.1GHz band // 1: tune to 5.8GHz band #define BK5811_BANK1_REG4_MODE 0 -// 0: default recommended value +// 0: default recommended value // 1: "single carrier mode" - constant wave mode (after translation from chienglish) #define BK5811_RSSI_THRESHOLD_LEVEL 9 // 0-15 diff --git a/examples/rfm7xAndBk242xCompatiblity/rfm7x_hardware.cpp b/examples/rfm7xAndBk242xCompatiblity/rfm7x_hardware.cpp index 925ad4f97..fe884896b 100644 --- a/examples/rfm7xAndBk242xCompatiblity/rfm7x_hardware.cpp +++ b/examples/rfm7xAndBk242xCompatiblity/rfm7x_hardware.cpp @@ -1,177 +1,180 @@ #if defined(ARDUINO) - #include - #include +#include +#include #elif defined(__AVR_ARCH__) - #include +#include #else - #include +#include #endif #include "rfm7x_hardware.h" void rfm7x_io_init(void) //hardcoded at the moment { - RFM7x_CSN_HI; - RFM7x_CE_LOW; + RFM7x_CSN_HI; + RFM7x_CE_LOW; #if defined(USE_EXAMPLE_SPI_MEGA328) - //set ce to output - //set csn to output + //set ce to output + //set csn to output #elif defined(USE_EXAMPLE_SPI_XMEGA) - //PORTC.DIRSET = PIN4_bm | PIN1_bm; // as output + //PORTC.DIRSET = PIN4_bm | PIN1_bm; // as output #elif defined(USE_EXAMPLE_SPI_STM32F0) - //RCC->AHBENR |= RCC_AHBENR_GPIOAEN; + //RCC->AHBENR |= RCC_AHBENR_GPIOAEN; - //GPIOA->MODER |= (1 << __builtin_ctz(GPIO_MODER_MODER3)) | (1 << __builtin_ctz(GPIO_MODER_MODER4)); // set PA3 and PA4 to output + //GPIOA->MODER |= (1 << __builtin_ctz(GPIO_MODER_MODER3)) | (1 << __builtin_ctz(GPIO_MODER_MODER4)); // set PA3 and PA4 to output #elif defined(USE_EXAMPLE_SPI_ARDUINO) - - pinMode(8,OUTPUT); // ce - pinMode(9,OUTPUT); //csn -#else // soft - //set ce to output - //set csn to output + + pinMode(8, OUTPUT); // ce + pinMode(9, OUTPUT); //csn +#else // soft \ + //set ce to output \ + //set csn to output #endif } void spi_init(void) { #if defined(USE_EXAMPLE_SPI_MEGA328) - DDRB |= (1 << PB3) | (1 << PB5); // configure output pins - PORTB |= (1 << PB4); // pullup miso + DDRB |= (1 << PB3) | (1 << PB5); // configure output pins + PORTB |= (1 << PB4); // pullup miso + + SPCR |= (1 << SPE) | (1 << MSTR); + SPSR |= (1 << SPI2X); - SPCR |= (1 << SPE) | (1 << MSTR); - SPSR |= (1 << SPI2X); - #elif defined(USE_EXAMPLE_SPI_XMEGA) - PORTC.DIRSET = PIN5_bm | PIN7_bm; // sck , mosi - PORTC.PIN6CTRL = PORT_OPC_PULLUP_gc; // pullup miso - SPIC.CTRL = SPI_ENABLE_bm | SPI_MASTER_bm | SPI_MODE_0_gc | SPI_PRESCALER_DIV4_gc; // 32MHz/4 + PORTC.DIRSET = PIN5_bm | PIN7_bm; // sck , mosi + PORTC.PIN6CTRL = PORT_OPC_PULLUP_gc; // pullup miso + SPIC.CTRL = SPI_ENABLE_bm | SPI_MASTER_bm | SPI_MODE_0_gc | SPI_PRESCALER_DIV4_gc; // 32MHz/4 #elif defined(USE_EXAMPLE_SPI_STM32F0) - RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; - GPIOA->MODER |= (2 << __builtin_ctz(GPIO_MODER_MODER5))|(2 << __builtin_ctz(GPIO_MODER_MODER6))|(2 << __builtin_ctz(GPIO_MODER_MODER7)); // PA5, PA6, PA7 as alternate - //GPIOA->AFR[0] &= ~((0x0f << __builtin_ctz(GPIO_AFRL_AFR5))|(0x0f << __builtin_ctz(GPIO_AFRL_AFR6))|(0x0f << __builtin_ctz(GPIO_AFRL_AFR7))); - //GPIOA->AFR[0] |= (0 << __builtin_ctz(GPIO_AFRL_AFR5))|(0 << __builtin_ctz(GPIO_AFRL_AFR6))|(0 << __builtin_ctz(GPIO_AFRL_AFR7)); + RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; + GPIOA->MODER |= (2 << __builtin_ctz(GPIO_MODER_MODER5)) | (2 << __builtin_ctz(GPIO_MODER_MODER6)) | (2 << __builtin_ctz(GPIO_MODER_MODER7)); // PA5, PA6, PA7 as alternate + //GPIOA->AFR[0] &= ~((0x0f << __builtin_ctz(GPIO_AFRL_AFR5))|(0x0f << __builtin_ctz(GPIO_AFRL_AFR6))|(0x0f << __builtin_ctz(GPIO_AFRL_AFR7))); + //GPIOA->AFR[0] |= (0 << __builtin_ctz(GPIO_AFRL_AFR5))|(0 << __builtin_ctz(GPIO_AFRL_AFR6))|(0 << __builtin_ctz(GPIO_AFRL_AFR7)); - GPIOA->OSPEEDR |= (3 << __builtin_ctz(GPIO_OSPEEDR_OSPEEDR5))|(3 << __builtin_ctz(GPIO_OSPEEDR_OSPEEDR7)); // set SCK and MOSI into high speed mode - GPIOA->PUPDR |= (1 << __builtin_ctz(GPIO_PUPDR_PUPDR6)); // pullup miso + GPIOA->OSPEEDR |= (3 << __builtin_ctz(GPIO_OSPEEDR_OSPEEDR5)) | (3 << __builtin_ctz(GPIO_OSPEEDR_OSPEEDR7)); // set SCK and MOSI into high speed mode + GPIOA->PUPDR |= (1 << __builtin_ctz(GPIO_PUPDR_PUPDR6)); // pullup miso - SPI1->CR2 |= SPI_CR2_FRXTH; // RXNE treshold at 1 byte - SPI1->CR1 = SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_SPE | (2 << __builtin_ctz(SPI_CR1_BR)) | SPI_CR1_MSTR; // soft NSS force to master, enable, PCLK/8, master - //SSOE ??? + SPI1->CR2 |= SPI_CR2_FRXTH; // RXNE treshold at 1 byte + SPI1->CR1 = SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_SPE | (2 << __builtin_ctz(SPI_CR1_BR)) | SPI_CR1_MSTR; // soft NSS force to master, enable, PCLK/8, master + //SSOE ??? #elif defined(USE_EXAMPLE_SPI_ARDUINO) - SPI.begin(); - - // necessary? - //SPI.setBitOrder(MSBFIRST); - //SPI.setDataMode(SPI_MODE0); - SPI.setClockDivider(SPI_CLOCK_DIV2); + SPI.begin(); + + // necessary? + //SPI.setBitOrder(MSBFIRST); + //SPI.setDataMode(SPI_MODE0); + SPI.setClockDivider(SPI_CLOCK_DIV2); #else - // can be optimized into single write if port wiring allows - SOFT_SPI_SCK_DIRSET(); - SOFT_SPI_MOSI_DIRSET(); - SOFT_SPI_MISO_DIRSET(); // always input after POR, can be commented out - SOFT_SPI_MISO_PULLUP_SET(); // ?? + // can be optimized into single write if port wiring allows + SOFT_SPI_SCK_DIRSET(); + SOFT_SPI_MOSI_DIRSET(); + SOFT_SPI_MISO_DIRSET(); // always input after POR, can be commented out + SOFT_SPI_MISO_PULLUP_SET(); // ?? #endif } uint8_t spi_rw(uint8_t data) { #if defined(USE_EXAMPLE_SPI_MEGA328) - SPDR = data; - while (!(SPSR & (1 << SPIF))); + SPDR = data; + while (!(SPSR & (1 << SPIF))) + ; + + return SPDR; - return SPDR; - #elif defined(USE_EXAMPLE_SPI_XMEGA) - SPIC.DATA = dat; - while(!(SPIC.STATUS & (1<<7))); // no SPIF defined + SPIC.DATA = dat; + while (!(SPIC.STATUS & (1 << 7))) + ; // no SPIF defined - return SPIC.DATA; + return SPIC.DATA; #elif defined(USE_EXAMPLE_SPI_STM32F0) - - while( (SPI1->SR & SPI_SR_BSY) ); - *(uint8_t *)&(SPI1->DR) = data; // cast to make 8 bit transfer and thus transmit only 8bit frame - while( !(SPI1->SR & SPI_SR_RXNE) ); - data = SPI1->DR; - return data; + + while ((SPI1->SR & SPI_SR_BSY)) + ; + *(uint8_t*)&(SPI1->DR) = data; // cast to make 8 bit transfer and thus transmit only 8bit frame + while (!(SPI1->SR & SPI_SR_RXNE)) + ; + data = SPI1->DR; + return data; #elif defined(USE_EXAMPLE_SPI_ARDUINO) - uint8_t tmp = SPI.transfer(data); - return tmp; + uint8_t tmp = SPI.transfer(data); + return tmp; #else - for(uint_fast8_t i = 0; i < 8; i++) - { - if (data & 0x80) - SOFT_SPI_MOSI_HI(); - else - SOFT_SPI_MOSI_LO(); - - //_delay_us(0.125); - //_delay_us(1); - delayMicroseconds(1); - SOFT_SPI_SCK_HI(); - delayMicroseconds(1); - // _delay_us(1); - - data <<= 1; - - if (SOFT_SPI_MISO_READ()) - data |= 0x01; // data++ - - // _delay_us(0.125); - delayMicroseconds(1); - SOFT_SPI_SCK_LO(); - // _delay_us(0.125); - delayMicroseconds(1); - } - - return data; -#endif + for (uint_fast8_t i = 0; i < 8; i++) { + if (data & 0x80) + SOFT_SPI_MOSI_HI(); + else + SOFT_SPI_MOSI_LO(); + + //_delay_us(0.125); + //_delay_us(1); + delayMicroseconds(1); + SOFT_SPI_SCK_HI(); + delayMicroseconds(1); + // _delay_us(1); + + data <<= 1; + + if (SOFT_SPI_MISO_READ()) + data |= 0x01; // data++ + + // _delay_us(0.125); + delayMicroseconds(1); + SOFT_SPI_SCK_LO(); + // _delay_us(0.125); + delayMicroseconds(1); + } + + return data; +#endif } void spi_reg_write(uint8_t reg, uint8_t dat) { - spi_rw(reg); - spi_rw(dat); + spi_rw(reg); + spi_rw(dat); } uint8_t spi_reg_read(uint8_t reg) { - uint8_t tmp; - - spi_rw(reg); - tmp = spi_rw(0); - - return tmp; // spi_rw(spi_rw(reg)) + uint8_t tmp; + + spi_rw(reg); + tmp = spi_rw(0); + + return tmp; // spi_rw(spi_rw(reg)) } -void spi_reg_buff_write(uint8_t reg, uint8_t *buff, uint8_t len) +void spi_reg_buff_write(uint8_t reg, uint8_t* buff, uint8_t len) { - spi_rw(reg); - - for(uint8_t i=0; i Date: Fri, 26 Mar 2021 16:07:26 +0100 Subject: [PATCH 3/5] more formatting --- examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp | 942 +++++++++--------- examples/rfm7xAndBk242xCompatiblity/rfm7x.h | 8 +- .../rfm7xAndBk242xCompatiblity.ino | 106 +- .../rfm7x_hardware.cpp | 192 ++-- 4 files changed, 624 insertions(+), 624 deletions(-) diff --git a/examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp b/examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp index 8c687dd37..7c59f7b7b 100644 --- a/examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp +++ b/examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp @@ -19,20 +19,20 @@ // workaround for ATOMIC_BLOCK __attribute__((always_inline)) inline int __int_disable_irq(void) { - int primask; - asm volatile("mrs %0, PRIMASK\n" - : "=r"(primask)); - asm volatile("cpsid i\n"); - return primask & 1; +int primask; +asm volatile("mrs %0, PRIMASK\n" + : "=r"(primask)); +asm volatile("cpsid i\n"); +return primask & 1; } __attribute__((always_inline)) inline void __int_restore_irq(int* primask) { - if (!(*primask)) { - asm volatile("" :: - : "memory"); - asm volatile("cpsie i\n"); - } +if (!(*primask)) { + asm volatile("" :: + : "memory"); + asm volatile("cpsie i\n"); +} } #define CRITICAL_SECTION for (int primask_save __attribute__((__cleanup__(__int_restore_irq))) = __int_disable_irq(), __ToDo = 1; __ToDo; __ToDo = 0) @@ -49,59 +49,59 @@ const __flash uint8_t rfm7x_init_struct[] = const uint8_t rfm7x_init_struct[] = // generic for all architectures // table will be placed in SRAM if your mcu doesn't have unified memory space (flash + ram) #endif { - ////////////////////////////////////////// bank 1 initialization registers ////////////////////////////////////////// - - RFM7x_BANK1_REG0, - RFM7x_BANK1_REG1, - RFM7x_BANK1_REG2, - RFM7x_BANK1_REG3, - RFM7x_BANK1_REG4, - RFM7x_BANK1_REG5, - RFM7x_BANK1_REG6, - RFM7x_BANK1_REG7, - RFM7x_BANK1_REG8, - RFM7x_BANK1_REG9, - RFM7x_BANK1_REGA, - RFM7x_BANK1_REGB, - RFM7x_BANK1_REGC, - RFM7x_BANK1_REGD, - RFM7x_BANK1_RAMP_CURVE, +////////////////////////////////////////// bank 1 initialization registers ////////////////////////////////////////// + +RFM7x_BANK1_REG0, +RFM7x_BANK1_REG1, +RFM7x_BANK1_REG2, +RFM7x_BANK1_REG3, +RFM7x_BANK1_REG4, +RFM7x_BANK1_REG5, +RFM7x_BANK1_REG6, +RFM7x_BANK1_REG7, +RFM7x_BANK1_REG8, +RFM7x_BANK1_REG9, +RFM7x_BANK1_REGA, +RFM7x_BANK1_REGB, +RFM7x_BANK1_REGC, +RFM7x_BANK1_REGD, +RFM7x_BANK1_RAMP_CURVE, ////////////////////////////////////////// bank 0 initialization registers ////////////////////////////////////////// #ifndef RFM7x_DO_NOT_INITIALIZE_BANK0 - RFM7x_BANK0_REG_CONFIG, // PTX/PRX mode - doesn't care, it will be set later with rest commands - RFM7x_BANK0_REG_EN_AA, - RFM7x_BANK0_REG_EN_RXADDR, - RFM7x_BANK0_REG_SETUP_AW, - RFM7x_BANK0_REG_SETUP_RETR, - RFM7x_BANK0_REG_RF_CH, - RFM7x_BANK0_REG_RF_SETUP, - - RFM7x_BANK0_REG_STATUS, // status register that have to be initialized - not documented - RFM7x_BANK0_REG_OBSERVE_TX, // status register that have to be initialized - not documented - RFM7x_BANK0_REG_CD, // status register that have to be initialized - not documented +RFM7x_BANK0_REG_CONFIG, // PTX/PRX mode - doesn't care, it will be set later with rest commands +RFM7x_BANK0_REG_EN_AA, +RFM7x_BANK0_REG_EN_RXADDR, +RFM7x_BANK0_REG_SETUP_AW, +RFM7x_BANK0_REG_SETUP_RETR, +RFM7x_BANK0_REG_RF_CH, +RFM7x_BANK0_REG_RF_SETUP, + +RFM7x_BANK0_REG_STATUS, // status register that have to be initialized - not documented +RFM7x_BANK0_REG_OBSERVE_TX, // status register that have to be initialized - not documented +RFM7x_BANK0_REG_CD, // status register that have to be initialized - not documented #ifndef RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS - 0xE7, // pipe0 default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined - 0xC2, // pipe1 default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined +0xE7, // pipe0 default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined +0xC2, // pipe1 default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined - RFM7x_PIPE2_RX_ADDRESS, // pipe 2 address // LSB only - RFM7x_PIPE3_RX_ADDRESS, // pipe 3 address // LSB only - RFM7x_PIPE4_RX_ADDRESS, // pipe 4 address // LSB only - RFM7x_PIPE5_RX_ADDRESS, // pipe 5 address // LSB only +RFM7x_PIPE2_RX_ADDRESS, // pipe 2 address // LSB only +RFM7x_PIPE3_RX_ADDRESS, // pipe 3 address // LSB only +RFM7x_PIPE4_RX_ADDRESS, // pipe 4 address // LSB only +RFM7x_PIPE5_RX_ADDRESS, // pipe 5 address // LSB only #endif #if !defined(RFM7x_DO_NOT_INITIALIZE_RX_PAYLOAD_LEN_REGS) && !defined(RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS) - 0xE7, // TX default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined +0xE7, // TX default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined - RFM7x_PIPE0_RX_PAYLOAD_LEN, // pipe 0 - payload length // 0 equals to dynamic payload ?? - RFM7x_PIPE1_RX_PAYLOAD_LEN, // pipe 1 - payload length // 0 equals to dynamic payload ?? - RFM7x_PIPE2_RX_PAYLOAD_LEN, // pipe 2 - payload length // 0 equals to dynamic payload ?? - RFM7x_PIPE3_RX_PAYLOAD_LEN, // pipe 3 - payload length // 0 equals to dynamic payload ?? - RFM7x_PIPE4_RX_PAYLOAD_LEN, // pipe 4 - payload length // 0 equals to dynamic payload ?? - RFM7x_PIPE5_RX_PAYLOAD_LEN, // pipe 5 - payload length // 0 equals to dynamic payload ?? +RFM7x_PIPE0_RX_PAYLOAD_LEN, // pipe 0 - payload length // 0 equals to dynamic payload ?? +RFM7x_PIPE1_RX_PAYLOAD_LEN, // pipe 1 - payload length // 0 equals to dynamic payload ?? +RFM7x_PIPE2_RX_PAYLOAD_LEN, // pipe 2 - payload length // 0 equals to dynamic payload ?? +RFM7x_PIPE3_RX_PAYLOAD_LEN, // pipe 3 - payload length // 0 equals to dynamic payload ?? +RFM7x_PIPE4_RX_PAYLOAD_LEN, // pipe 4 - payload length // 0 equals to dynamic payload ?? +RFM7x_PIPE5_RX_PAYLOAD_LEN, // pipe 5 - payload length // 0 equals to dynamic payload ?? - RFM7x_BANK0_REG_FIFO_STATUS, // status register that have to be initialized - not documented +RFM7x_BANK0_REG_FIFO_STATUS, // status register that have to be initialized - not documented #endif //0x00, // dummy @@ -113,13 +113,13 @@ const uint8_t rfm7x_init_struct[] = // generic for all architectures // table wi //RFM7x_BANK0_REG_FEATURE, #if defined(RFM7x_TX_ADDRESS) && !defined(RFM7x_USE_PIPE0_ADDRESS_FOR_TX_ADDRESS) - RFM7x_TX_ADDRESS, +RFM7x_TX_ADDRESS, #endif #ifdef RFM7x_PIPE0_RX_ADDRESS - RFM7x_PIPE0_RX_ADDRESS, +RFM7x_PIPE0_RX_ADDRESS, #endif #ifdef RFM7x_PIPE1_RX_ADDRESS - RFM7x_PIPE1_RX_ADDRESS, +RFM7x_PIPE1_RX_ADDRESS, #endif #endif //RFM7x_DO_NOT_INITIALIZE_BANK0 @@ -128,92 +128,92 @@ const uint8_t rfm7x_init_struct[] = // generic for all architectures // table wi void rfm7x_init(void) { #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION +CRITICAL_SECTION #endif - { +{ #if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - const __flash uint8_t* p_init_struct = rfm7x_init_struct; + const __flash uint8_t* p_init_struct = rfm7x_init_struct; #else - const uint8_t* p_init_struct = rfm7x_init_struct; + const uint8_t* p_init_struct = rfm7x_init_struct; #endif - if ((0x80 & rfm7x_reg_read(RFM7x_REG_STATUS)) == 0) - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // select bank 1 + if ((0x80 & rfm7x_reg_read(RFM7x_REG_STATUS)) == 0) + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // select bank 1 - for (uint_fast8_t i = 0; i < RFM7x_BANK1_ENTRIES; i++) { + for (uint_fast8_t i = 0; i < RFM7x_BANK1_ENTRIES; i++) { #if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - if (i != RFM7x_BANK1_ENTRIES - 1) { - rfm7x_reg_buff_write_P(i, p_init_struct, 4); - p_init_struct += 4; - } else { - rfm7x_reg_buff_write_P(i, p_init_struct, 11); - p_init_struct += 11; - } + if (i != RFM7x_BANK1_ENTRIES - 1) { + rfm7x_reg_buff_write_P(i, p_init_struct, 4); + p_init_struct += 4; + } else { + rfm7x_reg_buff_write_P(i, p_init_struct, 11); + p_init_struct += 11; + } #else - if (i != RFM7x_BANK1_ENTRIES - 1) { - rfm7x_reg_buff_write(i, (uint8_t*)p_init_struct, 4); - p_init_struct += 4; - } else { - rfm7x_reg_buff_write(i, (uint8_t*)p_init_struct, 11); - p_init_struct += 11; - } + if (i != RFM7x_BANK1_ENTRIES - 1) { + rfm7x_reg_buff_write(i, (uint8_t*)p_init_struct, 4); + p_init_struct += 4; + } else { + rfm7x_reg_buff_write(i, (uint8_t*)p_init_struct, 11); + p_init_struct += 11; + } #endif - } + } - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 - rfm7x_reg_write(RFM7x_REG_FEATURE, 0x01); // check if "feature register" is writable before (de)activating it + rfm7x_reg_write(RFM7x_REG_FEATURE, 0x01); // check if "feature register" is writable before (de)activating it - if (!rfm7x_reg_read(RFM7x_REG_FEATURE)) - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x73); // activate feature register if not activated + if (!rfm7x_reg_read(RFM7x_REG_FEATURE)) + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x73); // activate feature register if not activated - for (uint_fast8_t i = 0; i < RFM7x_BANK0_ENTRIES; i++) { - rfm7x_reg_write(i, *p_init_struct++); - } + for (uint_fast8_t i = 0; i < RFM7x_BANK0_ENTRIES; i++) { + rfm7x_reg_write(i, *p_init_struct++); + } #if defined(RFM7x_TX_ADDRESS) || defined(RFM7x_USE_PIPE0_ADDRESS_FOR_TX_ADDRESS) #if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - rfm7x_reg_buff_write_P(RFM7x_REG_TX_ADDR, p_init_struct, RFM7x_TX_ADDRESS_SIZE); + rfm7x_reg_buff_write_P(RFM7x_REG_TX_ADDR, p_init_struct, RFM7x_TX_ADDRESS_SIZE); #else - rfm7x_reg_buff_write(RFM7x_REG_TX_ADDR, (uint8_t*)p_init_struct, RFM7x_TX_ADDRESS_SIZE); + rfm7x_reg_buff_write(RFM7x_REG_TX_ADDR, (uint8_t*)p_init_struct, RFM7x_TX_ADDRESS_SIZE); #endif #ifndef RFM7x_USE_PIPE0_ADDRESS_FOR_TX_ADDRESS - p_init_struct += RFM7x_TX_ADDRESS_SIZE; + p_init_struct += RFM7x_TX_ADDRESS_SIZE; #endif #endif #ifdef RFM7x_PIPE0_RX_ADDRESS #if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - rfm7x_reg_buff_write_P(RFM7x_REG_RX_ADDR_P0, p_init_struct, RFM7x_PIPE0_RX_ADDRESS_SIZE); + rfm7x_reg_buff_write_P(RFM7x_REG_RX_ADDR_P0, p_init_struct, RFM7x_PIPE0_RX_ADDRESS_SIZE); #else - rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P0, (uint8_t*)p_init_struct, RFM7x_PIPE0_RX_ADDRESS_SIZE); + rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P0, (uint8_t*)p_init_struct, RFM7x_PIPE0_RX_ADDRESS_SIZE); #endif - p_init_struct += RFM7x_PIPE0_RX_ADDRESS_SIZE; + p_init_struct += RFM7x_PIPE0_RX_ADDRESS_SIZE; #endif #ifdef RFM7x_PIPE1_RX_ADDRESS #if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - rfm7x_reg_buff_write_P(RFM7x_REG_RX_ADDR_P1, p_init_struct, RFM7x_PIPE1_RX_ADDRESS_SIZE); + rfm7x_reg_buff_write_P(RFM7x_REG_RX_ADDR_P1, p_init_struct, RFM7x_PIPE1_RX_ADDRESS_SIZE); #else - rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P1, (uint8_t*)p_init_struct, RFM7x_PIPE1_RX_ADDRESS_SIZE); + rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P1, (uint8_t*)p_init_struct, RFM7x_PIPE1_RX_ADDRESS_SIZE); #endif #endif #ifdef RFM7x_DO_NOT_INITIALIZE_BANK0 - rfm7x_reg_write(RFM7x_REG_STATUS, RFM7x_BANK0_REG_STATUS); - rfm7x_reg_write(RFM7x_REG_OBSERVE_TX, RFM7x_BANK0_REG_OBSERVE_TX); - rfm7x_reg_write(RFM7x_REG_CD, RFM7x_BANK0_REG_CD); - rfm7x_reg_write(RFM7x_REG_FIFO_STATUS, RFM7x_BANK0_REG_FIFO_STATUS); + rfm7x_reg_write(RFM7x_REG_STATUS, RFM7x_BANK0_REG_STATUS); + rfm7x_reg_write(RFM7x_REG_OBSERVE_TX, RFM7x_BANK0_REG_OBSERVE_TX); + rfm7x_reg_write(RFM7x_REG_CD, RFM7x_BANK0_REG_CD); + rfm7x_reg_write(RFM7x_REG_FIFO_STATUS, RFM7x_BANK0_REG_FIFO_STATUS); #elif defined(RFM7x_DO_NOT_INITIALIZE_RX_PAYLOAD_LEN_REGS) || defined(RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS) - rfm7x_reg_write(RFM7x_REG_FIFO_STATUS, RFM7x_BANK0_REG_FIFO_STATUS); + rfm7x_reg_write(RFM7x_REG_FIFO_STATUS, RFM7x_BANK0_REG_FIFO_STATUS); #endif - rfm7x_reg_write(RFM7x_REG_DYNPD, RFM7x_BANK0_REG_DYNPD); - rfm7x_reg_write(RFM7x_REG_FEATURE, RFM7x_BANK0_REG_FEATURE); - } + rfm7x_reg_write(RFM7x_REG_DYNPD, RFM7x_BANK0_REG_DYNPD); + rfm7x_reg_write(RFM7x_REG_FEATURE, RFM7x_BANK0_REG_FEATURE); +} } #if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) @@ -221,138 +221,138 @@ const __flash uint8_t rfm7x_REG4_toggle_struct[] = #else const uint8_t rfm7x_REG4_toggle_struct[] = #endif - { - 0x06 | RFM7x_BANK1_REG4 // 0x06 will be or'ed with first element (bits 25,26 set) - }; +{ + 0x06 | RFM7x_BANK1_REG4 // 0x06 will be or'ed with first element (bits 25,26 set) +}; void rfm7x_toggle_reg4(void) // MIGHT NOT BE THE CASE FOR BK2411/BK2412/BK5811 { - // one of the chinese documents (rfm73 -> rfm75 migration) says that it should be executed after every PWR_UP, not only during initialization +// one of the chinese documents (rfm73 -> rfm75 migration) says that it should be executed after every PWR_UP, not only during initialization - // 4. RFM75 PowerUP after the first packet of data sent unsuccessful solution - // RFM75 from the POWER DOWN state to switch to POWER UP state, send the first packet is not successful, the reason - // Is the PLL is not locked, the solution is as follows: - // Before transmitting data normally, please follow the following procedure: - // Power up = 1 - // Wait for 2ms - // Operate the bank1 register, writing a 1 to bit 25 of register 04 - // Wait 20us - // Operate the bank1 register, writing a 0 to bit 25 of register 04 - // Wait for 0.5ms. - // Then normal launch. +// 4. RFM75 PowerUP after the first packet of data sent unsuccessful solution +// RFM75 from the POWER DOWN state to switch to POWER UP state, send the first packet is not successful, the reason +// Is the PLL is not locked, the solution is as follows: +// Before transmitting data normally, please follow the following procedure: +// Power up = 1 +// Wait for 2ms +// Operate the bank1 register, writing a 1 to bit 25 of register 04 +// Wait 20us +// Operate the bank1 register, writing a 0 to bit 25 of register 04 +// Wait for 0.5ms. +// Then normal launch. - // AN0008 - // 9. Toggle REG4<25?26>, write 1 to bit25, bit 26, then write 0 to them. +// AN0008 +// 9. Toggle REG4<25?26>, write 1 to bit25, bit 26, then write 0 to them. #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION +CRITICAL_SECTION #endif - { - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 +{ + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 #if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - rfm7x_reg_buff_write_P(0x04, rfm7x_REG4_toggle_struct, 4); - _delay_us(20); // if not required then this function may not be required, so better to leave it here - rfm7x_reg_buff_write_P(0x04, &rfm7x_init_struct[16], 4); + rfm7x_reg_buff_write_P(0x04, rfm7x_REG4_toggle_struct, 4); + _delay_us(20); // if not required then this function may not be required, so better to leave it here + rfm7x_reg_buff_write_P(0x04, &rfm7x_init_struct[16], 4); #else - rfm7x_reg_buff_write(0x04, (uint8_t*)rfm7x_REG4_toggle_struct, 4); - //_delay_us(20); // if not required then this function may not be required, so better to leave it here - rfm7x_reg_buff_write(0x04, (uint8_t*)&rfm7x_init_struct[16], 4); + rfm7x_reg_buff_write(0x04, (uint8_t*)rfm7x_REG4_toggle_struct, 4); + //_delay_us(20); // if not required then this function may not be required, so better to leave it here + rfm7x_reg_buff_write(0x04, (uint8_t*)&rfm7x_init_struct[16], 4); #endif - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 - } + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 +} } void rfm7x_cmd_write(uint8_t reg, uint8_t dat) { #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION +CRITICAL_SECTION #endif - { - RFM7x_CSN_LOW; - rfm7x_spi_rw(reg); - rfm7x_spi_rw(dat); - RFM7x_CSN_HI; - } +{ + RFM7x_CSN_LOW; + rfm7x_spi_rw(reg); + rfm7x_spi_rw(dat); + RFM7x_CSN_HI; +} } uint8_t rfm7x_cmd_read(uint8_t reg) { - uint8_t tmp; +uint8_t tmp; #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION +CRITICAL_SECTION #endif - { - RFM7x_CSN_LOW; - rfm7x_spi_rw(reg); - tmp = rfm7x_spi_rw(0); // rfm7x_spi_rw(rfm7x_spi_rw()) - RFM7x_CSN_HI; - } +{ + RFM7x_CSN_LOW; + rfm7x_spi_rw(reg); + tmp = rfm7x_spi_rw(0); // rfm7x_spi_rw(rfm7x_spi_rw()) + RFM7x_CSN_HI; +} - return tmp; +return tmp; } #ifdef RFM7x_USE_UNIVERSAL_SPI_BUFF_RW_FUNCTIONS void rfm7x_cmd_buff_write(uint8_t reg, uint8_t* buff, uint8_t len) { #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION +CRITICAL_SECTION #endif - { - RFM7x_CSN_LOW; - rfm7x_spi_rw(reg); - rfm7x_buff_write(buff, len); - RFM7x_CSN_HI; - } +{ + RFM7x_CSN_LOW; + rfm7x_spi_rw(reg); + rfm7x_buff_write(buff, len); + RFM7x_CSN_HI; +} } void rfm7x_cmd_buff_read(uint8_t reg, uint8_t* buff, uint8_t len) { #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION +CRITICAL_SECTION #endif - { - RFM7x_CSN_LOW; - rfm7x_spi_rw(reg); - rfm7x_buff_read(buff, len); - RFM7x_CSN_HI; - } +{ + RFM7x_CSN_LOW; + rfm7x_spi_rw(reg); + rfm7x_buff_read(buff, len); + RFM7x_CSN_HI; +} } #else void rfm7x_cmd_buff_write(uint8_t reg, uint8_t* buff, uint8_t len) { #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION +CRITICAL_SECTION #endif - { - RFM7x_CSN_LOW; +{ + RFM7x_CSN_LOW; - rfm7x_spi_rw(reg); + rfm7x_spi_rw(reg); - for (uint_fast8_t i = 0; i < len; i++) - rfm7x_spi_rw(buff[i]); + for (uint_fast8_t i = 0; i < len; i++) + rfm7x_spi_rw(buff[i]); - RFM7x_CSN_HI; - } + RFM7x_CSN_HI; +} } void rfm7x_cmd_buff_read(uint8_t reg, uint8_t* buff, uint8_t len) { #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION +CRITICAL_SECTION #endif - { - RFM7x_CSN_LOW; +{ + RFM7x_CSN_LOW; - rfm7x_spi_rw(reg); + rfm7x_spi_rw(reg); - for (uint_fast8_t i = 0; i < len; i++) - buff[i] = rfm7x_spi_rw(0); + for (uint_fast8_t i = 0; i < len; i++) + buff[i] = rfm7x_spi_rw(0); - RFM7x_CSN_HI; - } + RFM7x_CSN_HI; +} } #endif @@ -360,486 +360,486 @@ void rfm7x_cmd_buff_read(uint8_t reg, uint8_t* buff, uint8_t len) void rfm7x_cmd_buff_write_P(uint8_t reg, const __flash uint8_t* buff, uint8_t len) // __memx ???? { #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION +CRITICAL_SECTION #endif - { - RFM7x_CSN_LOW; +{ + RFM7x_CSN_LOW; - rfm7x_spi_rw(reg); + rfm7x_spi_rw(reg); - for (uint_fast8_t i = 0; i < len; i++) - rfm7x_spi_rw(buff[i]); + for (uint_fast8_t i = 0; i < len; i++) + rfm7x_spi_rw(buff[i]); - RFM7x_CSN_HI; - } + RFM7x_CSN_HI; +} } #endif uint8_t rfm7x_is_present(void) { - uint8_t tmp1, tmp2; - tmp1 = rfm7x_reg_read(RFM7x_REG_STATUS); - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); - tmp2 = rfm7x_reg_read(RFM7x_REG_STATUS); - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); - return (tmp1 ^ tmp2) == 0x80; +uint8_t tmp1, tmp2; +tmp1 = rfm7x_reg_read(RFM7x_REG_STATUS); +rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); +tmp2 = rfm7x_reg_read(RFM7x_REG_STATUS); +rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); +return (tmp1 ^ tmp2) == 0x80; } void rfm7x_power_up(void) { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); - tmp |= 0x02; // set PWR_UP bit - rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); +uint8_t tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); +tmp |= 0x02; // set PWR_UP bit +rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); } void rfm7x_power_down(void) { - RFM7x_CE_LOW; +RFM7x_CE_LOW; - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); - tmp &= 0xFD; // clear PWR_UP bit - rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); +uint8_t tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); +tmp &= 0xFD; // clear PWR_UP bit +rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); } void rfm7x_mode_receive(void) { - RFM7x_CE_LOW; - uint8_t tmp; +RFM7x_CE_LOW; +uint8_t tmp; - //tmp = rfm7x_reg_read(RFM7x_REG_STATUS); - // handle requests here ?? - //rfm7x_reg_write(RFM7x_REG_STATUS, tmp); // clear interrupt requests +//tmp = rfm7x_reg_read(RFM7x_REG_STATUS); +// handle requests here ?? +//rfm7x_reg_write(RFM7x_REG_STATUS, tmp); // clear interrupt requests - rfm7x_reg_write(RFM7x_REG_STATUS, 0x70); // clear interrupt requests +rfm7x_reg_write(RFM7x_REG_STATUS, 0x70); // clear interrupt requests - tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); - tmp |= 0x01; // set RX bit - rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); +tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); +tmp |= 0x01; // set RX bit +rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); #ifdef RFM7x_FLUSH_TX_AND_RX_WHILE_SWITCHING_MODES - rfm7x_cmd_write(RFM7x_CMD_FLUSH_TX, 0); +rfm7x_cmd_write(RFM7x_CMD_FLUSH_TX, 0); #endif - rfm7x_cmd_write(RFM7x_CMD_FLUSH_RX, 0); // it have to be flushed, otherwise doesn't work +rfm7x_cmd_write(RFM7x_CMD_FLUSH_RX, 0); // it have to be flushed, otherwise doesn't work - RFM7x_CE_HI; +RFM7x_CE_HI; } void rfm7x_mode_transmit(void) { - RFM7x_CE_LOW; - uint8_t tmp; +RFM7x_CE_LOW; +uint8_t tmp; - //tmp = rfm7x_reg_read(RFM7x_REG_STATUS); - // handle requests here ?? - //rfm7x_reg_write(RFM7x_REG_STATUS, tmp); // clear interrupt requests +//tmp = rfm7x_reg_read(RFM7x_REG_STATUS); +// handle requests here ?? +//rfm7x_reg_write(RFM7x_REG_STATUS, tmp); // clear interrupt requests - rfm7x_reg_write(RFM7x_REG_STATUS, 0x70); // clear interrupt requests, otherwise further communication is not possible if MAX_RT is asserted +rfm7x_reg_write(RFM7x_REG_STATUS, 0x70); // clear interrupt requests, otherwise further communication is not possible if MAX_RT is asserted - tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); - tmp &= 0xFE; // clear RX bit - rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); +tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); +tmp &= 0xFE; // clear RX bit +rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); #ifdef RFM7x_FLUSH_TX_AND_RX_WHILE_SWITCHING_MODES - rfm7x_cmd_write(RFM7x_CMD_FLUSH_RX, 0); +rfm7x_cmd_write(RFM7x_CMD_FLUSH_RX, 0); #endif - rfm7x_cmd_write(RFM7x_CMD_FLUSH_TX, 0); // it have to be flushed, otherwise chip doesn't work +rfm7x_cmd_write(RFM7x_CMD_FLUSH_TX, 0); // it have to be flushed, otherwise chip doesn't work - RFM7x_CE_HI; +RFM7x_CE_HI; } uint8_t rfm7x_receive(uint8_t* buff) { - uint8_t p = rfm7x_receive_next_pipe(); +uint8_t p = rfm7x_receive_next_pipe(); - if (p == 0x07) - return 0; +if (p == 0x07) + return 0; - uint8_t len = rfm7x_receive_next_length(); +uint8_t len = rfm7x_receive_next_length(); - rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); +rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); - return len; +return len; } void rfm7x_receive_nocheck(uint8_t* buff) { - uint8_t len = rfm7x_receive_next_length(); - rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); +uint8_t len = rfm7x_receive_next_length(); +rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); } uint8_t rfm7x_receive_p_(uint8_t* pipe, uint8_t* buff) { - uint8_t p = rfm7x_receive_next_pipe(); +uint8_t p = rfm7x_receive_next_pipe(); - if (p == 0x07) - return 0; +if (p == 0x07) + return 0; - *pipe = p; - uint8_t len = rfm7x_receive_next_length(); +*pipe = p; +uint8_t len = rfm7x_receive_next_length(); - rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); +rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); - return len; +return len; } uint8_t rfm7x_receive_s(uint8_t* buff, uint8_t length) { - uint8_t p = rfm7x_receive_next_pipe(); +uint8_t p = rfm7x_receive_next_pipe(); - if (p == 0x07) - return p; +if (p == 0x07) + return p; - rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, length); +rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, length); - return p; +return p; } uint8_t rfm7x_receive_f(uint8_t* buff, uint8_t* pipe, uint8_t* length) { - uint8_t p = rfm7x_receive_next_pipe(); +uint8_t p = rfm7x_receive_next_pipe(); - if (p == 0x07) - return 0; +if (p == 0x07) + return 0; - uint8_t len = rfm7x_receive_next_length(); +uint8_t len = rfm7x_receive_next_length(); - *pipe = p; - *length = len; +*pipe = p; +*length = len; - rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); +rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); - return 1; +return 1; } void rfm7x_set_rssi_threshold_step(uint8_t level) { #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION +CRITICAL_SECTION #endif - { - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 +{ + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 - RFM7x_CSN_LOW; - rfm7x_spi_rw(0x05 | 0x20); + RFM7x_CSN_LOW; + rfm7x_spi_rw(0x05 | 0x20); #if (RFM7x_MODULECHIP_USED == 2) - uint8_t tmp; - - switch (level) { - case 0: - tmp = 0x00; - break; - case 1: - tmp = 0x02; - break; - case 2: - tmp = 0x01; - break; - case 3: - tmp = 0x03; - break; - case 4: - tmp = 0x08; - break; - case 5: - tmp = 0x0A; - break; - case 6: - tmp = 0x09; - break; - case 7: - tmp = 0x0B; - break; - case 8: - tmp = 0x04; - break; - case 9: - tmp = 0x06; - break; - case 10: - tmp = 0x05; - break; - case 11: - tmp = 0x07; - break; - case 12: - tmp = 0x0C; - break; - case 13: - tmp = 0x0E; - break; - case 14: - tmp = 0x0D; - break; - case 15: - tmp = 0x0F; - break; - default: - tmp = level; - break; - } - - rfm7x_spi_rw(tmp << 2); + uint8_t tmp; + + switch (level) { + case 0: + tmp = 0x00; + break; + case 1: + tmp = 0x02; + break; + case 2: + tmp = 0x01; + break; + case 3: + tmp = 0x03; + break; + case 4: + tmp = 0x08; + break; + case 5: + tmp = 0x0A; + break; + case 6: + tmp = 0x09; + break; + case 7: + tmp = 0x0B; + break; + case 8: + tmp = 0x04; + break; + case 9: + tmp = 0x06; + break; + case 10: + tmp = 0x05; + break; + case 11: + tmp = 0x07; + break; + case 12: + tmp = 0x0C; + break; + case 13: + tmp = 0x0E; + break; + case 14: + tmp = 0x0D; + break; + case 15: + tmp = 0x0F; + break; + default: + tmp = level; + break; + } + + rfm7x_spi_rw(tmp << 2); #else - rfm7x_spi_rw(level << 2); + rfm7x_spi_rw(level << 2); #endif - rfm7x_spi_rw(rfm7x_init_struct[21]); - rfm7x_spi_rw(rfm7x_init_struct[22]); - rfm7x_spi_rw(rfm7x_init_struct[23]); - RFM7x_CSN_HI; + rfm7x_spi_rw(rfm7x_init_struct[21]); + rfm7x_spi_rw(rfm7x_init_struct[22]); + rfm7x_spi_rw(rfm7x_init_struct[23]); + RFM7x_CSN_HI; - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 - } + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 +} } void rfm7x_set_crc_length(uint8_t len) { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); +uint8_t tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); - tmp &= ~(RFM7x_CONFIG_EN_CRC | RFM7x_CONFIG_CRCO); // clear EN_CRC and CRCO +tmp &= ~(RFM7x_CONFIG_EN_CRC | RFM7x_CONFIG_CRCO); // clear EN_CRC and CRCO - if (len == 0) { - rfm7x_reg_write(RFM7x_REG_EN_AA, 0); // Auto ACK have to be disabled before disabling CRC - rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); - } else { - tmp |= (RFM7x_CONFIG_EN_CRC); // set EN_CRC +if (len == 0) { + rfm7x_reg_write(RFM7x_REG_EN_AA, 0); // Auto ACK have to be disabled before disabling CRC + rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); +} else { + tmp |= (RFM7x_CONFIG_EN_CRC); // set EN_CRC - if (len & 0x02) // if 2 byte encoding scheme is selected, set CRCO - tmp |= (RFM7x_CONFIG_CRCO); + if (len & 0x02) // if 2 byte encoding scheme is selected, set CRCO + tmp |= (RFM7x_CONFIG_CRCO); - //rfm7x_reg_write(RFM7x_REG_EN_AA, 0x3f); //???? - rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); - } + //rfm7x_reg_write(RFM7x_REG_EN_AA, 0x3f); //???? + rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); +} } void rfm7x_set_tx_pwr(uint8_t level) { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); +uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); #if (RFM7x_MODULECHIP_USED == 0) | (RFM7x_MODULECHIP_USED == 1) | (RFM7x_MODULECHIP_USED == 2) // bk2401//bk2421/bk2423 - tmp |= (level << 1); - rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); +tmp |= (level << 1); +rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); #elif (RFM7x_MODULECHIP_USED == 3) // bk2425 - uint8_t txictrl_tmp = 0; +uint8_t txictrl_tmp = 0; - switch (level) { - default: - case 0: // -25 dBm - case 1: // -18 dBm - break; - case 2: // -12 dBm - level -= 1; - txictrl_tmp = 1; - break; +switch (level) { +default: +case 0: // -25 dBm +case 1: // -18 dBm + break; +case 2: // -12 dBm + level -= 1; + txictrl_tmp = 1; + break; - case 3: // -7 dBm - level -= 1; - txictrl_tmp = 2; - break; +case 3: // -7 dBm + level -= 1; + txictrl_tmp = 2; + break; - case 4: // -1 dBm - level -= 1; - break; +case 4: // -1 dBm + level -= 1; + break; - case 5: // 4 dBm - level -= 2; - txictrl_tmp = 7; - break; - } +case 5: // 4 dBm + level -= 2; + txictrl_tmp = 7; + break; +} - tmp |= (level << 1); - rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); +tmp |= (level << 1); +rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION +CRITICAL_SECTION #endif - { - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 +{ + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 - RFM7x_CSN_LOW; - rfm7x_spi_rw(0x04 | 0x20); - rfm7x_spi_rw((rfm7x_init_struct[16] & 0x38) | txictrl_tmp); - rfm7x_spi_rw(rfm7x_init_struct[17]); - rfm7x_spi_rw(rfm7x_init_struct[18]); - rfm7x_spi_rw(rfm7x_init_struct[19]); - RFM7x_CSN_HI; + RFM7x_CSN_LOW; + rfm7x_spi_rw(0x04 | 0x20); + rfm7x_spi_rw((rfm7x_init_struct[16] & 0x38) | txictrl_tmp); + rfm7x_spi_rw(rfm7x_init_struct[17]); + rfm7x_spi_rw(rfm7x_init_struct[18]); + rfm7x_spi_rw(rfm7x_init_struct[19]); + RFM7x_CSN_HI; - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 - } + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 +} #elif (RFM7x_MODULECHIP_USED == 4) | (RFM7x_MODULECHIP_USED == 5) // bk2411//bk2412//bk5811 - tmp |= ((level & 0x03) << 1) | ((level >> 2) << 4); // to optimize ? - rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); +tmp |= ((level & 0x03) << 1) | ((level >> 2) << 4); // to optimize ? +rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); #endif } void rfm7x_set_lna_gain(uint8_t enable) { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); +uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); - if (enable) - tmp |= RFM7x_RF_SETUP_LNA_HCURR; - else - tmp &= ~(RFM7x_RF_SETUP_LNA_HCURR); +if (enable) + tmp |= RFM7x_RF_SETUP_LNA_HCURR; +else + tmp &= ~(RFM7x_RF_SETUP_LNA_HCURR); - rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); +rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); } void rfm7x_set_datarate(uint8_t datarate) { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); +uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); #if (RFM7x_MODULECHIP_USED == 0) | (RFM7x_MODULECHIP_USED == 1) | (RFM7x_MODULECHIP_USED == 4) | (RFM7x_MODULECHIP_USED == 5) // bk2401/bk2421/bk2411/bk2412/bk5811 - tmp &= ~(RFM7x_RF_SETUP_RF_DR_HIGH); +tmp &= ~(RFM7x_RF_SETUP_RF_DR_HIGH); - if (datarate & 0x01) - tmp |= RFM7x_RF_SETUP_RF_DR_HIGH; +if (datarate & 0x01) + tmp |= RFM7x_RF_SETUP_RF_DR_HIGH; - //tmp |= ((datarate & 0x01) << 3); + //tmp |= ((datarate & 0x01) << 3); #elif (RFM7x_MODULECHIP_USED == 2) | (RFM7x_MODULECHIP_USED == 3) // bk2423/bk2425 - tmp &= ~(RFM7x_RF_SETUP_RF_DR_HIGH | RFM7x_RF_SETUP_RF_DR_LOW); +tmp &= ~(RFM7x_RF_SETUP_RF_DR_HIGH | RFM7x_RF_SETUP_RF_DR_LOW); - if (datarate & 0x01) - tmp |= RFM7x_RF_SETUP_RF_DR_HIGH; +if (datarate & 0x01) + tmp |= RFM7x_RF_SETUP_RF_DR_HIGH; - if (datarate & 0x02) - tmp |= RFM7x_RF_SETUP_RF_DR_LOW; +if (datarate & 0x02) + tmp |= RFM7x_RF_SETUP_RF_DR_LOW; - //tmp |= ((datarate & 0x01) << 3)|(((datarate >> 1) & 0x01) << 5); + //tmp |= ((datarate & 0x01) << 3)|(((datarate >> 1) & 0x01) << 5); #endif - rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); +rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); } #if (RFM7x_MODULECHIP_USED == 4) || (RFM7x_MODULECHIP_USED == 5) void rfm7x_enable_rssi_measurements(uint8_t enable) { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); +uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); - if (enable) - tmp |= RFM7x_RF_SETUP_RSSI_EN; - else - tmp &= ~(RFM7x_RF_SETUP_RSSI_EN); +if (enable) + tmp |= RFM7x_RF_SETUP_RSSI_EN; +else + tmp &= ~(RFM7x_RF_SETUP_RSSI_EN); - rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); +rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); } #endif #if (RFM7x_MODULECHIP_USED == 4) void rfm7x_dreg_enable(uint8_t enable) { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); +uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); - if (enable) - tmp |= BK2411_RF_SETUP_DREG_ON; - else - tmp &= ~(BK2411_RF_SETUP_DREG_ON); +if (enable) + tmp |= BK2411_RF_SETUP_DREG_ON; +else + tmp &= ~(BK2411_RF_SETUP_DREG_ON); - rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); +rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); } #endif void rfm7x_enable_pipe_autoack(uint8_t pipe, uint8_t enabled) { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_EN_AA); +uint8_t tmp = rfm7x_reg_read(RFM7x_REG_EN_AA); - tmp &= ~(1 << pipe); +tmp &= ~(1 << pipe); - if (enabled) - tmp |= (1 << pipe); +if (enabled) + tmp |= (1 << pipe); - rfm7x_reg_write(RFM7x_REG_EN_AA, tmp); +rfm7x_reg_write(RFM7x_REG_EN_AA, tmp); } void rfm7x_enable_pipe_receive(uint8_t pipe, uint8_t enabled) { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_EN_RXADDR); +uint8_t tmp = rfm7x_reg_read(RFM7x_REG_EN_RXADDR); - tmp &= ~(1 << pipe); +tmp &= ~(1 << pipe); - if (enabled) - tmp |= (1 << pipe); +if (enabled) + tmp |= (1 << pipe); - rfm7x_reg_write(RFM7x_REG_EN_RXADDR, tmp); +rfm7x_reg_write(RFM7x_REG_EN_RXADDR, tmp); } void rfm7x_enable_dynamic_payload_feature(uint8_t enable) { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); +uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); - tmp &= ~(RFM7x_FEATURE_EN_DPL); +tmp &= ~(RFM7x_FEATURE_EN_DPL); - if (enable) - tmp |= RFM7x_FEATURE_EN_DPL; +if (enable) + tmp |= RFM7x_FEATURE_EN_DPL; - rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); +rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); } void rfm7x_enable_ack_payload_feature(uint8_t enable) { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); +uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); - tmp &= ~(RFM7x_FEATURE_EN_ACK_PAY); +tmp &= ~(RFM7x_FEATURE_EN_ACK_PAY); - if (enable) - tmp |= RFM7x_FEATURE_EN_ACK_PAY; +if (enable) + tmp |= RFM7x_FEATURE_EN_ACK_PAY; - rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); +rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); } void rfm7x_enable_noack_payload_feature(uint8_t enable) { - uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); +uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); - tmp &= ~(RFM7x_FEATURE_EN_DYN_ACK); +tmp &= ~(RFM7x_FEATURE_EN_DYN_ACK); - if (enable) - tmp |= RFM7x_FEATURE_EN_DYN_ACK; +if (enable) + tmp |= RFM7x_FEATURE_EN_DYN_ACK; - rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); +rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); } void rfm7x_set_transmit_address(uint8_t* addr) { - uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); - size += 2; - rfm7x_reg_buff_write(RFM7x_REG_TX_ADDR, addr, size); +uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); +size += 2; +rfm7x_reg_buff_write(RFM7x_REG_TX_ADDR, addr, size); } void rfm7x_open_writing_pipe(uint64_t addr) { - uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); - size += 2; +uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); +size += 2; - //initialize also RX0 ? - rfm7x_reg_buff_write(RFM7x_REG_TX_ADDR, (uint8_t*)&addr, size); // just push that onto the stack, forget about shifts +//initialize also RX0 ? +rfm7x_reg_buff_write(RFM7x_REG_TX_ADDR, (uint8_t*)&addr, size); // just push that onto the stack, forget about shifts } //pipe 1 and 2 (??) void rfm7x_set_receive_address(uint8_t pipe, uint8_t* addr) { - uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); - size += 2; - rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P0 + pipe, addr, size); +uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); +size += 2; +rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P0 + pipe, addr, size); } void rfm7x_open_reading_pipe(uint8_t pipe, uint64_t addr) { - rfm7x_enable_pipe_receive(pipe, 1); +rfm7x_enable_pipe_receive(pipe, 1); - if (pipe >= 2) { - rfm7x_reg_write(RFM7x_REG_RX_ADDR_P0 + pipe, (addr & 0xff)); - } else { - uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); - size += 2; +if (pipe >= 2) { + rfm7x_reg_write(RFM7x_REG_RX_ADDR_P0 + pipe, (addr & 0xff)); +} else { + uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); + size += 2; - rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P0 + pipe, (uint8_t*)&addr, size); // just push that onto the stack, forget about shifts // LE archs only ? - } + rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P0 + pipe, (uint8_t*)&addr, size); // just push that onto the stack, forget about shifts // LE archs only ? +} } #if (RFM7x_MODULECHIP_USED == 5) @@ -849,58 +849,58 @@ const __flash uint8_t rfm7x_swapbandtune_struct[] = #else const uint8_t rfm7x_swapbandtune_struct[] = // generic for all architectures // table will be placed in SRAM if your mcu doesn't have unified memory space (flash + ram) #endif - { +{ #if (BK5811_BANK1_DEFAULT_BAND == 0) // 5.1GHz in rfm7x_init_struct - 0x04, 0x05, 0x78, 0x32, // reg 0 - 0xC0, 0x05, 0xAE, 0x00, // reg 1 // dummy - 0xE8, 0x80, 0x0C, 0xD2, // reg 2 - 0x19, 0x0D, 0x7D, 0x6D // reg 3 + 0x04, 0x05, 0x78, 0x32, // reg 0 + 0xC0, 0x05, 0xAE, 0x00, // reg 1 // dummy + 0xE8, 0x80, 0x0C, 0xD2, // reg 2 + 0x19, 0x0D, 0x7D, 0x6D // reg 3 #else //(BK5811_BANK1_DEFAULT_BAND == 1) // 5.8GHz in rfm7x_init_struct - 0x04, 0x05, 0x78, 0x33, // reg 0 - 0xC0, 0x05, 0xAE, 0x00, // reg 1 // dummy - 0xE8, 0x80, 0x8C, 0xD3, // reg 2 - 0x18, 0x0D, 0x7D, 0x6C // reg 3 + 0x04, 0x05, 0x78, 0x33, // reg 0 + 0xC0, 0x05, 0xAE, 0x00, // reg 1 // dummy + 0xE8, 0x80, 0x8C, 0xD3, // reg 2 + 0x18, 0x0D, 0x7D, 0x6C // reg 3 #endif - }; +}; void bk5811_set_frequency_band(uint8_t range) { #if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - const __flash uint8_t* p_swapband_struct; +const __flash uint8_t* p_swapband_struct; #else - const uint8_t* p_swapband_struct; +const uint8_t* p_swapband_struct; #endif #if (BK5811_BANK1_DEFAULT_BAND == 0) // 5.1GHz in rfm7x_init_struct - if (range) - p_swapband_struct = rfm7x_init_struct; - else - p_swapband_struct = rfm7x_swapbandtune_struct; +if (range) + p_swapband_struct = rfm7x_init_struct; +else + p_swapband_struct = rfm7x_swapbandtune_struct; #else //(BK5811_BANK1_DEFAULT_BAND == 1) // 5.8GHz in rfm7x_init_struct - if (range) - p_swapband_struct = rfm7x_swapbandtune_struct; - else - p_swapband_struct = rfm7x_init_struct; +if (range) + p_swapband_struct = rfm7x_swapbandtune_struct; +else + p_swapband_struct = rfm7x_init_struct; #endif #ifdef RFM7x_ATOMIC_REG_ACCES - CRITICAL_SECTION +CRITICAL_SECTION #endif - { - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 +{ + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 - for (uint_fast8_t i = 0; i < 4; i++) { + for (uint_fast8_t i = 0; i < 4; i++) { #if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - rfm7x_reg_buff_write_P(i, p_swapband_struct + i * 4, 4); + rfm7x_reg_buff_write_P(i, p_swapband_struct + i * 4, 4); #else - rfm7x_reg_buff_write(i, p_swapband_struct + i * 4, 4); + rfm7x_reg_buff_write(i, p_swapband_struct + i * 4, 4); #endif - } + } - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 - } + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 +} } #endif diff --git a/examples/rfm7xAndBk242xCompatiblity/rfm7x.h b/examples/rfm7xAndBk242xCompatiblity/rfm7x.h index cd321bc27..6474688bd 100644 --- a/examples/rfm7xAndBk242xCompatiblity/rfm7x.h +++ b/examples/rfm7xAndBk242xCompatiblity/rfm7x.h @@ -504,13 +504,13 @@ extern "C" { ////////////////////////////////////////////////////////////////// //?????? /*#if defined(RFM7x_TX_ADDRESS)&&defined(RFM7x_PIPE0_RX_ADDRESS)&&defined(RFM7x_PIPE1_RX_ADDRESS) - #define RFM7x_LONG_ADDR_ENTRIES 3 +#define RFM7x_LONG_ADDR_ENTRIES 3 #elif (defined(RFM7x_TX_ADDRESS)&&defined(RFM7x_PIPE0_RX_ADDRESS))||(defined(RFM7x_PIPE0_RX_ADDRESS)&&defined(RFM7x_PIPE1_RX_ADDRESS))||(defined(RFM7x_TX_ADDRESS)&&defined(RFM7x_PIPE1_RX_ADDRESS)) - #define RFM7x_LONG_ADDR_ENTRIES 2 +#define RFM7x_LONG_ADDR_ENTRIES 2 #elif defined(RFM7x_TX_ADDRESS)||defined(RFM7x_PIPE0_RX_ADDRESS)||defined(RFM7x_PIPE1_RX_ADDRESS) - #define RFM7x_LONG_ADDR_ENTRIES 1 +#define RFM7x_LONG_ADDR_ENTRIES 1 #else - #define RFM7x_LONG_ADDR_ENTRIES 0 +#define RFM7x_LONG_ADDR_ENTRIES 0 #endif*/ ////////////////////////////////////////////////////////////////// diff --git a/examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino b/examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino index 947b6d1d4..9ceedfb1d 100644 --- a/examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino +++ b/examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino @@ -40,70 +40,70 @@ float payload = 0.0; void setup() { - Serial.begin(115200); - while (!Serial) { - // some boards need to wait to ensure access to serial over USB - } + Serial.begin(115200); + while (!Serial) { + // some boards need to wait to ensure access to serial over USB + } - // initialize the transceiver on the SPI bus - if (!radio.begin()) { - Serial.println(F("radio hardware is not responding!!")); - while (1) { } // hold in infinite loop - } + // initialize the transceiver on the SPI bus + if (!radio.begin()) { + Serial.println(F("radio hardware is not responding!!")); + while (1) { } // hold in infinite loop + } - rfm7x_io_init(); - spi_init(); - if (rfm7x_is_present()) { - Serial.println("RFM7X connected, initializing"); - //this code initializes the required registers for the clones. Especially bank1 - rfm7x_init(); - delay(2); - rfm7x_toggle_reg4(); - delay(1); - } + rfm7x_io_init(); + spi_init(); + if (rfm7x_is_present()) { + Serial.println("RFM7X connected, initializing"); + //this code initializes the required registers for the clones. Especially bank1 + rfm7x_init(); + delay(2); + rfm7x_toggle_reg4(); + delay(1); + } - // print example's introductory prompt - Serial.println(F("RF24/examples/rfm7xAndBk242xCompatiblity")); + // print example's introductory prompt + Serial.println(F("RF24/examples/rfm7xAndBk242xCompatiblity")); - // To set the radioNumber via the Serial monitor on startup - Serial.println(F("Which radio is this? Enter '0' or '1'. Defaults to '0'")); - while (!Serial.available()) { - // wait for user input - } - char input = Serial.parseInt(); - radioNumber = input == 1; - Serial.print(F("radioNumber = ")); - Serial.println((int)radioNumber); + // To set the radioNumber via the Serial monitor on startup + Serial.println(F("Which radio is this? Enter '0' or '1'. Defaults to '0'")); + while (!Serial.available()) { + // wait for user input + } + char input = Serial.parseInt(); + radioNumber = input == 1; + Serial.print(F("radioNumber = ")); + Serial.println((int)radioNumber); - // role variable is hardcoded to RX behavior, inform the user of this - Serial.println(F("*** PRESS 'T' to begin transmitting to the other node")); + // role variable is hardcoded to RX behavior, inform the user of this + Serial.println(F("*** PRESS 'T' to begin transmitting to the other node")); - // Set the PA Level low to try preventing power supply related problems - // because these examples are likely run with nodes in close proximity to - // each other. - radio.setPALevel(RF24_PA_LOW); // RF24_PA_MAX is default. + // Set the PA Level low to try preventing power supply related problems + // because these examples are likely run with nodes in close proximity to + // each other. + radio.setPALevel(RF24_PA_LOW); // RF24_PA_MAX is default. - // save on transmission time by setting the radio to only transmit the - // number of bytes we need to transmit a float - radio.setPayloadSize(sizeof(payload)); // float datatype occupies 4 bytes + // save on transmission time by setting the radio to only transmit the + // number of bytes we need to transmit a float + radio.setPayloadSize(sizeof(payload)); // float datatype occupies 4 bytes - // set the TX address of the RX node into the TX pipe - radio.openWritingPipe(address[radioNumber]); // always uses pipe 0 + // set the TX address of the RX node into the TX pipe + radio.openWritingPipe(address[radioNumber]); // always uses pipe 0 - // set the RX address of the TX node into a RX pipe - radio.openReadingPipe(1, address[!radioNumber]); // using pipe 1 + // set the RX address of the TX node into a RX pipe + radio.openReadingPipe(1, address[!radioNumber]); // using pipe 1 - // additional setup specific to the node's role - if (role) { - radio.stopListening(); // put radio in TX mode - } else { - radio.startListening(); // put radio in RX mode - } + // additional setup specific to the node's role + if (role) { + radio.stopListening(); // put radio in TX mode + } else { + radio.startListening(); // put radio in RX mode + } - // For debugging info - // printf_begin(); // needed only once for printing details - // radio.printDetails(); // (smaller) function that prints raw register values - // radio.printPrettyDetails(); // (larger) function that prints human readable data + // For debugging info + // printf_begin(); // needed only once for printing details + // radio.printDetails(); // (smaller) function that prints raw register values + // radio.printPrettyDetails(); // (larger) function that prints human readable data } // setup diff --git a/examples/rfm7xAndBk242xCompatiblity/rfm7x_hardware.cpp b/examples/rfm7xAndBk242xCompatiblity/rfm7x_hardware.cpp index fe884896b..08897f487 100644 --- a/examples/rfm7xAndBk242xCompatiblity/rfm7x_hardware.cpp +++ b/examples/rfm7xAndBk242xCompatiblity/rfm7x_hardware.cpp @@ -11,170 +11,170 @@ void rfm7x_io_init(void) //hardcoded at the moment { - RFM7x_CSN_HI; - RFM7x_CE_LOW; +RFM7x_CSN_HI; +RFM7x_CE_LOW; #if defined(USE_EXAMPLE_SPI_MEGA328) - //set ce to output - //set csn to output +//set ce to output +//set csn to output #elif defined(USE_EXAMPLE_SPI_XMEGA) - //PORTC.DIRSET = PIN4_bm | PIN1_bm; // as output +//PORTC.DIRSET = PIN4_bm | PIN1_bm; // as output #elif defined(USE_EXAMPLE_SPI_STM32F0) - //RCC->AHBENR |= RCC_AHBENR_GPIOAEN; +//RCC->AHBENR |= RCC_AHBENR_GPIOAEN; - //GPIOA->MODER |= (1 << __builtin_ctz(GPIO_MODER_MODER3)) | (1 << __builtin_ctz(GPIO_MODER_MODER4)); // set PA3 and PA4 to output +//GPIOA->MODER |= (1 << __builtin_ctz(GPIO_MODER_MODER3)) | (1 << __builtin_ctz(GPIO_MODER_MODER4)); // set PA3 and PA4 to output #elif defined(USE_EXAMPLE_SPI_ARDUINO) - pinMode(8, OUTPUT); // ce - pinMode(9, OUTPUT); //csn +pinMode(8, OUTPUT); // ce +pinMode(9, OUTPUT); //csn #else // soft \ - //set ce to output \ - //set csn to output +//set ce to output \ +//set csn to output #endif } void spi_init(void) { #if defined(USE_EXAMPLE_SPI_MEGA328) - DDRB |= (1 << PB3) | (1 << PB5); // configure output pins - PORTB |= (1 << PB4); // pullup miso +DDRB |= (1 << PB3) | (1 << PB5); // configure output pins +PORTB |= (1 << PB4); // pullup miso - SPCR |= (1 << SPE) | (1 << MSTR); - SPSR |= (1 << SPI2X); +SPCR |= (1 << SPE) | (1 << MSTR); +SPSR |= (1 << SPI2X); #elif defined(USE_EXAMPLE_SPI_XMEGA) - PORTC.DIRSET = PIN5_bm | PIN7_bm; // sck , mosi - PORTC.PIN6CTRL = PORT_OPC_PULLUP_gc; // pullup miso - SPIC.CTRL = SPI_ENABLE_bm | SPI_MASTER_bm | SPI_MODE_0_gc | SPI_PRESCALER_DIV4_gc; // 32MHz/4 +PORTC.DIRSET = PIN5_bm | PIN7_bm; // sck , mosi +PORTC.PIN6CTRL = PORT_OPC_PULLUP_gc; // pullup miso +SPIC.CTRL = SPI_ENABLE_bm | SPI_MASTER_bm | SPI_MODE_0_gc | SPI_PRESCALER_DIV4_gc; // 32MHz/4 #elif defined(USE_EXAMPLE_SPI_STM32F0) - RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; - GPIOA->MODER |= (2 << __builtin_ctz(GPIO_MODER_MODER5)) | (2 << __builtin_ctz(GPIO_MODER_MODER6)) | (2 << __builtin_ctz(GPIO_MODER_MODER7)); // PA5, PA6, PA7 as alternate - //GPIOA->AFR[0] &= ~((0x0f << __builtin_ctz(GPIO_AFRL_AFR5))|(0x0f << __builtin_ctz(GPIO_AFRL_AFR6))|(0x0f << __builtin_ctz(GPIO_AFRL_AFR7))); - //GPIOA->AFR[0] |= (0 << __builtin_ctz(GPIO_AFRL_AFR5))|(0 << __builtin_ctz(GPIO_AFRL_AFR6))|(0 << __builtin_ctz(GPIO_AFRL_AFR7)); +RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; +GPIOA->MODER |= (2 << __builtin_ctz(GPIO_MODER_MODER5)) | (2 << __builtin_ctz(GPIO_MODER_MODER6)) | (2 << __builtin_ctz(GPIO_MODER_MODER7)); // PA5, PA6, PA7 as alternate +//GPIOA->AFR[0] &= ~((0x0f << __builtin_ctz(GPIO_AFRL_AFR5))|(0x0f << __builtin_ctz(GPIO_AFRL_AFR6))|(0x0f << __builtin_ctz(GPIO_AFRL_AFR7))); +//GPIOA->AFR[0] |= (0 << __builtin_ctz(GPIO_AFRL_AFR5))|(0 << __builtin_ctz(GPIO_AFRL_AFR6))|(0 << __builtin_ctz(GPIO_AFRL_AFR7)); - GPIOA->OSPEEDR |= (3 << __builtin_ctz(GPIO_OSPEEDR_OSPEEDR5)) | (3 << __builtin_ctz(GPIO_OSPEEDR_OSPEEDR7)); // set SCK and MOSI into high speed mode - GPIOA->PUPDR |= (1 << __builtin_ctz(GPIO_PUPDR_PUPDR6)); // pullup miso +GPIOA->OSPEEDR |= (3 << __builtin_ctz(GPIO_OSPEEDR_OSPEEDR5)) | (3 << __builtin_ctz(GPIO_OSPEEDR_OSPEEDR7)); // set SCK and MOSI into high speed mode +GPIOA->PUPDR |= (1 << __builtin_ctz(GPIO_PUPDR_PUPDR6)); // pullup miso - SPI1->CR2 |= SPI_CR2_FRXTH; // RXNE treshold at 1 byte - SPI1->CR1 = SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_SPE | (2 << __builtin_ctz(SPI_CR1_BR)) | SPI_CR1_MSTR; // soft NSS force to master, enable, PCLK/8, master - //SSOE ??? +SPI1->CR2 |= SPI_CR2_FRXTH; // RXNE treshold at 1 byte +SPI1->CR1 = SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_SPE | (2 << __builtin_ctz(SPI_CR1_BR)) | SPI_CR1_MSTR; // soft NSS force to master, enable, PCLK/8, master +//SSOE ??? #elif defined(USE_EXAMPLE_SPI_ARDUINO) - SPI.begin(); +SPI.begin(); - // necessary? - //SPI.setBitOrder(MSBFIRST); - //SPI.setDataMode(SPI_MODE0); - SPI.setClockDivider(SPI_CLOCK_DIV2); +// necessary? +//SPI.setBitOrder(MSBFIRST); +//SPI.setDataMode(SPI_MODE0); +SPI.setClockDivider(SPI_CLOCK_DIV2); #else - // can be optimized into single write if port wiring allows - SOFT_SPI_SCK_DIRSET(); - SOFT_SPI_MOSI_DIRSET(); - SOFT_SPI_MISO_DIRSET(); // always input after POR, can be commented out - SOFT_SPI_MISO_PULLUP_SET(); // ?? +// can be optimized into single write if port wiring allows +SOFT_SPI_SCK_DIRSET(); +SOFT_SPI_MOSI_DIRSET(); +SOFT_SPI_MISO_DIRSET(); // always input after POR, can be commented out +SOFT_SPI_MISO_PULLUP_SET(); // ?? #endif } uint8_t spi_rw(uint8_t data) { #if defined(USE_EXAMPLE_SPI_MEGA328) - SPDR = data; - while (!(SPSR & (1 << SPIF))) - ; +SPDR = data; +while (!(SPSR & (1 << SPIF))) + ; - return SPDR; +return SPDR; #elif defined(USE_EXAMPLE_SPI_XMEGA) - SPIC.DATA = dat; - while (!(SPIC.STATUS & (1 << 7))) - ; // no SPIF defined +SPIC.DATA = dat; +while (!(SPIC.STATUS & (1 << 7))) + ; // no SPIF defined - return SPIC.DATA; +return SPIC.DATA; #elif defined(USE_EXAMPLE_SPI_STM32F0) - while ((SPI1->SR & SPI_SR_BSY)) - ; - *(uint8_t*)&(SPI1->DR) = data; // cast to make 8 bit transfer and thus transmit only 8bit frame - while (!(SPI1->SR & SPI_SR_RXNE)) - ; - data = SPI1->DR; - return data; +while ((SPI1->SR & SPI_SR_BSY)) + ; +*(uint8_t*)&(SPI1->DR) = data; // cast to make 8 bit transfer and thus transmit only 8bit frame +while (!(SPI1->SR & SPI_SR_RXNE)) + ; +data = SPI1->DR; +return data; #elif defined(USE_EXAMPLE_SPI_ARDUINO) - uint8_t tmp = SPI.transfer(data); - return tmp; +uint8_t tmp = SPI.transfer(data); +return tmp; #else - for (uint_fast8_t i = 0; i < 8; i++) { - if (data & 0x80) - SOFT_SPI_MOSI_HI(); - else - SOFT_SPI_MOSI_LO(); - - //_delay_us(0.125); - //_delay_us(1); - delayMicroseconds(1); - SOFT_SPI_SCK_HI(); - delayMicroseconds(1); - // _delay_us(1); - - data <<= 1; - - if (SOFT_SPI_MISO_READ()) - data |= 0x01; // data++ - - // _delay_us(0.125); - delayMicroseconds(1); - SOFT_SPI_SCK_LO(); - // _delay_us(0.125); - delayMicroseconds(1); - } - - return data; +for (uint_fast8_t i = 0; i < 8; i++) { + if (data & 0x80) + SOFT_SPI_MOSI_HI(); + else + SOFT_SPI_MOSI_LO(); + + //_delay_us(0.125); + //_delay_us(1); + delayMicroseconds(1); + SOFT_SPI_SCK_HI(); + delayMicroseconds(1); + // _delay_us(1); + + data <<= 1; + + if (SOFT_SPI_MISO_READ()) + data |= 0x01; // data++ + + // _delay_us(0.125); + delayMicroseconds(1); + SOFT_SPI_SCK_LO(); + // _delay_us(0.125); + delayMicroseconds(1); +} + +return data; #endif } void spi_reg_write(uint8_t reg, uint8_t dat) { - spi_rw(reg); - spi_rw(dat); +spi_rw(reg); +spi_rw(dat); } uint8_t spi_reg_read(uint8_t reg) { - uint8_t tmp; +uint8_t tmp; - spi_rw(reg); - tmp = spi_rw(0); +spi_rw(reg); +tmp = spi_rw(0); - return tmp; // spi_rw(spi_rw(reg)) +return tmp; // spi_rw(spi_rw(reg)) } void spi_reg_buff_write(uint8_t reg, uint8_t* buff, uint8_t len) { - spi_rw(reg); +spi_rw(reg); - for (uint8_t i = 0; i < len; i++) - spi_rw(buff[i]); +for (uint8_t i = 0; i < len; i++) + spi_rw(buff[i]); } void spi_buff_write(uint8_t* buff, uint8_t len) { - for (uint_fast8_t i = 0; i < len; i++) - spi_rw(buff[i]); +for (uint_fast8_t i = 0; i < len; i++) + spi_rw(buff[i]); } void spi_reg_buff_read(uint8_t reg, uint8_t* buff, uint8_t len) { - spi_rw(reg); +spi_rw(reg); - for (uint8_t i = 0; i < len; i++) - buff[i] = spi_rw(0); +for (uint8_t i = 0; i < len; i++) + buff[i] = spi_rw(0); } void spi_buff_read(uint8_t* buff, uint8_t len) { - for (uint_fast8_t i = 0; i < len; i++) - buff[i] = spi_rw(0); +for (uint_fast8_t i = 0; i < len; i++) + buff[i] = spi_rw(0); } From 6b5b8f4e3ebfa27727b51478fd6b240292b54cee Mon Sep 17 00:00:00 2001 From: Tony Date: Fri, 26 Mar 2021 16:22:16 +0100 Subject: [PATCH 4/5] just used arduinoIDE to do formatting --- examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp | 950 +++++++++--------- examples/rfm7xAndBk242xCompatiblity/rfm7x.h | 94 +- .../rfm7xAndBk242xCompatiblity.ino | 2 +- .../rfm7x_hardware.cpp | 188 ++-- 4 files changed, 635 insertions(+), 599 deletions(-) diff --git a/examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp b/examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp index 7c59f7b7b..f2982f904 100644 --- a/examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp +++ b/examples/rfm7xAndBk242xCompatiblity/rfm7x.cpp @@ -19,20 +19,20 @@ // workaround for ATOMIC_BLOCK __attribute__((always_inline)) inline int __int_disable_irq(void) { -int primask; -asm volatile("mrs %0, PRIMASK\n" - : "=r"(primask)); -asm volatile("cpsid i\n"); -return primask & 1; + int primask; + asm volatile("mrs %0, PRIMASK\n" + : "=r"(primask)); + asm volatile("cpsid i\n"); + return primask & 1; } __attribute__((always_inline)) inline void __int_restore_irq(int* primask) { -if (!(*primask)) { - asm volatile("" :: - : "memory"); - asm volatile("cpsie i\n"); -} + if (!(*primask)) { + asm volatile("" :: + : "memory"); + asm volatile("cpsie i\n"); + } } #define CRITICAL_SECTION for (int primask_save __attribute__((__cleanup__(__int_restore_irq))) = __int_disable_irq(), __ToDo = 1; __ToDo; __ToDo = 0) @@ -49,77 +49,77 @@ const __flash uint8_t rfm7x_init_struct[] = const uint8_t rfm7x_init_struct[] = // generic for all architectures // table will be placed in SRAM if your mcu doesn't have unified memory space (flash + ram) #endif { -////////////////////////////////////////// bank 1 initialization registers ////////////////////////////////////////// - -RFM7x_BANK1_REG0, -RFM7x_BANK1_REG1, -RFM7x_BANK1_REG2, -RFM7x_BANK1_REG3, -RFM7x_BANK1_REG4, -RFM7x_BANK1_REG5, -RFM7x_BANK1_REG6, -RFM7x_BANK1_REG7, -RFM7x_BANK1_REG8, -RFM7x_BANK1_REG9, -RFM7x_BANK1_REGA, -RFM7x_BANK1_REGB, -RFM7x_BANK1_REGC, -RFM7x_BANK1_REGD, -RFM7x_BANK1_RAMP_CURVE, - -////////////////////////////////////////// bank 0 initialization registers ////////////////////////////////////////// + ////////////////////////////////////////// bank 1 initialization registers ////////////////////////////////////////// + + RFM7x_BANK1_REG0, + RFM7x_BANK1_REG1, + RFM7x_BANK1_REG2, + RFM7x_BANK1_REG3, + RFM7x_BANK1_REG4, + RFM7x_BANK1_REG5, + RFM7x_BANK1_REG6, + RFM7x_BANK1_REG7, + RFM7x_BANK1_REG8, + RFM7x_BANK1_REG9, + RFM7x_BANK1_REGA, + RFM7x_BANK1_REGB, + RFM7x_BANK1_REGC, + RFM7x_BANK1_REGD, + RFM7x_BANK1_RAMP_CURVE, + + ////////////////////////////////////////// bank 0 initialization registers ////////////////////////////////////////// #ifndef RFM7x_DO_NOT_INITIALIZE_BANK0 -RFM7x_BANK0_REG_CONFIG, // PTX/PRX mode - doesn't care, it will be set later with rest commands -RFM7x_BANK0_REG_EN_AA, -RFM7x_BANK0_REG_EN_RXADDR, -RFM7x_BANK0_REG_SETUP_AW, -RFM7x_BANK0_REG_SETUP_RETR, -RFM7x_BANK0_REG_RF_CH, -RFM7x_BANK0_REG_RF_SETUP, - -RFM7x_BANK0_REG_STATUS, // status register that have to be initialized - not documented -RFM7x_BANK0_REG_OBSERVE_TX, // status register that have to be initialized - not documented -RFM7x_BANK0_REG_CD, // status register that have to be initialized - not documented + RFM7x_BANK0_REG_CONFIG, // PTX/PRX mode - doesn't care, it will be set later with rest commands + RFM7x_BANK0_REG_EN_AA, + RFM7x_BANK0_REG_EN_RXADDR, + RFM7x_BANK0_REG_SETUP_AW, + RFM7x_BANK0_REG_SETUP_RETR, + RFM7x_BANK0_REG_RF_CH, + RFM7x_BANK0_REG_RF_SETUP, + + RFM7x_BANK0_REG_STATUS, // status register that have to be initialized - not documented + RFM7x_BANK0_REG_OBSERVE_TX, // status register that have to be initialized - not documented + RFM7x_BANK0_REG_CD, // status register that have to be initialized - not documented #ifndef RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS -0xE7, // pipe0 default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined -0xC2, // pipe1 default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined + 0xE7, // pipe0 default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined + 0xC2, // pipe1 default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined -RFM7x_PIPE2_RX_ADDRESS, // pipe 2 address // LSB only -RFM7x_PIPE3_RX_ADDRESS, // pipe 3 address // LSB only -RFM7x_PIPE4_RX_ADDRESS, // pipe 4 address // LSB only -RFM7x_PIPE5_RX_ADDRESS, // pipe 5 address // LSB only + RFM7x_PIPE2_RX_ADDRESS, // pipe 2 address // LSB only + RFM7x_PIPE3_RX_ADDRESS, // pipe 3 address // LSB only + RFM7x_PIPE4_RX_ADDRESS, // pipe 4 address // LSB only + RFM7x_PIPE5_RX_ADDRESS, // pipe 5 address // LSB only #endif #if !defined(RFM7x_DO_NOT_INITIALIZE_RX_PAYLOAD_LEN_REGS) && !defined(RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS) -0xE7, // TX default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined + 0xE7, // TX default address // just dummy byte to fill space for loading whole bank0 in one-run // single byte write might be undefined -RFM7x_PIPE0_RX_PAYLOAD_LEN, // pipe 0 - payload length // 0 equals to dynamic payload ?? -RFM7x_PIPE1_RX_PAYLOAD_LEN, // pipe 1 - payload length // 0 equals to dynamic payload ?? -RFM7x_PIPE2_RX_PAYLOAD_LEN, // pipe 2 - payload length // 0 equals to dynamic payload ?? -RFM7x_PIPE3_RX_PAYLOAD_LEN, // pipe 3 - payload length // 0 equals to dynamic payload ?? -RFM7x_PIPE4_RX_PAYLOAD_LEN, // pipe 4 - payload length // 0 equals to dynamic payload ?? -RFM7x_PIPE5_RX_PAYLOAD_LEN, // pipe 5 - payload length // 0 equals to dynamic payload ?? + RFM7x_PIPE0_RX_PAYLOAD_LEN, // pipe 0 - payload length // 0 equals to dynamic payload ?? + RFM7x_PIPE1_RX_PAYLOAD_LEN, // pipe 1 - payload length // 0 equals to dynamic payload ?? + RFM7x_PIPE2_RX_PAYLOAD_LEN, // pipe 2 - payload length // 0 equals to dynamic payload ?? + RFM7x_PIPE3_RX_PAYLOAD_LEN, // pipe 3 - payload length // 0 equals to dynamic payload ?? + RFM7x_PIPE4_RX_PAYLOAD_LEN, // pipe 4 - payload length // 0 equals to dynamic payload ?? + RFM7x_PIPE5_RX_PAYLOAD_LEN, // pipe 5 - payload length // 0 equals to dynamic payload ?? -RFM7x_BANK0_REG_FIFO_STATUS, // status register that have to be initialized - not documented + RFM7x_BANK0_REG_FIFO_STATUS, // status register that have to be initialized - not documented #endif -//0x00, // dummy -//0x00, // dummy -//0x00, // dummy -//0x00, // dummy + //0x00, // dummy + //0x00, // dummy + //0x00, // dummy + //0x00, // dummy -//RFM7x_BANK0_REG_DYNPD, -//RFM7x_BANK0_REG_FEATURE, + //RFM7x_BANK0_REG_DYNPD, + //RFM7x_BANK0_REG_FEATURE, #if defined(RFM7x_TX_ADDRESS) && !defined(RFM7x_USE_PIPE0_ADDRESS_FOR_TX_ADDRESS) -RFM7x_TX_ADDRESS, + RFM7x_TX_ADDRESS, #endif #ifdef RFM7x_PIPE0_RX_ADDRESS -RFM7x_PIPE0_RX_ADDRESS, + RFM7x_PIPE0_RX_ADDRESS, #endif #ifdef RFM7x_PIPE1_RX_ADDRESS -RFM7x_PIPE1_RX_ADDRESS, + RFM7x_PIPE1_RX_ADDRESS, #endif #endif //RFM7x_DO_NOT_INITIALIZE_BANK0 @@ -128,92 +128,92 @@ RFM7x_PIPE1_RX_ADDRESS, void rfm7x_init(void) { #ifdef RFM7x_ATOMIC_REG_ACCES -CRITICAL_SECTION + CRITICAL_SECTION #endif -{ + { #if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - const __flash uint8_t* p_init_struct = rfm7x_init_struct; + const __flash uint8_t* p_init_struct = rfm7x_init_struct; #else - const uint8_t* p_init_struct = rfm7x_init_struct; + const uint8_t* p_init_struct = rfm7x_init_struct; #endif - if ((0x80 & rfm7x_reg_read(RFM7x_REG_STATUS)) == 0) - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // select bank 1 + if ((0x80 & rfm7x_reg_read(RFM7x_REG_STATUS)) == 0) + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // select bank 1 - for (uint_fast8_t i = 0; i < RFM7x_BANK1_ENTRIES; i++) { + for (uint_fast8_t i = 0; i < RFM7x_BANK1_ENTRIES; i++) { #if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - if (i != RFM7x_BANK1_ENTRIES - 1) { - rfm7x_reg_buff_write_P(i, p_init_struct, 4); - p_init_struct += 4; - } else { - rfm7x_reg_buff_write_P(i, p_init_struct, 11); - p_init_struct += 11; - } + if (i != RFM7x_BANK1_ENTRIES - 1) { + rfm7x_reg_buff_write_P(i, p_init_struct, 4); + p_init_struct += 4; + } else { + rfm7x_reg_buff_write_P(i, p_init_struct, 11); + p_init_struct += 11; + } #else - if (i != RFM7x_BANK1_ENTRIES - 1) { - rfm7x_reg_buff_write(i, (uint8_t*)p_init_struct, 4); - p_init_struct += 4; - } else { - rfm7x_reg_buff_write(i, (uint8_t*)p_init_struct, 11); - p_init_struct += 11; - } + if (i != RFM7x_BANK1_ENTRIES - 1) { + rfm7x_reg_buff_write(i, (uint8_t*)p_init_struct, 4); + p_init_struct += 4; + } else { + rfm7x_reg_buff_write(i, (uint8_t*)p_init_struct, 11); + p_init_struct += 11; + } #endif - } + } - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 - rfm7x_reg_write(RFM7x_REG_FEATURE, 0x01); // check if "feature register" is writable before (de)activating it + rfm7x_reg_write(RFM7x_REG_FEATURE, 0x01); // check if "feature register" is writable before (de)activating it - if (!rfm7x_reg_read(RFM7x_REG_FEATURE)) - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x73); // activate feature register if not activated + if (!rfm7x_reg_read(RFM7x_REG_FEATURE)) + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x73); // activate feature register if not activated - for (uint_fast8_t i = 0; i < RFM7x_BANK0_ENTRIES; i++) { - rfm7x_reg_write(i, *p_init_struct++); - } + for (uint_fast8_t i = 0; i < RFM7x_BANK0_ENTRIES; i++) { + rfm7x_reg_write(i, *p_init_struct++); + } #if defined(RFM7x_TX_ADDRESS) || defined(RFM7x_USE_PIPE0_ADDRESS_FOR_TX_ADDRESS) #if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - rfm7x_reg_buff_write_P(RFM7x_REG_TX_ADDR, p_init_struct, RFM7x_TX_ADDRESS_SIZE); + rfm7x_reg_buff_write_P(RFM7x_REG_TX_ADDR, p_init_struct, RFM7x_TX_ADDRESS_SIZE); #else - rfm7x_reg_buff_write(RFM7x_REG_TX_ADDR, (uint8_t*)p_init_struct, RFM7x_TX_ADDRESS_SIZE); + rfm7x_reg_buff_write(RFM7x_REG_TX_ADDR, (uint8_t*)p_init_struct, RFM7x_TX_ADDRESS_SIZE); #endif #ifndef RFM7x_USE_PIPE0_ADDRESS_FOR_TX_ADDRESS - p_init_struct += RFM7x_TX_ADDRESS_SIZE; + p_init_struct += RFM7x_TX_ADDRESS_SIZE; #endif #endif #ifdef RFM7x_PIPE0_RX_ADDRESS #if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - rfm7x_reg_buff_write_P(RFM7x_REG_RX_ADDR_P0, p_init_struct, RFM7x_PIPE0_RX_ADDRESS_SIZE); + rfm7x_reg_buff_write_P(RFM7x_REG_RX_ADDR_P0, p_init_struct, RFM7x_PIPE0_RX_ADDRESS_SIZE); #else - rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P0, (uint8_t*)p_init_struct, RFM7x_PIPE0_RX_ADDRESS_SIZE); + rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P0, (uint8_t*)p_init_struct, RFM7x_PIPE0_RX_ADDRESS_SIZE); #endif - p_init_struct += RFM7x_PIPE0_RX_ADDRESS_SIZE; + p_init_struct += RFM7x_PIPE0_RX_ADDRESS_SIZE; #endif #ifdef RFM7x_PIPE1_RX_ADDRESS #if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - rfm7x_reg_buff_write_P(RFM7x_REG_RX_ADDR_P1, p_init_struct, RFM7x_PIPE1_RX_ADDRESS_SIZE); + rfm7x_reg_buff_write_P(RFM7x_REG_RX_ADDR_P1, p_init_struct, RFM7x_PIPE1_RX_ADDRESS_SIZE); #else - rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P1, (uint8_t*)p_init_struct, RFM7x_PIPE1_RX_ADDRESS_SIZE); + rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P1, (uint8_t*)p_init_struct, RFM7x_PIPE1_RX_ADDRESS_SIZE); #endif #endif #ifdef RFM7x_DO_NOT_INITIALIZE_BANK0 - rfm7x_reg_write(RFM7x_REG_STATUS, RFM7x_BANK0_REG_STATUS); - rfm7x_reg_write(RFM7x_REG_OBSERVE_TX, RFM7x_BANK0_REG_OBSERVE_TX); - rfm7x_reg_write(RFM7x_REG_CD, RFM7x_BANK0_REG_CD); - rfm7x_reg_write(RFM7x_REG_FIFO_STATUS, RFM7x_BANK0_REG_FIFO_STATUS); + rfm7x_reg_write(RFM7x_REG_STATUS, RFM7x_BANK0_REG_STATUS); + rfm7x_reg_write(RFM7x_REG_OBSERVE_TX, RFM7x_BANK0_REG_OBSERVE_TX); + rfm7x_reg_write(RFM7x_REG_CD, RFM7x_BANK0_REG_CD); + rfm7x_reg_write(RFM7x_REG_FIFO_STATUS, RFM7x_BANK0_REG_FIFO_STATUS); #elif defined(RFM7x_DO_NOT_INITIALIZE_RX_PAYLOAD_LEN_REGS) || defined(RFM7x_DO_NOT_INITIALIZE_P2_RX_ADDRESS_AND_PAYLOAD_LEN_REGS) - rfm7x_reg_write(RFM7x_REG_FIFO_STATUS, RFM7x_BANK0_REG_FIFO_STATUS); + rfm7x_reg_write(RFM7x_REG_FIFO_STATUS, RFM7x_BANK0_REG_FIFO_STATUS); #endif - rfm7x_reg_write(RFM7x_REG_DYNPD, RFM7x_BANK0_REG_DYNPD); - rfm7x_reg_write(RFM7x_REG_FEATURE, RFM7x_BANK0_REG_FEATURE); -} + rfm7x_reg_write(RFM7x_REG_DYNPD, RFM7x_BANK0_REG_DYNPD); + rfm7x_reg_write(RFM7x_REG_FEATURE, RFM7x_BANK0_REG_FEATURE); + } } #if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) @@ -222,137 +222,137 @@ const __flash uint8_t rfm7x_REG4_toggle_struct[] = const uint8_t rfm7x_REG4_toggle_struct[] = #endif { - 0x06 | RFM7x_BANK1_REG4 // 0x06 will be or'ed with first element (bits 25,26 set) + 0x06 | RFM7x_BANK1_REG4 // 0x06 will be or'ed with first element (bits 25,26 set) }; void rfm7x_toggle_reg4(void) // MIGHT NOT BE THE CASE FOR BK2411/BK2412/BK5811 { -// one of the chinese documents (rfm73 -> rfm75 migration) says that it should be executed after every PWR_UP, not only during initialization + // one of the chinese documents (rfm73 -> rfm75 migration) says that it should be executed after every PWR_UP, not only during initialization -// 4. RFM75 PowerUP after the first packet of data sent unsuccessful solution -// RFM75 from the POWER DOWN state to switch to POWER UP state, send the first packet is not successful, the reason -// Is the PLL is not locked, the solution is as follows: -// Before transmitting data normally, please follow the following procedure: -// Power up = 1 -// Wait for 2ms -// Operate the bank1 register, writing a 1 to bit 25 of register 04 -// Wait 20us -// Operate the bank1 register, writing a 0 to bit 25 of register 04 -// Wait for 0.5ms. -// Then normal launch. + // 4. RFM75 PowerUP after the first packet of data sent unsuccessful solution + // RFM75 from the POWER DOWN state to switch to POWER UP state, send the first packet is not successful, the reason + // Is the PLL is not locked, the solution is as follows: + // Before transmitting data normally, please follow the following procedure: + // Power up = 1 + // Wait for 2ms + // Operate the bank1 register, writing a 1 to bit 25 of register 04 + // Wait 20us + // Operate the bank1 register, writing a 0 to bit 25 of register 04 + // Wait for 0.5ms. + // Then normal launch. -// AN0008 -// 9. Toggle REG4<25?26>, write 1 to bit25, bit 26, then write 0 to them. + // AN0008 + // 9. Toggle REG4<25?26>, write 1 to bit25, bit 26, then write 0 to them. #ifdef RFM7x_ATOMIC_REG_ACCES -CRITICAL_SECTION + CRITICAL_SECTION #endif -{ - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 + { + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 #if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - rfm7x_reg_buff_write_P(0x04, rfm7x_REG4_toggle_struct, 4); - _delay_us(20); // if not required then this function may not be required, so better to leave it here - rfm7x_reg_buff_write_P(0x04, &rfm7x_init_struct[16], 4); + rfm7x_reg_buff_write_P(0x04, rfm7x_REG4_toggle_struct, 4); + _delay_us(20); // if not required then this function may not be required, so better to leave it here + rfm7x_reg_buff_write_P(0x04, &rfm7x_init_struct[16], 4); #else - rfm7x_reg_buff_write(0x04, (uint8_t*)rfm7x_REG4_toggle_struct, 4); - //_delay_us(20); // if not required then this function may not be required, so better to leave it here - rfm7x_reg_buff_write(0x04, (uint8_t*)&rfm7x_init_struct[16], 4); + rfm7x_reg_buff_write(0x04, (uint8_t*)rfm7x_REG4_toggle_struct, 4); + //_delay_us(20); // if not required then this function may not be required, so better to leave it here + rfm7x_reg_buff_write(0x04, (uint8_t*)&rfm7x_init_struct[16], 4); #endif - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 -} + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 + } } void rfm7x_cmd_write(uint8_t reg, uint8_t dat) { #ifdef RFM7x_ATOMIC_REG_ACCES -CRITICAL_SECTION + CRITICAL_SECTION #endif -{ - RFM7x_CSN_LOW; - rfm7x_spi_rw(reg); - rfm7x_spi_rw(dat); - RFM7x_CSN_HI; -} + { + RFM7x_CSN_LOW; + rfm7x_spi_rw(reg); + rfm7x_spi_rw(dat); + RFM7x_CSN_HI; + } } uint8_t rfm7x_cmd_read(uint8_t reg) { -uint8_t tmp; + uint8_t tmp; #ifdef RFM7x_ATOMIC_REG_ACCES -CRITICAL_SECTION + CRITICAL_SECTION #endif -{ - RFM7x_CSN_LOW; - rfm7x_spi_rw(reg); - tmp = rfm7x_spi_rw(0); // rfm7x_spi_rw(rfm7x_spi_rw()) - RFM7x_CSN_HI; -} + { + RFM7x_CSN_LOW; + rfm7x_spi_rw(reg); + tmp = rfm7x_spi_rw(0); // rfm7x_spi_rw(rfm7x_spi_rw()) + RFM7x_CSN_HI; + } -return tmp; + return tmp; } #ifdef RFM7x_USE_UNIVERSAL_SPI_BUFF_RW_FUNCTIONS void rfm7x_cmd_buff_write(uint8_t reg, uint8_t* buff, uint8_t len) { #ifdef RFM7x_ATOMIC_REG_ACCES -CRITICAL_SECTION + CRITICAL_SECTION #endif -{ - RFM7x_CSN_LOW; - rfm7x_spi_rw(reg); - rfm7x_buff_write(buff, len); - RFM7x_CSN_HI; -} + { + RFM7x_CSN_LOW; + rfm7x_spi_rw(reg); + rfm7x_buff_write(buff, len); + RFM7x_CSN_HI; + } } void rfm7x_cmd_buff_read(uint8_t reg, uint8_t* buff, uint8_t len) { #ifdef RFM7x_ATOMIC_REG_ACCES -CRITICAL_SECTION + CRITICAL_SECTION #endif -{ - RFM7x_CSN_LOW; - rfm7x_spi_rw(reg); - rfm7x_buff_read(buff, len); - RFM7x_CSN_HI; -} + { + RFM7x_CSN_LOW; + rfm7x_spi_rw(reg); + rfm7x_buff_read(buff, len); + RFM7x_CSN_HI; + } } #else void rfm7x_cmd_buff_write(uint8_t reg, uint8_t* buff, uint8_t len) { #ifdef RFM7x_ATOMIC_REG_ACCES -CRITICAL_SECTION + CRITICAL_SECTION #endif -{ - RFM7x_CSN_LOW; + { + RFM7x_CSN_LOW; - rfm7x_spi_rw(reg); + rfm7x_spi_rw(reg); - for (uint_fast8_t i = 0; i < len; i++) - rfm7x_spi_rw(buff[i]); + for (uint_fast8_t i = 0; i < len; i++) + rfm7x_spi_rw(buff[i]); - RFM7x_CSN_HI; -} + RFM7x_CSN_HI; + } } void rfm7x_cmd_buff_read(uint8_t reg, uint8_t* buff, uint8_t len) { #ifdef RFM7x_ATOMIC_REG_ACCES -CRITICAL_SECTION + CRITICAL_SECTION #endif -{ - RFM7x_CSN_LOW; + { + RFM7x_CSN_LOW; - rfm7x_spi_rw(reg); + rfm7x_spi_rw(reg); - for (uint_fast8_t i = 0; i < len; i++) - buff[i] = rfm7x_spi_rw(0); + for (uint_fast8_t i = 0; i < len; i++) + buff[i] = rfm7x_spi_rw(0); - RFM7x_CSN_HI; -} + RFM7x_CSN_HI; + } } #endif @@ -360,486 +360,486 @@ CRITICAL_SECTION void rfm7x_cmd_buff_write_P(uint8_t reg, const __flash uint8_t* buff, uint8_t len) // __memx ???? { #ifdef RFM7x_ATOMIC_REG_ACCES -CRITICAL_SECTION + CRITICAL_SECTION #endif -{ - RFM7x_CSN_LOW; + { + RFM7x_CSN_LOW; - rfm7x_spi_rw(reg); + rfm7x_spi_rw(reg); - for (uint_fast8_t i = 0; i < len; i++) - rfm7x_spi_rw(buff[i]); + for (uint_fast8_t i = 0; i < len; i++) + rfm7x_spi_rw(buff[i]); - RFM7x_CSN_HI; -} + RFM7x_CSN_HI; + } } #endif uint8_t rfm7x_is_present(void) { -uint8_t tmp1, tmp2; -tmp1 = rfm7x_reg_read(RFM7x_REG_STATUS); -rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); -tmp2 = rfm7x_reg_read(RFM7x_REG_STATUS); -rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); -return (tmp1 ^ tmp2) == 0x80; + uint8_t tmp1, tmp2; + tmp1 = rfm7x_reg_read(RFM7x_REG_STATUS); + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); + tmp2 = rfm7x_reg_read(RFM7x_REG_STATUS); + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); + return (tmp1 ^ tmp2) == 0x80; } void rfm7x_power_up(void) { -uint8_t tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); -tmp |= 0x02; // set PWR_UP bit -rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); + tmp |= 0x02; // set PWR_UP bit + rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); } void rfm7x_power_down(void) { -RFM7x_CE_LOW; + RFM7x_CE_LOW; -uint8_t tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); -tmp &= 0xFD; // clear PWR_UP bit -rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); + tmp &= 0xFD; // clear PWR_UP bit + rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); } void rfm7x_mode_receive(void) { -RFM7x_CE_LOW; -uint8_t tmp; + RFM7x_CE_LOW; + uint8_t tmp; -//tmp = rfm7x_reg_read(RFM7x_REG_STATUS); -// handle requests here ?? -//rfm7x_reg_write(RFM7x_REG_STATUS, tmp); // clear interrupt requests + //tmp = rfm7x_reg_read(RFM7x_REG_STATUS); + // handle requests here ?? + //rfm7x_reg_write(RFM7x_REG_STATUS, tmp); // clear interrupt requests -rfm7x_reg_write(RFM7x_REG_STATUS, 0x70); // clear interrupt requests + rfm7x_reg_write(RFM7x_REG_STATUS, 0x70); // clear interrupt requests -tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); -tmp |= 0x01; // set RX bit -rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); + tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); + tmp |= 0x01; // set RX bit + rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); #ifdef RFM7x_FLUSH_TX_AND_RX_WHILE_SWITCHING_MODES -rfm7x_cmd_write(RFM7x_CMD_FLUSH_TX, 0); + rfm7x_cmd_write(RFM7x_CMD_FLUSH_TX, 0); #endif -rfm7x_cmd_write(RFM7x_CMD_FLUSH_RX, 0); // it have to be flushed, otherwise doesn't work + rfm7x_cmd_write(RFM7x_CMD_FLUSH_RX, 0); // it have to be flushed, otherwise doesn't work -RFM7x_CE_HI; + RFM7x_CE_HI; } void rfm7x_mode_transmit(void) { -RFM7x_CE_LOW; -uint8_t tmp; + RFM7x_CE_LOW; + uint8_t tmp; -//tmp = rfm7x_reg_read(RFM7x_REG_STATUS); -// handle requests here ?? -//rfm7x_reg_write(RFM7x_REG_STATUS, tmp); // clear interrupt requests + //tmp = rfm7x_reg_read(RFM7x_REG_STATUS); + // handle requests here ?? + //rfm7x_reg_write(RFM7x_REG_STATUS, tmp); // clear interrupt requests -rfm7x_reg_write(RFM7x_REG_STATUS, 0x70); // clear interrupt requests, otherwise further communication is not possible if MAX_RT is asserted + rfm7x_reg_write(RFM7x_REG_STATUS, 0x70); // clear interrupt requests, otherwise further communication is not possible if MAX_RT is asserted -tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); -tmp &= 0xFE; // clear RX bit -rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); + tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); + tmp &= 0xFE; // clear RX bit + rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); #ifdef RFM7x_FLUSH_TX_AND_RX_WHILE_SWITCHING_MODES -rfm7x_cmd_write(RFM7x_CMD_FLUSH_RX, 0); + rfm7x_cmd_write(RFM7x_CMD_FLUSH_RX, 0); #endif -rfm7x_cmd_write(RFM7x_CMD_FLUSH_TX, 0); // it have to be flushed, otherwise chip doesn't work + rfm7x_cmd_write(RFM7x_CMD_FLUSH_TX, 0); // it have to be flushed, otherwise chip doesn't work -RFM7x_CE_HI; + RFM7x_CE_HI; } uint8_t rfm7x_receive(uint8_t* buff) { -uint8_t p = rfm7x_receive_next_pipe(); + uint8_t p = rfm7x_receive_next_pipe(); -if (p == 0x07) - return 0; + if (p == 0x07) + return 0; -uint8_t len = rfm7x_receive_next_length(); + uint8_t len = rfm7x_receive_next_length(); -rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); + rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); -return len; + return len; } void rfm7x_receive_nocheck(uint8_t* buff) { -uint8_t len = rfm7x_receive_next_length(); -rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); + uint8_t len = rfm7x_receive_next_length(); + rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); } uint8_t rfm7x_receive_p_(uint8_t* pipe, uint8_t* buff) { -uint8_t p = rfm7x_receive_next_pipe(); + uint8_t p = rfm7x_receive_next_pipe(); -if (p == 0x07) - return 0; + if (p == 0x07) + return 0; -*pipe = p; -uint8_t len = rfm7x_receive_next_length(); + *pipe = p; + uint8_t len = rfm7x_receive_next_length(); -rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); + rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); -return len; + return len; } uint8_t rfm7x_receive_s(uint8_t* buff, uint8_t length) { -uint8_t p = rfm7x_receive_next_pipe(); + uint8_t p = rfm7x_receive_next_pipe(); -if (p == 0x07) - return p; + if (p == 0x07) + return p; -rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, length); + rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, length); -return p; + return p; } uint8_t rfm7x_receive_f(uint8_t* buff, uint8_t* pipe, uint8_t* length) { -uint8_t p = rfm7x_receive_next_pipe(); + uint8_t p = rfm7x_receive_next_pipe(); -if (p == 0x07) - return 0; + if (p == 0x07) + return 0; -uint8_t len = rfm7x_receive_next_length(); + uint8_t len = rfm7x_receive_next_length(); -*pipe = p; -*length = len; + *pipe = p; + *length = len; -rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); + rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, len); -return 1; + return 1; } void rfm7x_set_rssi_threshold_step(uint8_t level) { #ifdef RFM7x_ATOMIC_REG_ACCES -CRITICAL_SECTION + CRITICAL_SECTION #endif -{ - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 + { + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 - RFM7x_CSN_LOW; - rfm7x_spi_rw(0x05 | 0x20); + RFM7x_CSN_LOW; + rfm7x_spi_rw(0x05 | 0x20); #if (RFM7x_MODULECHIP_USED == 2) - uint8_t tmp; - - switch (level) { - case 0: - tmp = 0x00; - break; - case 1: - tmp = 0x02; - break; - case 2: - tmp = 0x01; - break; - case 3: - tmp = 0x03; - break; - case 4: - tmp = 0x08; - break; - case 5: - tmp = 0x0A; - break; - case 6: - tmp = 0x09; - break; - case 7: - tmp = 0x0B; - break; - case 8: - tmp = 0x04; - break; - case 9: - tmp = 0x06; - break; - case 10: - tmp = 0x05; - break; - case 11: - tmp = 0x07; - break; - case 12: - tmp = 0x0C; - break; - case 13: - tmp = 0x0E; - break; - case 14: - tmp = 0x0D; - break; - case 15: - tmp = 0x0F; - break; - default: - tmp = level; - break; - } - - rfm7x_spi_rw(tmp << 2); + uint8_t tmp; + + switch (level) { + case 0: + tmp = 0x00; + break; + case 1: + tmp = 0x02; + break; + case 2: + tmp = 0x01; + break; + case 3: + tmp = 0x03; + break; + case 4: + tmp = 0x08; + break; + case 5: + tmp = 0x0A; + break; + case 6: + tmp = 0x09; + break; + case 7: + tmp = 0x0B; + break; + case 8: + tmp = 0x04; + break; + case 9: + tmp = 0x06; + break; + case 10: + tmp = 0x05; + break; + case 11: + tmp = 0x07; + break; + case 12: + tmp = 0x0C; + break; + case 13: + tmp = 0x0E; + break; + case 14: + tmp = 0x0D; + break; + case 15: + tmp = 0x0F; + break; + default: + tmp = level; + break; + } + + rfm7x_spi_rw(tmp << 2); #else - rfm7x_spi_rw(level << 2); + rfm7x_spi_rw(level << 2); #endif - rfm7x_spi_rw(rfm7x_init_struct[21]); - rfm7x_spi_rw(rfm7x_init_struct[22]); - rfm7x_spi_rw(rfm7x_init_struct[23]); - RFM7x_CSN_HI; + rfm7x_spi_rw(rfm7x_init_struct[21]); + rfm7x_spi_rw(rfm7x_init_struct[22]); + rfm7x_spi_rw(rfm7x_init_struct[23]); + RFM7x_CSN_HI; - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 -} + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 + } } void rfm7x_set_crc_length(uint8_t len) { -uint8_t tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_CONFIG); -tmp &= ~(RFM7x_CONFIG_EN_CRC | RFM7x_CONFIG_CRCO); // clear EN_CRC and CRCO + tmp &= ~(RFM7x_CONFIG_EN_CRC | RFM7x_CONFIG_CRCO); // clear EN_CRC and CRCO -if (len == 0) { - rfm7x_reg_write(RFM7x_REG_EN_AA, 0); // Auto ACK have to be disabled before disabling CRC - rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); -} else { - tmp |= (RFM7x_CONFIG_EN_CRC); // set EN_CRC + if (len == 0) { + rfm7x_reg_write(RFM7x_REG_EN_AA, 0); // Auto ACK have to be disabled before disabling CRC + rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); + } else { + tmp |= (RFM7x_CONFIG_EN_CRC); // set EN_CRC - if (len & 0x02) // if 2 byte encoding scheme is selected, set CRCO - tmp |= (RFM7x_CONFIG_CRCO); + if (len & 0x02) // if 2 byte encoding scheme is selected, set CRCO + tmp |= (RFM7x_CONFIG_CRCO); - //rfm7x_reg_write(RFM7x_REG_EN_AA, 0x3f); //???? - rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); -} + //rfm7x_reg_write(RFM7x_REG_EN_AA, 0x3f); //???? + rfm7x_reg_write(RFM7x_REG_CONFIG, tmp); + } } void rfm7x_set_tx_pwr(uint8_t level) { -uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); #if (RFM7x_MODULECHIP_USED == 0) | (RFM7x_MODULECHIP_USED == 1) | (RFM7x_MODULECHIP_USED == 2) // bk2401//bk2421/bk2423 -tmp |= (level << 1); -rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); + tmp |= (level << 1); + rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); #elif (RFM7x_MODULECHIP_USED == 3) // bk2425 -uint8_t txictrl_tmp = 0; + uint8_t txictrl_tmp = 0; -switch (level) { -default: -case 0: // -25 dBm -case 1: // -18 dBm - break; -case 2: // -12 dBm - level -= 1; - txictrl_tmp = 1; - break; + switch (level) { + default: + case 0: // -25 dBm + case 1: // -18 dBm + break; + case 2: // -12 dBm + level -= 1; + txictrl_tmp = 1; + break; -case 3: // -7 dBm - level -= 1; - txictrl_tmp = 2; - break; + case 3: // -7 dBm + level -= 1; + txictrl_tmp = 2; + break; -case 4: // -1 dBm - level -= 1; - break; + case 4: // -1 dBm + level -= 1; + break; -case 5: // 4 dBm - level -= 2; - txictrl_tmp = 7; - break; -} + case 5: // 4 dBm + level -= 2; + txictrl_tmp = 7; + break; + } -tmp |= (level << 1); -rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); + tmp |= (level << 1); + rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); #ifdef RFM7x_ATOMIC_REG_ACCES -CRITICAL_SECTION + CRITICAL_SECTION #endif -{ - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 + { + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 - RFM7x_CSN_LOW; - rfm7x_spi_rw(0x04 | 0x20); - rfm7x_spi_rw((rfm7x_init_struct[16] & 0x38) | txictrl_tmp); - rfm7x_spi_rw(rfm7x_init_struct[17]); - rfm7x_spi_rw(rfm7x_init_struct[18]); - rfm7x_spi_rw(rfm7x_init_struct[19]); - RFM7x_CSN_HI; + RFM7x_CSN_LOW; + rfm7x_spi_rw(0x04 | 0x20); + rfm7x_spi_rw((rfm7x_init_struct[16] & 0x38) | txictrl_tmp); + rfm7x_spi_rw(rfm7x_init_struct[17]); + rfm7x_spi_rw(rfm7x_init_struct[18]); + rfm7x_spi_rw(rfm7x_init_struct[19]); + RFM7x_CSN_HI; - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 -} + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 + } #elif (RFM7x_MODULECHIP_USED == 4) | (RFM7x_MODULECHIP_USED == 5) // bk2411//bk2412//bk5811 -tmp |= ((level & 0x03) << 1) | ((level >> 2) << 4); // to optimize ? -rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); + tmp |= ((level & 0x03) << 1) | ((level >> 2) << 4); // to optimize ? + rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); #endif } void rfm7x_set_lna_gain(uint8_t enable) { -uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); -if (enable) - tmp |= RFM7x_RF_SETUP_LNA_HCURR; -else - tmp &= ~(RFM7x_RF_SETUP_LNA_HCURR); + if (enable) + tmp |= RFM7x_RF_SETUP_LNA_HCURR; + else + tmp &= ~(RFM7x_RF_SETUP_LNA_HCURR); -rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); + rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); } void rfm7x_set_datarate(uint8_t datarate) { -uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); #if (RFM7x_MODULECHIP_USED == 0) | (RFM7x_MODULECHIP_USED == 1) | (RFM7x_MODULECHIP_USED == 4) | (RFM7x_MODULECHIP_USED == 5) // bk2401/bk2421/bk2411/bk2412/bk5811 -tmp &= ~(RFM7x_RF_SETUP_RF_DR_HIGH); + tmp &= ~(RFM7x_RF_SETUP_RF_DR_HIGH); -if (datarate & 0x01) - tmp |= RFM7x_RF_SETUP_RF_DR_HIGH; + if (datarate & 0x01) + tmp |= RFM7x_RF_SETUP_RF_DR_HIGH; - //tmp |= ((datarate & 0x01) << 3); + //tmp |= ((datarate & 0x01) << 3); #elif (RFM7x_MODULECHIP_USED == 2) | (RFM7x_MODULECHIP_USED == 3) // bk2423/bk2425 -tmp &= ~(RFM7x_RF_SETUP_RF_DR_HIGH | RFM7x_RF_SETUP_RF_DR_LOW); + tmp &= ~(RFM7x_RF_SETUP_RF_DR_HIGH | RFM7x_RF_SETUP_RF_DR_LOW); -if (datarate & 0x01) - tmp |= RFM7x_RF_SETUP_RF_DR_HIGH; + if (datarate & 0x01) + tmp |= RFM7x_RF_SETUP_RF_DR_HIGH; -if (datarate & 0x02) - tmp |= RFM7x_RF_SETUP_RF_DR_LOW; + if (datarate & 0x02) + tmp |= RFM7x_RF_SETUP_RF_DR_LOW; - //tmp |= ((datarate & 0x01) << 3)|(((datarate >> 1) & 0x01) << 5); + //tmp |= ((datarate & 0x01) << 3)|(((datarate >> 1) & 0x01) << 5); #endif -rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); + rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); } #if (RFM7x_MODULECHIP_USED == 4) || (RFM7x_MODULECHIP_USED == 5) void rfm7x_enable_rssi_measurements(uint8_t enable) { -uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); -if (enable) - tmp |= RFM7x_RF_SETUP_RSSI_EN; -else - tmp &= ~(RFM7x_RF_SETUP_RSSI_EN); + if (enable) + tmp |= RFM7x_RF_SETUP_RSSI_EN; + else + tmp &= ~(RFM7x_RF_SETUP_RSSI_EN); -rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); + rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); } #endif #if (RFM7x_MODULECHIP_USED == 4) void rfm7x_dreg_enable(uint8_t enable) { -uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_RF_SETUP); -if (enable) - tmp |= BK2411_RF_SETUP_DREG_ON; -else - tmp &= ~(BK2411_RF_SETUP_DREG_ON); + if (enable) + tmp |= BK2411_RF_SETUP_DREG_ON; + else + tmp &= ~(BK2411_RF_SETUP_DREG_ON); -rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); + rfm7x_reg_write(RFM7x_REG_RF_SETUP, tmp); } #endif void rfm7x_enable_pipe_autoack(uint8_t pipe, uint8_t enabled) { -uint8_t tmp = rfm7x_reg_read(RFM7x_REG_EN_AA); + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_EN_AA); -tmp &= ~(1 << pipe); + tmp &= ~(1 << pipe); -if (enabled) - tmp |= (1 << pipe); + if (enabled) + tmp |= (1 << pipe); -rfm7x_reg_write(RFM7x_REG_EN_AA, tmp); + rfm7x_reg_write(RFM7x_REG_EN_AA, tmp); } void rfm7x_enable_pipe_receive(uint8_t pipe, uint8_t enabled) { -uint8_t tmp = rfm7x_reg_read(RFM7x_REG_EN_RXADDR); + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_EN_RXADDR); -tmp &= ~(1 << pipe); + tmp &= ~(1 << pipe); -if (enabled) - tmp |= (1 << pipe); + if (enabled) + tmp |= (1 << pipe); -rfm7x_reg_write(RFM7x_REG_EN_RXADDR, tmp); + rfm7x_reg_write(RFM7x_REG_EN_RXADDR, tmp); } void rfm7x_enable_dynamic_payload_feature(uint8_t enable) { -uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); -tmp &= ~(RFM7x_FEATURE_EN_DPL); + tmp &= ~(RFM7x_FEATURE_EN_DPL); -if (enable) - tmp |= RFM7x_FEATURE_EN_DPL; + if (enable) + tmp |= RFM7x_FEATURE_EN_DPL; -rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); + rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); } void rfm7x_enable_ack_payload_feature(uint8_t enable) { -uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); -tmp &= ~(RFM7x_FEATURE_EN_ACK_PAY); + tmp &= ~(RFM7x_FEATURE_EN_ACK_PAY); -if (enable) - tmp |= RFM7x_FEATURE_EN_ACK_PAY; + if (enable) + tmp |= RFM7x_FEATURE_EN_ACK_PAY; -rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); + rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); } void rfm7x_enable_noack_payload_feature(uint8_t enable) { -uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); + uint8_t tmp = rfm7x_reg_read(RFM7x_REG_FEATURE); -tmp &= ~(RFM7x_FEATURE_EN_DYN_ACK); + tmp &= ~(RFM7x_FEATURE_EN_DYN_ACK); -if (enable) - tmp |= RFM7x_FEATURE_EN_DYN_ACK; + if (enable) + tmp |= RFM7x_FEATURE_EN_DYN_ACK; -rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); + rfm7x_reg_write(RFM7x_REG_FEATURE, tmp); } void rfm7x_set_transmit_address(uint8_t* addr) { -uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); -size += 2; -rfm7x_reg_buff_write(RFM7x_REG_TX_ADDR, addr, size); + uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); + size += 2; + rfm7x_reg_buff_write(RFM7x_REG_TX_ADDR, addr, size); } void rfm7x_open_writing_pipe(uint64_t addr) { -uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); -size += 2; + uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); + size += 2; -//initialize also RX0 ? -rfm7x_reg_buff_write(RFM7x_REG_TX_ADDR, (uint8_t*)&addr, size); // just push that onto the stack, forget about shifts + //initialize also RX0 ? + rfm7x_reg_buff_write(RFM7x_REG_TX_ADDR, (uint8_t*)&addr, size); // just push that onto the stack, forget about shifts } //pipe 1 and 2 (??) void rfm7x_set_receive_address(uint8_t pipe, uint8_t* addr) { -uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); -size += 2; -rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P0 + pipe, addr, size); + uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); + size += 2; + rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P0 + pipe, addr, size); } void rfm7x_open_reading_pipe(uint8_t pipe, uint64_t addr) { -rfm7x_enable_pipe_receive(pipe, 1); + rfm7x_enable_pipe_receive(pipe, 1); -if (pipe >= 2) { - rfm7x_reg_write(RFM7x_REG_RX_ADDR_P0 + pipe, (addr & 0xff)); -} else { - uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); - size += 2; + if (pipe >= 2) { + rfm7x_reg_write(RFM7x_REG_RX_ADDR_P0 + pipe, (addr & 0xff)); + } else { + uint8_t size = rfm7x_reg_read(RFM7x_REG_SETUP_AW); + size += 2; - rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P0 + pipe, (uint8_t*)&addr, size); // just push that onto the stack, forget about shifts // LE archs only ? -} + rfm7x_reg_buff_write(RFM7x_REG_RX_ADDR_P0 + pipe, (uint8_t*)&addr, size); // just push that onto the stack, forget about shifts // LE archs only ? + } } #if (RFM7x_MODULECHIP_USED == 5) @@ -852,55 +852,55 @@ const uint8_t rfm7x_swapbandtune_struct[] = // generic for all architectures // { #if (BK5811_BANK1_DEFAULT_BAND == 0) // 5.1GHz in rfm7x_init_struct - 0x04, 0x05, 0x78, 0x32, // reg 0 - 0xC0, 0x05, 0xAE, 0x00, // reg 1 // dummy - 0xE8, 0x80, 0x0C, 0xD2, // reg 2 - 0x19, 0x0D, 0x7D, 0x6D // reg 3 + 0x04, 0x05, 0x78, 0x32, // reg 0 + 0xC0, 0x05, 0xAE, 0x00, // reg 1 // dummy + 0xE8, 0x80, 0x0C, 0xD2, // reg 2 + 0x19, 0x0D, 0x7D, 0x6D // reg 3 #else //(BK5811_BANK1_DEFAULT_BAND == 1) // 5.8GHz in rfm7x_init_struct - 0x04, 0x05, 0x78, 0x33, // reg 0 - 0xC0, 0x05, 0xAE, 0x00, // reg 1 // dummy - 0xE8, 0x80, 0x8C, 0xD3, // reg 2 - 0x18, 0x0D, 0x7D, 0x6C // reg 3 + 0x04, 0x05, 0x78, 0x33, // reg 0 + 0xC0, 0x05, 0xAE, 0x00, // reg 1 // dummy + 0xE8, 0x80, 0x8C, 0xD3, // reg 2 + 0x18, 0x0D, 0x7D, 0x6C // reg 3 #endif }; void bk5811_set_frequency_band(uint8_t range) { #if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) -const __flash uint8_t* p_swapband_struct; + const __flash uint8_t* p_swapband_struct; #else -const uint8_t* p_swapband_struct; + const uint8_t* p_swapband_struct; #endif #if (BK5811_BANK1_DEFAULT_BAND == 0) // 5.1GHz in rfm7x_init_struct -if (range) - p_swapband_struct = rfm7x_init_struct; -else - p_swapband_struct = rfm7x_swapbandtune_struct; + if (range) + p_swapband_struct = rfm7x_init_struct; + else + p_swapband_struct = rfm7x_swapbandtune_struct; #else //(BK5811_BANK1_DEFAULT_BAND == 1) // 5.8GHz in rfm7x_init_struct -if (range) - p_swapband_struct = rfm7x_swapbandtune_struct; -else - p_swapband_struct = rfm7x_init_struct; + if (range) + p_swapband_struct = rfm7x_swapbandtune_struct; + else + p_swapband_struct = rfm7x_init_struct; #endif #ifdef RFM7x_ATOMIC_REG_ACCES -CRITICAL_SECTION + CRITICAL_SECTION #endif -{ - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 + { + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 1 - for (uint_fast8_t i = 0; i < 4; i++) { + for (uint_fast8_t i = 0; i < 4; i++) { #if defined(__AVR_ARCH__) && !defined(RFM7x_AVR_DO_NOT_PUT_INIT_STRUCT_IN_FLASH) - rfm7x_reg_buff_write_P(i, p_swapband_struct + i * 4, 4); + rfm7x_reg_buff_write_P(i, p_swapband_struct + i * 4, 4); #else - rfm7x_reg_buff_write(i, p_swapband_struct + i * 4, 4); + rfm7x_reg_buff_write(i, p_swapband_struct + i * 4, 4); #endif - } + } - rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 -} + rfm7x_cmd_write(RFM7x_CMD_ACTIVATE, 0x53); // toggle to bank 0 + } } #endif diff --git a/examples/rfm7xAndBk242xCompatiblity/rfm7x.h b/examples/rfm7xAndBk242xCompatiblity/rfm7x.h index 6474688bd..03faea710 100644 --- a/examples/rfm7xAndBk242xCompatiblity/rfm7x.h +++ b/examples/rfm7xAndBk242xCompatiblity/rfm7x.h @@ -2,9 +2,9 @@ #define RFM7x_H_ /************************************************************************************ - * Author: jnk0le@hotmail.com * - * https://github.com/jnk0le * - * This library is distributed under MIT license terms * + Author: jnk0le@hotmail.com + https://github.com/jnk0le + This library is distributed under MIT license terms ************************************************************************************/ #include "rfm7x_config.h" @@ -504,14 +504,14 @@ extern "C" { ////////////////////////////////////////////////////////////////// //?????? /*#if defined(RFM7x_TX_ADDRESS)&&defined(RFM7x_PIPE0_RX_ADDRESS)&&defined(RFM7x_PIPE1_RX_ADDRESS) -#define RFM7x_LONG_ADDR_ENTRIES 3 -#elif (defined(RFM7x_TX_ADDRESS)&&defined(RFM7x_PIPE0_RX_ADDRESS))||(defined(RFM7x_PIPE0_RX_ADDRESS)&&defined(RFM7x_PIPE1_RX_ADDRESS))||(defined(RFM7x_TX_ADDRESS)&&defined(RFM7x_PIPE1_RX_ADDRESS)) -#define RFM7x_LONG_ADDR_ENTRIES 2 -#elif defined(RFM7x_TX_ADDRESS)||defined(RFM7x_PIPE0_RX_ADDRESS)||defined(RFM7x_PIPE1_RX_ADDRESS) -#define RFM7x_LONG_ADDR_ENTRIES 1 -#else -#define RFM7x_LONG_ADDR_ENTRIES 0 -#endif*/ + #define RFM7x_LONG_ADDR_ENTRIES 3 + #elif (defined(RFM7x_TX_ADDRESS)&&defined(RFM7x_PIPE0_RX_ADDRESS))||(defined(RFM7x_PIPE0_RX_ADDRESS)&&defined(RFM7x_PIPE1_RX_ADDRESS))||(defined(RFM7x_TX_ADDRESS)&&defined(RFM7x_PIPE1_RX_ADDRESS)) + #define RFM7x_LONG_ADDR_ENTRIES 2 + #elif defined(RFM7x_TX_ADDRESS)||defined(RFM7x_PIPE0_RX_ADDRESS)||defined(RFM7x_PIPE1_RX_ADDRESS) + #define RFM7x_LONG_ADDR_ENTRIES 1 + #else + #define RFM7x_LONG_ADDR_ENTRIES 0 + #endif*/ ////////////////////////////////////////////////////////////////// @@ -551,43 +551,71 @@ void rfm7x_power_down(void); // this function will not wait for finishing any on void rfm7x_mode_receive(void); void rfm7x_mode_transmit(void); -inline void rfm7x_mode_standby(void) { RFM7x_CE_LOW; } +inline void rfm7x_mode_standby(void) { + RFM7x_CE_LOW; +} -inline uint8_t rfm7x_tx_fifo_full(void) { return (rfm7x_reg_read(RFM7x_REG_FIFO_STATUS) & RFM7x_FIFO_STATUS_TX_FULL) != 0; } -inline uint8_t rfm7x_tx_fifo_empty(void) { return (rfm7x_reg_read(RFM7x_REG_FIFO_STATUS) & RFM7x_FIFO_STATUS_TX_EMPTY) != 0; } +inline uint8_t rfm7x_tx_fifo_full(void) { + return (rfm7x_reg_read(RFM7x_REG_FIFO_STATUS) & RFM7x_FIFO_STATUS_TX_FULL) != 0; +} +inline uint8_t rfm7x_tx_fifo_empty(void) { + return (rfm7x_reg_read(RFM7x_REG_FIFO_STATUS) & RFM7x_FIFO_STATUS_TX_EMPTY) != 0; +} -inline uint8_t rfm7x_rx_fifo_full(void) { return (rfm7x_reg_read(RFM7x_REG_FIFO_STATUS) & RFM7x_FIFO_STATUS_RX_FULL) != 0; } -inline uint8_t rfm7x_rx_fifo_empty(void) { return (rfm7x_reg_read(RFM7x_REG_FIFO_STATUS) & RFM7x_FIFO_STATUS_RX_EMPTY) != 0; } +inline uint8_t rfm7x_rx_fifo_full(void) { + return (rfm7x_reg_read(RFM7x_REG_FIFO_STATUS) & RFM7x_FIFO_STATUS_RX_FULL) != 0; +} +inline uint8_t rfm7x_rx_fifo_empty(void) { + return (rfm7x_reg_read(RFM7x_REG_FIFO_STATUS) & RFM7x_FIFO_STATUS_RX_EMPTY) != 0; +} -inline uint8_t rfm7x_receive_next_pipe(void) { return (rfm7x_reg_read(RFM7x_REG_STATUS) >> 1) & 0x07; } -inline uint8_t rfm7x_receive_next_length(void) { return rfm7x_cmd_read(RFM7x_CMD_R_RX_PL_WID); } +inline uint8_t rfm7x_receive_next_pipe(void) { + return (rfm7x_reg_read(RFM7x_REG_STATUS) >> 1) & 0x07; +} +inline uint8_t rfm7x_receive_next_length(void) { + return rfm7x_cmd_read(RFM7x_CMD_R_RX_PL_WID); +} uint8_t rfm7x_receive(uint8_t* buff); // returns received length // 0x00 - nothing received, or empty packet void rfm7x_receive_nocheck(uint8_t* buff); uint8_t rfm7x_receive_p_(uint8_t* pipe, uint8_t* buff); // returns received length // 0x00 - nothing received static inline uint8_t rfm7x_receive_p(uint8_t* buff, uint8_t* pipe) __attribute__((always_inline)); -static inline uint8_t rfm7x_receive_p(uint8_t* buff, uint8_t* pipe) { return rfm7x_receive_p_(pipe, buff); } +static inline uint8_t rfm7x_receive_p(uint8_t* buff, uint8_t* pipe) { + return rfm7x_receive_p_(pipe, buff); +} -inline void rfm7x_receive_nocheck_s(uint8_t* buff, uint8_t length) { rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, length); } +inline void rfm7x_receive_nocheck_s(uint8_t* buff, uint8_t length) { + rfm7x_cmd_buff_read(RFM7x_CMD_R_RX_PAYLOAD, buff, length); +} uint8_t rfm7x_receive_s(uint8_t* buff, uint8_t length); // returns number of received pipe // 0x07 - nothing received uint8_t rfm7x_receive_f(uint8_t* buff, uint8_t* pipe, uint8_t* length); -inline void rfm7x_transmit(uint8_t* buff, uint8_t length) { rfm7x_cmd_buff_write(RFM7x_CMD_W_TX_PAYLOAD, buff, length); } -inline void rfm7x_transmit_noack(uint8_t* buff, uint8_t length) { rfm7x_cmd_buff_write(RFM7x_CMD_W_TX_PAYLOAD_NOACK, buff, length); } +inline void rfm7x_transmit(uint8_t* buff, uint8_t length) { + rfm7x_cmd_buff_write(RFM7x_CMD_W_TX_PAYLOAD, buff, length); +} +inline void rfm7x_transmit_noack(uint8_t* buff, uint8_t length) { + rfm7x_cmd_buff_write(RFM7x_CMD_W_TX_PAYLOAD_NOACK, buff, length); +} // used in RX mode // transmit message while ACK'ing received packet on selected pipe -inline void rfm7x_rx_ack_transmit(uint8_t pipe, uint8_t* buff, uint8_t length) { rfm7x_cmd_buff_write(RFM7x_CMD_W_ACK_PAYLOAD | pipe, buff, length); } +inline void rfm7x_rx_ack_transmit(uint8_t pipe, uint8_t* buff, uint8_t length) { + rfm7x_cmd_buff_write(RFM7x_CMD_W_ACK_PAYLOAD | pipe, buff, length); +} //uint8_t rfm7x_available(uint8_t *pipe); // normal receive mode // // reset irq flags?? void rfm7x_set_rssi_threshold_step(uint8_t level); // usually linear scale from 0 (-97/100dBm) to 15 (-67/70dBm) // bk2423 is also linearized by this function, some levels may be out of useable range (over -105dBm) -inline uint8_t rfm7x_read_CD(void) { return rfm7x_reg_read(RFM7x_REG_CD); } +inline uint8_t rfm7x_read_CD(void) { + return rfm7x_reg_read(RFM7x_REG_CD); +} //config -inline void rfm7x_set_channel(uint8_t channel) { rfm7x_reg_write(RFM7x_REG_RF_CH, channel); } // 0-83 , 0-127 , clears MAX_RT counter +inline void rfm7x_set_channel(uint8_t channel) { + rfm7x_reg_write(RFM7x_REG_RF_CH, channel); // 0-83 , 0-127 , clears MAX_RT counter +} void rfm7x_set_crc_length(uint8_t len); //bk2421/bk2423 aka rfm70/73 @@ -642,13 +670,19 @@ void rfm7x_dreg_enable(uint8_t enable); #endif //250us steps -inline void rfm7x_set_retransmits(uint8_t retransmits, uint8_t delay) { rfm7x_reg_write(RFM7x_REG_SETUP_RETR, (retransmits) | (delay << 4)); } +inline void rfm7x_set_retransmits(uint8_t retransmits, uint8_t delay) { + rfm7x_reg_write(RFM7x_REG_SETUP_RETR, (retransmits) | (delay << 4)); +} // 3 to 5 bytes (2 byte width is reserved) -inline void rfm7x_set_addres_width(uint8_t width) { rfm7x_reg_write(RFM7x_REG_SETUP_AW, width - 2); } +inline void rfm7x_set_addres_width(uint8_t width) { + rfm7x_reg_write(RFM7x_REG_SETUP_AW, width - 2); +} //0-32 -inline void rfm7x_set_rx_pyaload_size(uint8_t pipe, uint8_t size) { rfm7x_reg_write(RFM7x_REG_RX_PW_P0 + pipe, size); } +inline void rfm7x_set_rx_pyaload_size(uint8_t pipe, uint8_t size) { + rfm7x_reg_write(RFM7x_REG_RX_PW_P0 + pipe, size); +} //void rfm7x_set_receiving_pipes(uint8_t mask); //void rfm7x_set_autoack_pipes(uint8_t mask); @@ -668,7 +702,9 @@ void rfm7x_open_writing_pipe(uint64_t addr); //pipe 1 and 2 (??) void rfm7x_set_receive_address(uint8_t pipe, uint8_t* addr); // LSB first -inline void rfm7x_set_receive_address_pn(uint8_t pipe, uint8_t LSB_addr) { rfm7x_reg_write(RFM7x_REG_RX_ADDR_P0 + pipe, LSB_addr); } +inline void rfm7x_set_receive_address_pn(uint8_t pipe, uint8_t LSB_addr) { + rfm7x_reg_write(RFM7x_REG_RX_ADDR_P0 + pipe, LSB_addr); +} //all pipes void rfm7x_open_reading_pipe(uint8_t pipe, uint64_t addr); diff --git a/examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino b/examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino index 9ceedfb1d..c73ea6f39 100644 --- a/examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino +++ b/examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino @@ -42,7 +42,7 @@ void setup() Serial.begin(115200); while (!Serial) { - // some boards need to wait to ensure access to serial over USB + // some boards need to wait to ensure access to serial over USB } // initialize the transceiver on the SPI bus diff --git a/examples/rfm7xAndBk242xCompatiblity/rfm7x_hardware.cpp b/examples/rfm7xAndBk242xCompatiblity/rfm7x_hardware.cpp index 08897f487..218adac66 100644 --- a/examples/rfm7xAndBk242xCompatiblity/rfm7x_hardware.cpp +++ b/examples/rfm7xAndBk242xCompatiblity/rfm7x_hardware.cpp @@ -11,24 +11,24 @@ void rfm7x_io_init(void) //hardcoded at the moment { -RFM7x_CSN_HI; -RFM7x_CE_LOW; + RFM7x_CSN_HI; + RFM7x_CE_LOW; #if defined(USE_EXAMPLE_SPI_MEGA328) -//set ce to output -//set csn to output + //set ce to output + //set csn to output #elif defined(USE_EXAMPLE_SPI_XMEGA) -//PORTC.DIRSET = PIN4_bm | PIN1_bm; // as output + //PORTC.DIRSET = PIN4_bm | PIN1_bm; // as output #elif defined(USE_EXAMPLE_SPI_STM32F0) -//RCC->AHBENR |= RCC_AHBENR_GPIOAEN; + //RCC->AHBENR |= RCC_AHBENR_GPIOAEN; -//GPIOA->MODER |= (1 << __builtin_ctz(GPIO_MODER_MODER3)) | (1 << __builtin_ctz(GPIO_MODER_MODER4)); // set PA3 and PA4 to output + //GPIOA->MODER |= (1 << __builtin_ctz(GPIO_MODER_MODER3)) | (1 << __builtin_ctz(GPIO_MODER_MODER4)); // set PA3 and PA4 to output #elif defined(USE_EXAMPLE_SPI_ARDUINO) -pinMode(8, OUTPUT); // ce -pinMode(9, OUTPUT); //csn + pinMode(8, OUTPUT); // ce + pinMode(9, OUTPUT); //csn #else // soft \ //set ce to output \ //set csn to output @@ -38,143 +38,143 @@ pinMode(9, OUTPUT); //csn void spi_init(void) { #if defined(USE_EXAMPLE_SPI_MEGA328) -DDRB |= (1 << PB3) | (1 << PB5); // configure output pins -PORTB |= (1 << PB4); // pullup miso + DDRB |= (1 << PB3) | (1 << PB5); // configure output pins + PORTB |= (1 << PB4); // pullup miso -SPCR |= (1 << SPE) | (1 << MSTR); -SPSR |= (1 << SPI2X); + SPCR |= (1 << SPE) | (1 << MSTR); + SPSR |= (1 << SPI2X); #elif defined(USE_EXAMPLE_SPI_XMEGA) -PORTC.DIRSET = PIN5_bm | PIN7_bm; // sck , mosi -PORTC.PIN6CTRL = PORT_OPC_PULLUP_gc; // pullup miso -SPIC.CTRL = SPI_ENABLE_bm | SPI_MASTER_bm | SPI_MODE_0_gc | SPI_PRESCALER_DIV4_gc; // 32MHz/4 + PORTC.DIRSET = PIN5_bm | PIN7_bm; // sck , mosi + PORTC.PIN6CTRL = PORT_OPC_PULLUP_gc; // pullup miso + SPIC.CTRL = SPI_ENABLE_bm | SPI_MASTER_bm | SPI_MODE_0_gc | SPI_PRESCALER_DIV4_gc; // 32MHz/4 #elif defined(USE_EXAMPLE_SPI_STM32F0) -RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; -GPIOA->MODER |= (2 << __builtin_ctz(GPIO_MODER_MODER5)) | (2 << __builtin_ctz(GPIO_MODER_MODER6)) | (2 << __builtin_ctz(GPIO_MODER_MODER7)); // PA5, PA6, PA7 as alternate -//GPIOA->AFR[0] &= ~((0x0f << __builtin_ctz(GPIO_AFRL_AFR5))|(0x0f << __builtin_ctz(GPIO_AFRL_AFR6))|(0x0f << __builtin_ctz(GPIO_AFRL_AFR7))); -//GPIOA->AFR[0] |= (0 << __builtin_ctz(GPIO_AFRL_AFR5))|(0 << __builtin_ctz(GPIO_AFRL_AFR6))|(0 << __builtin_ctz(GPIO_AFRL_AFR7)); + RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; + GPIOA->MODER |= (2 << __builtin_ctz(GPIO_MODER_MODER5)) | (2 << __builtin_ctz(GPIO_MODER_MODER6)) | (2 << __builtin_ctz(GPIO_MODER_MODER7)); // PA5, PA6, PA7 as alternate + //GPIOA->AFR[0] &= ~((0x0f << __builtin_ctz(GPIO_AFRL_AFR5))|(0x0f << __builtin_ctz(GPIO_AFRL_AFR6))|(0x0f << __builtin_ctz(GPIO_AFRL_AFR7))); + //GPIOA->AFR[0] |= (0 << __builtin_ctz(GPIO_AFRL_AFR5))|(0 << __builtin_ctz(GPIO_AFRL_AFR6))|(0 << __builtin_ctz(GPIO_AFRL_AFR7)); -GPIOA->OSPEEDR |= (3 << __builtin_ctz(GPIO_OSPEEDR_OSPEEDR5)) | (3 << __builtin_ctz(GPIO_OSPEEDR_OSPEEDR7)); // set SCK and MOSI into high speed mode -GPIOA->PUPDR |= (1 << __builtin_ctz(GPIO_PUPDR_PUPDR6)); // pullup miso + GPIOA->OSPEEDR |= (3 << __builtin_ctz(GPIO_OSPEEDR_OSPEEDR5)) | (3 << __builtin_ctz(GPIO_OSPEEDR_OSPEEDR7)); // set SCK and MOSI into high speed mode + GPIOA->PUPDR |= (1 << __builtin_ctz(GPIO_PUPDR_PUPDR6)); // pullup miso -SPI1->CR2 |= SPI_CR2_FRXTH; // RXNE treshold at 1 byte -SPI1->CR1 = SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_SPE | (2 << __builtin_ctz(SPI_CR1_BR)) | SPI_CR1_MSTR; // soft NSS force to master, enable, PCLK/8, master -//SSOE ??? + SPI1->CR2 |= SPI_CR2_FRXTH; // RXNE treshold at 1 byte + SPI1->CR1 = SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_SPE | (2 << __builtin_ctz(SPI_CR1_BR)) | SPI_CR1_MSTR; // soft NSS force to master, enable, PCLK/8, master + //SSOE ??? #elif defined(USE_EXAMPLE_SPI_ARDUINO) -SPI.begin(); + SPI.begin(); -// necessary? -//SPI.setBitOrder(MSBFIRST); -//SPI.setDataMode(SPI_MODE0); -SPI.setClockDivider(SPI_CLOCK_DIV2); + // necessary? + //SPI.setBitOrder(MSBFIRST); + //SPI.setDataMode(SPI_MODE0); + SPI.setClockDivider(SPI_CLOCK_DIV2); #else -// can be optimized into single write if port wiring allows -SOFT_SPI_SCK_DIRSET(); -SOFT_SPI_MOSI_DIRSET(); -SOFT_SPI_MISO_DIRSET(); // always input after POR, can be commented out -SOFT_SPI_MISO_PULLUP_SET(); // ?? + // can be optimized into single write if port wiring allows + SOFT_SPI_SCK_DIRSET(); + SOFT_SPI_MOSI_DIRSET(); + SOFT_SPI_MISO_DIRSET(); // always input after POR, can be commented out + SOFT_SPI_MISO_PULLUP_SET(); // ?? #endif } uint8_t spi_rw(uint8_t data) { #if defined(USE_EXAMPLE_SPI_MEGA328) -SPDR = data; -while (!(SPSR & (1 << SPIF))) - ; + SPDR = data; + while (!(SPSR & (1 << SPIF))) + ; -return SPDR; + return SPDR; #elif defined(USE_EXAMPLE_SPI_XMEGA) -SPIC.DATA = dat; -while (!(SPIC.STATUS & (1 << 7))) - ; // no SPIF defined + SPIC.DATA = dat; + while (!(SPIC.STATUS & (1 << 7))) + ; // no SPIF defined -return SPIC.DATA; + return SPIC.DATA; #elif defined(USE_EXAMPLE_SPI_STM32F0) -while ((SPI1->SR & SPI_SR_BSY)) - ; -*(uint8_t*)&(SPI1->DR) = data; // cast to make 8 bit transfer and thus transmit only 8bit frame -while (!(SPI1->SR & SPI_SR_RXNE)) - ; -data = SPI1->DR; -return data; + while ((SPI1->SR & SPI_SR_BSY)) + ; + *(uint8_t*)&(SPI1->DR) = data; // cast to make 8 bit transfer and thus transmit only 8bit frame + while (!(SPI1->SR & SPI_SR_RXNE)) + ; + data = SPI1->DR; + return data; #elif defined(USE_EXAMPLE_SPI_ARDUINO) -uint8_t tmp = SPI.transfer(data); -return tmp; + uint8_t tmp = SPI.transfer(data); + return tmp; #else -for (uint_fast8_t i = 0; i < 8; i++) { - if (data & 0x80) - SOFT_SPI_MOSI_HI(); - else - SOFT_SPI_MOSI_LO(); - - //_delay_us(0.125); - //_delay_us(1); - delayMicroseconds(1); - SOFT_SPI_SCK_HI(); - delayMicroseconds(1); - // _delay_us(1); - - data <<= 1; - - if (SOFT_SPI_MISO_READ()) - data |= 0x01; // data++ - - // _delay_us(0.125); - delayMicroseconds(1); - SOFT_SPI_SCK_LO(); - // _delay_us(0.125); - delayMicroseconds(1); -} - -return data; + for (uint_fast8_t i = 0; i < 8; i++) { + if (data & 0x80) + SOFT_SPI_MOSI_HI(); + else + SOFT_SPI_MOSI_LO(); + + //_delay_us(0.125); + //_delay_us(1); + delayMicroseconds(1); + SOFT_SPI_SCK_HI(); + delayMicroseconds(1); + // _delay_us(1); + + data <<= 1; + + if (SOFT_SPI_MISO_READ()) + data |= 0x01; // data++ + + // _delay_us(0.125); + delayMicroseconds(1); + SOFT_SPI_SCK_LO(); + // _delay_us(0.125); + delayMicroseconds(1); + } + + return data; #endif } void spi_reg_write(uint8_t reg, uint8_t dat) { -spi_rw(reg); -spi_rw(dat); + spi_rw(reg); + spi_rw(dat); } uint8_t spi_reg_read(uint8_t reg) { -uint8_t tmp; + uint8_t tmp; -spi_rw(reg); -tmp = spi_rw(0); + spi_rw(reg); + tmp = spi_rw(0); -return tmp; // spi_rw(spi_rw(reg)) + return tmp; // spi_rw(spi_rw(reg)) } void spi_reg_buff_write(uint8_t reg, uint8_t* buff, uint8_t len) { -spi_rw(reg); + spi_rw(reg); -for (uint8_t i = 0; i < len; i++) - spi_rw(buff[i]); + for (uint8_t i = 0; i < len; i++) + spi_rw(buff[i]); } void spi_buff_write(uint8_t* buff, uint8_t len) { -for (uint_fast8_t i = 0; i < len; i++) - spi_rw(buff[i]); + for (uint_fast8_t i = 0; i < len; i++) + spi_rw(buff[i]); } void spi_reg_buff_read(uint8_t reg, uint8_t* buff, uint8_t len) { -spi_rw(reg); + spi_rw(reg); -for (uint8_t i = 0; i < len; i++) - buff[i] = spi_rw(0); + for (uint8_t i = 0; i < len; i++) + buff[i] = spi_rw(0); } void spi_buff_read(uint8_t* buff, uint8_t len) { -for (uint_fast8_t i = 0; i < len; i++) - buff[i] = spi_rw(0); + for (uint_fast8_t i = 0; i < len; i++) + buff[i] = spi_rw(0); } From 0fc3cbb55043a818f9f0b6c73fae1d482444d7ef Mon Sep 17 00:00:00 2001 From: Tony Date: Fri, 26 Mar 2021 17:40:32 +0100 Subject: [PATCH 5/5] swapped order of init code in example --- .../rfm7xAndBk242xCompatiblity.ino | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino b/examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino index c73ea6f39..cecbafcf2 100644 --- a/examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino +++ b/examples/rfm7xAndBk242xCompatiblity/rfm7xAndBk242xCompatiblity.ino @@ -2,6 +2,7 @@ * See documentation at https://nRF24.github.io/RF24 * See License information at root directory of this library * Author: Brendan Doherty (2bndy5) + * Adapted for RFM75 by microtronics */ /** @@ -45,12 +46,6 @@ void setup() // some boards need to wait to ensure access to serial over USB } - // initialize the transceiver on the SPI bus - if (!radio.begin()) { - Serial.println(F("radio hardware is not responding!!")); - while (1) { } // hold in infinite loop - } - rfm7x_io_init(); spi_init(); if (rfm7x_is_present()) { @@ -62,6 +57,12 @@ void setup() delay(1); } + // initialize the transceiver on the SPI bus + if (!radio.begin()) { + Serial.println(F("radio hardware is not responding!!")); + while (1) { } // hold in infinite loop + } + // print example's introductory prompt Serial.println(F("RF24/examples/rfm7xAndBk242xCompatiblity"));