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LimeSDR-XTRX_gold.tcl
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LimeSDR-XTRX_gold.tcl
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#*****************************************************************************************
# Vivado (TM) v2022.1 (64-bit)
#
# LimeSDR-XTRX_gold.tcl: Tcl script for re-creating project 'LimeSDR-XTRX_gold'
#
# Generated by Vivado on Thu Jul 11 16:45:21 +0300 2024
# IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
# original project, however they will not be launched automatically. To regenerate the
# run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# NOTE: In order to use this script for source control purposes, please make sure that the
# following files are added to the source control system:-
#
# 1. This project restoration tcl script (LimeSDR-XTRX_gold.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
# <none>
#
# 3. The following remote source files that were added to the original project:-
#
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/ip/rx_pll/rx_pll/rx_pll.xci"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/ip/tx_pll/tx_pll/tx_pll.xci"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/ip/idelay_refclk_pll/idelay_refclk_pll/idelay_refclk_pll.xci"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/ip/pcie/pcie_s7/pcie_s7.xci"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/litepcie_gen/build/gateware/litepcie_core.v"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/packages/FIFO_PACK.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/packages/axi_pkg.vhdl"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/bit_pack/synth/pack_48_to_64.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/bit_pack/synth/pack_56_to_64.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/bit_pack/synth/bit_pack.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/tx_path_top/bit_unpack/synth/unpack_64_to_48.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/tx_path_top/bit_unpack/synth/unpack_64_to_64.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/tx_path_top/bit_unpack/synth/bit_unpack_64.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/general/bus_sync_reg.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/spi/fpgacfg_pkg.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/spi/pllcfg_pkg.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/spi/tstcfg_pkg.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/spi/periphcfg_pkg.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/spi/memcfg_pkg.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/spi/mem_package.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/revision/revisions_golden.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/spi/mcfg_components.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/spi/mcfg32wm_fsm.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/spi/fpgacfg.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/spi/pllcfg.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/spi/tstcfg.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/spi/periphcfg.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/spi/memcfg.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/spi/cfg_top.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/self_test/clk_no_ref_test.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/self_test/clock_test.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/pll_reconfig_ctrl/config_ctrl.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/data2packets/synth/data2packets.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/data2packets/synth/data2packets128.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/data2packets/synth/data2packets_fsm.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/data2packets/synth/data2packets_top.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/tx_path_top/fifo2diq/synth/edge_delay.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/altera_inst/fifo_inst.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/general/general_pkg.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/self_test/gnss_data_gen.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/uart/synth/uart.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/self_test/gnss_uart_test.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/altera_inst/lpm_cnt_inst.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/smpl_cnt/synth/iq_smpl_cnt.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/misc/led_ctrl_golden.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/litepcie/litepcie_pkg.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/litepcie/litepcie_top.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/altera_inst/lms7002_ddin.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/altera_inst/lms7002_ddout.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/general/sync_reg.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/diq2fifo/synth/rxiq_siso_sdr.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/diq2fifo/synth/rxiq_siso_ddr.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/diq2fifo/synth/rxiq_siso.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/diq2fifo/synth/rxiq_mimo_ddr.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/diq2fifo/synth/rxiq_pulse_ddr.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/diq2fifo/synth/rxiq_mimo.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/diq2fifo/synth/rxiq.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/diq2fifo/synth/test_data_dd.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/smpl_cmp/synth/smpl_cmp.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/diq2fifo/synth/diq2fifo.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/tx_path_top/fifo2diq/synth/txiq.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/tx_path_top/fifo2diq/synth/txiq_ctrl.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/tx_path_top/fifo2diq/synth/fifo2diq.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/txiqmux/synth/txiq_tst_ptrn.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/txiqmux/synth/txiqmux.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/lms7002/synth/lms7002_tx.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/lms7002/lms7002_top.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/tx_path_top/pct_separate/synth/pct_separate_fsm.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/tx_path_top/pct_separate/synth/one_pct_fifo.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/altera_inst/lpm_compare_inst.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/tx_path_top/packets2data/synth/p2d_rd.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/tx_path_top/packets2data/synth/p2d_wr_fsm.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/tx_path_top/packets2data/synth/packets2data.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/wfm_ram_buffer/pct_payload_extrct.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/pcie/wr_stream_buff.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/general/shift_reg.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/pcie/wr_control_buff.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/pcie/rd_stream_buff.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/resize_fifoword/resize_fifoword.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/pcie/rd_control_buff.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/pcie/pcie_top.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/packages/pll_top_blackbox_pkg.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/tx_path_top/pulse_gen/synth/pulse_gen.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/smpl_cnt/synth/smpl_cnt.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_path_top/rx_path/synth/rx_path_top.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/self_test/singl_clk_with_ref_test.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/tx_path_top/tx_path/synth/sync_fifo_rw.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/misc/tdd_control.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/self_test/tst_top.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/tx_path_top/bit_unpack/synth/unpack_128_to_48.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/tx_path_top/packets2data/synth/packets2data_top.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/tx_path_top/tx_path/synth/tx_path_top.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/tx_pll_top/synth/tx_pll_top.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/cpu/cpu_top.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rx_pll_top/synth/rx_pll_top.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/pll_top/pll_top.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/rxtx_top/synth/rxtx_top.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/hdl/top/LimeSDR_XTRX_top.vhd"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/ip/litex_pcie_phy/pcie_pipe_clock.v"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/ip/litex_pcie_phy/pcie_s7_support.v"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/mb_elf/cpu.elf"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/constrs/xtrxr5_ucf_mod.xdc"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/constrs/litepcie_constrs.xdc"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/constrs/lms7_timing.xdc"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/constrs/constrs_target_golden.xdc"
# "D:/work_dir/LimeSDR-XTRX/LimeSDR-XTRX_GW/src/mb_elf/cpu.elf"
#
#*****************************************************************************************
# Check file required for this script exists
proc checkRequiredFiles { origin_dir} {
set status true
set files [list \
"[file normalize "$origin_dir/ip/rx_pll/rx_pll/rx_pll.xci"]"\
"[file normalize "$origin_dir/ip/tx_pll/tx_pll/tx_pll.xci"]"\
"[file normalize "$origin_dir/ip/idelay_refclk_pll/idelay_refclk_pll/idelay_refclk_pll.xci"]"\
"[file normalize "$origin_dir/ip/pcie/pcie_s7/pcie_s7.xci"]"\
"[file normalize "$origin_dir/litepcie_gen/build/gateware/litepcie_core.v"]"\
"[file normalize "$origin_dir/src/hdl/packages/FIFO_PACK.vhd"]"\
"[file normalize "$origin_dir/src/hdl/packages/axi_pkg.vhdl"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/bit_pack/synth/pack_48_to_64.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/bit_pack/synth/pack_56_to_64.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/bit_pack/synth/bit_pack.vhd"]"\
"[file normalize "$origin_dir/src/hdl/tx_path_top/bit_unpack/synth/unpack_64_to_48.vhd"]"\
"[file normalize "$origin_dir/src/hdl/tx_path_top/bit_unpack/synth/unpack_64_to_64.vhd"]"\
"[file normalize "$origin_dir/src/hdl/tx_path_top/bit_unpack/synth/bit_unpack_64.vhd"]"\
"[file normalize "$origin_dir/src/hdl/general/bus_sync_reg.vhd"]"\
"[file normalize "$origin_dir/src/hdl/spi/fpgacfg_pkg.vhd"]"\
"[file normalize "$origin_dir/src/hdl/spi/pllcfg_pkg.vhd"]"\
"[file normalize "$origin_dir/src/hdl/spi/tstcfg_pkg.vhd"]"\
"[file normalize "$origin_dir/src/hdl/spi/periphcfg_pkg.vhd"]"\
"[file normalize "$origin_dir/src/hdl/spi/memcfg_pkg.vhd"]"\
"[file normalize "$origin_dir/src/hdl/spi/mem_package.vhd"]"\
"[file normalize "$origin_dir/src/hdl/revision/revisions_golden.vhd"]"\
"[file normalize "$origin_dir/src/hdl/spi/mcfg_components.vhd"]"\
"[file normalize "$origin_dir/src/hdl/spi/mcfg32wm_fsm.vhd"]"\
"[file normalize "$origin_dir/src/hdl/spi/fpgacfg.vhd"]"\
"[file normalize "$origin_dir/src/hdl/spi/pllcfg.vhd"]"\
"[file normalize "$origin_dir/src/hdl/spi/tstcfg.vhd"]"\
"[file normalize "$origin_dir/src/hdl/spi/periphcfg.vhd"]"\
"[file normalize "$origin_dir/src/hdl/spi/memcfg.vhd"]"\
"[file normalize "$origin_dir/src/hdl/spi/cfg_top.vhd"]"\
"[file normalize "$origin_dir/src/hdl/self_test/clk_no_ref_test.vhd"]"\
"[file normalize "$origin_dir/src/hdl/self_test/clock_test.vhd"]"\
"[file normalize "$origin_dir/src/hdl/pll_reconfig_ctrl/config_ctrl.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/data2packets/synth/data2packets.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/data2packets/synth/data2packets128.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/data2packets/synth/data2packets_fsm.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/data2packets/synth/data2packets_top.vhd"]"\
"[file normalize "$origin_dir/src/hdl/tx_path_top/fifo2diq/synth/edge_delay.vhd"]"\
"[file normalize "$origin_dir/src/hdl/altera_inst/fifo_inst.vhd"]"\
"[file normalize "$origin_dir/src/hdl/general/general_pkg.vhd"]"\
"[file normalize "$origin_dir/src/hdl/self_test/gnss_data_gen.vhd"]"\
"[file normalize "$origin_dir/src/hdl/uart/synth/uart.vhd"]"\
"[file normalize "$origin_dir/src/hdl/self_test/gnss_uart_test.vhd"]"\
"[file normalize "$origin_dir/src/hdl/altera_inst/lpm_cnt_inst.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/smpl_cnt/synth/iq_smpl_cnt.vhd"]"\
"[file normalize "$origin_dir/src/hdl/misc/led_ctrl_golden.vhd"]"\
"[file normalize "$origin_dir/src/hdl/litepcie/litepcie_pkg.vhd"]"\
"[file normalize "$origin_dir/src/hdl/litepcie/litepcie_top.vhd"]"\
"[file normalize "$origin_dir/src/hdl/altera_inst/lms7002_ddin.vhd"]"\
"[file normalize "$origin_dir/src/hdl/altera_inst/lms7002_ddout.vhd"]"\
"[file normalize "$origin_dir/src/hdl/general/sync_reg.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/diq2fifo/synth/rxiq_siso_sdr.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/diq2fifo/synth/rxiq_siso_ddr.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/diq2fifo/synth/rxiq_siso.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/diq2fifo/synth/rxiq_mimo_ddr.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/diq2fifo/synth/rxiq_pulse_ddr.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/diq2fifo/synth/rxiq_mimo.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/diq2fifo/synth/rxiq.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/diq2fifo/synth/test_data_dd.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/smpl_cmp/synth/smpl_cmp.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/diq2fifo/synth/diq2fifo.vhd"]"\
"[file normalize "$origin_dir/src/hdl/tx_path_top/fifo2diq/synth/txiq.vhd"]"\
"[file normalize "$origin_dir/src/hdl/tx_path_top/fifo2diq/synth/txiq_ctrl.vhd"]"\
"[file normalize "$origin_dir/src/hdl/tx_path_top/fifo2diq/synth/fifo2diq.vhd"]"\
"[file normalize "$origin_dir/src/hdl/txiqmux/synth/txiq_tst_ptrn.vhd"]"\
"[file normalize "$origin_dir/src/hdl/txiqmux/synth/txiqmux.vhd"]"\
"[file normalize "$origin_dir/src/hdl/lms7002/synth/lms7002_tx.vhd"]"\
"[file normalize "$origin_dir/src/hdl/lms7002/lms7002_top.vhd"]"\
"[file normalize "$origin_dir/src/hdl/tx_path_top/pct_separate/synth/pct_separate_fsm.vhd"]"\
"[file normalize "$origin_dir/src/hdl/tx_path_top/pct_separate/synth/one_pct_fifo.vhd"]"\
"[file normalize "$origin_dir/src/hdl/altera_inst/lpm_compare_inst.vhd"]"\
"[file normalize "$origin_dir/src/hdl/tx_path_top/packets2data/synth/p2d_rd.vhd"]"\
"[file normalize "$origin_dir/src/hdl/tx_path_top/packets2data/synth/p2d_wr_fsm.vhd"]"\
"[file normalize "$origin_dir/src/hdl/tx_path_top/packets2data/synth/packets2data.vhd"]"\
"[file normalize "$origin_dir/src/hdl/wfm_ram_buffer/pct_payload_extrct.vhd"]"\
"[file normalize "$origin_dir/src/hdl/pcie/wr_stream_buff.vhd"]"\
"[file normalize "$origin_dir/src/hdl/general/shift_reg.vhd"]"\
"[file normalize "$origin_dir/src/hdl/pcie/wr_control_buff.vhd"]"\
"[file normalize "$origin_dir/src/hdl/pcie/rd_stream_buff.vhd"]"\
"[file normalize "$origin_dir/src/hdl/resize_fifoword/resize_fifoword.vhd"]"\
"[file normalize "$origin_dir/src/hdl/pcie/rd_control_buff.vhd"]"\
"[file normalize "$origin_dir/src/hdl/pcie/pcie_top.vhd"]"\
"[file normalize "$origin_dir/src/hdl/packages/pll_top_blackbox_pkg.vhd"]"\
"[file normalize "$origin_dir/src/hdl/tx_path_top/pulse_gen/synth/pulse_gen.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/smpl_cnt/synth/smpl_cnt.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_path_top/rx_path/synth/rx_path_top.vhd"]"\
"[file normalize "$origin_dir/src/hdl/self_test/singl_clk_with_ref_test.vhd"]"\
"[file normalize "$origin_dir/src/hdl/tx_path_top/tx_path/synth/sync_fifo_rw.vhd"]"\
"[file normalize "$origin_dir/src/hdl/misc/tdd_control.vhd"]"\
"[file normalize "$origin_dir/src/hdl/self_test/tst_top.vhd"]"\
"[file normalize "$origin_dir/src/hdl/tx_path_top/bit_unpack/synth/unpack_128_to_48.vhd"]"\
"[file normalize "$origin_dir/src/hdl/tx_path_top/packets2data/synth/packets2data_top.vhd"]"\
"[file normalize "$origin_dir/src/hdl/tx_path_top/tx_path/synth/tx_path_top.vhd"]"\
"[file normalize "$origin_dir/src/hdl/tx_pll_top/synth/tx_pll_top.vhd"]"\
"[file normalize "$origin_dir/src/hdl/cpu/cpu_top.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rx_pll_top/synth/rx_pll_top.vhd"]"\
"[file normalize "$origin_dir/src/hdl/pll_top/pll_top.vhd"]"\
"[file normalize "$origin_dir/src/hdl/rxtx_top/synth/rxtx_top.vhd"]"\
"[file normalize "$origin_dir/src/hdl/top/LimeSDR_XTRX_top.vhd"]"\
"[file normalize "$origin_dir/ip/litex_pcie_phy/pcie_pipe_clock.v"]"\
"[file normalize "$origin_dir/ip/litex_pcie_phy/pcie_s7_support.v"]"\
"[file normalize "$origin_dir/src/mb_elf/cpu.elf"]"\
"[file normalize "$origin_dir/src/constrs/xtrxr5_ucf_mod.xdc"]"\
"[file normalize "$origin_dir/src/constrs/litepcie_constrs.xdc"]"\
"[file normalize "$origin_dir/src/constrs/lms7_timing.xdc"]"\
"[file normalize "$origin_dir/src/constrs/constrs_target_golden.xdc"]"\
"[file normalize "$origin_dir/src/mb_elf/cpu.elf"]"\
]
foreach ifile $files {
if { ![file isfile $ifile] } {
puts " Could not find remote file $ifile "
set status false
}
}
set paths [list \
"[file normalize "$origin_dir/[file normalize "$origin_dir/ip_repo/myip_1.0"]"]"\
"[file normalize "$origin_dir/[file normalize "$origin_dir/ip/ip_repo"]"]"\
]
foreach ipath $paths {
if { ![file isdirectory $ipath] } {
puts " Could not access $ipath "
set status false
}
}
return $status
}
# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir "."
# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
set origin_dir $::origin_dir_loc
}
# Set the project name
set _xil_proj_name_ "LimeSDR-XTRX_gold"
# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
set _xil_proj_name_ $::user_project_name
}
variable script_file
set script_file "LimeSDR-XTRX_gold.tcl"
# Help information for this script
proc print_help {} {
variable script_file
puts "\nDescription:"
puts "Recreate a Vivado project from this script. The created project will be"
puts "functionally equivalent to the original project for which this script was"
puts "generated. The script contains commands for creating a project, filesets,"
puts "runs, adding/importing sources and setting properties on various objects.\n"
puts "Syntax:"
puts "$script_file"
puts "$script_file -tclargs \[--origin_dir <path>\]"
puts "$script_file -tclargs \[--project_name <name>\]"
puts "$script_file -tclargs \[--help\]\n"
puts "Usage:"
puts "Name Description"
puts "-------------------------------------------------------------------------"
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
puts " origin_dir path value is \".\", otherwise, the value"
puts " that was set with the \"-paths_relative_to\" switch"
puts " when this script was generated.\n"
puts "\[--project_name <name>\] Create project with the specified name. Default"
puts " name is the name of the project from where this"
puts " script was generated.\n"
puts "\[--help\] Print help information for this script"
puts "-------------------------------------------------------------------------\n"
exit 0
}
if { $::argc > 0 } {
for {set i 0} {$i < $::argc} {incr i} {
set option [string trim [lindex $::argv $i]]
switch -regexp -- $option {
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
"--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
"--help" { print_help }
default {
if { [regexp {^-} $option] } {
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
return 1
}
}
}
}
}
# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/LimeSDR-XTRX_gold"]"
# Check for paths and files needed for project creation
set validate_required 0
if { $validate_required } {
if { [checkRequiredFiles $origin_dir] } {
puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
} else {
puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
return
}
}
# Create project
create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7a50tcpg236-2
# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]
# Set project properties
set obj [current_project]
set_property -name "board_part" -value "" -objects $obj
set_property -name "classic_soc_boot" -value "0" -objects $obj
set_property -name "compxlib.activehdl_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/activehdl" -objects $obj
set_property -name "compxlib.funcsim" -value "1" -objects $obj
set_property -name "compxlib.modelsim_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/modelsim" -objects $obj
set_property -name "compxlib.overwrite_libs" -value "0" -objects $obj
set_property -name "compxlib.questa_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/questa" -objects $obj
set_property -name "compxlib.riviera_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/riviera" -objects $obj
set_property -name "compxlib.timesim" -value "1" -objects $obj
set_property -name "compxlib.vcs_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/vcs" -objects $obj
set_property -name "compxlib.xsim_compiled_library_dir" -value "" -objects $obj
set_property -name "corecontainer.enable" -value "0" -objects $obj
set_property -name "customized_default_ip_location" -value "" -objects $obj
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "enable_optional_runs_sta" -value "0" -objects $obj
set_property -name "enable_resource_estimation" -value "0" -objects $obj
set_property -name "enable_vhdl_2008" -value "1" -objects $obj
set_property -name "generate_ip_upgrade_log" -value "1" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_interface_inference_priority" -value "" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
set_property -name "legacy_ip_repo_paths" -value "" -objects $obj
set_property -name "local_ip_repo_leaf_dir_name" -value "ip_repo" -objects $obj
set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
set_property -name "part" -value "xc7a50tcpg236-2" -objects $obj
set_property -name "platform.default_output_type" -value "undefined" -objects $obj
set_property -name "platform.design_intent.datacenter" -value "undefined" -objects $obj
set_property -name "platform.design_intent.embedded" -value "undefined" -objects $obj
set_property -name "platform.design_intent.external_host" -value "undefined" -objects $obj
set_property -name "platform.design_intent.server_managed" -value "undefined" -objects $obj
set_property -name "platform.rom.debug_type" -value "0" -objects $obj
set_property -name "platform.rom.prom_type" -value "0" -objects $obj
set_property -name "platform.slrconstraintmode" -value "0" -objects $obj
set_property -name "preferred_sim_model" -value "rtl" -objects $obj
set_property -name "project_type" -value "Default" -objects $obj
set_property -name "pr_flow" -value "0" -objects $obj
set_property -name "revised_directory_structure" -value "1" -objects $obj
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "sim.use_ip_compiled_libs" -value "1" -objects $obj
set_property -name "simulator.activehdl_gcc_install_dir" -value "" -objects $obj
set_property -name "simulator.activehdl_install_dir" -value "" -objects $obj
set_property -name "simulator.modelsim_gcc_install_dir" -value "" -objects $obj
set_property -name "simulator.modelsim_install_dir" -value "" -objects $obj
set_property -name "simulator.questa_gcc_install_dir" -value "" -objects $obj
set_property -name "simulator.questa_install_dir" -value "" -objects $obj
set_property -name "simulator.riviera_gcc_install_dir" -value "" -objects $obj
set_property -name "simulator.riviera_install_dir" -value "" -objects $obj
set_property -name "simulator.vcs_gcc_install_dir" -value "" -objects $obj
set_property -name "simulator.vcs_install_dir" -value "" -objects $obj
set_property -name "simulator.xcelium_gcc_install_dir" -value "" -objects $obj
set_property -name "simulator.xcelium_install_dir" -value "" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "source_mgmt_mode" -value "All" -objects $obj
set_property -name "target_language" -value "Verilog" -objects $obj
set_property -name "target_simulator" -value "XSim" -objects $obj
set_property -name "tool_flow" -value "Vivado" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "81" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "81" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "81" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "81" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "81" -objects $obj
set_property -name "webtalk.xcelium_export_sim" -value "1" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "81" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj
set_property -name "xsim.array_display_limit" -value "1024" -objects $obj
set_property -name "xsim.radix" -value "hex" -objects $obj
set_property -name "xsim.time_unit" -value "ns" -objects $obj
set_property -name "xsim.trace_limit" -value "65536" -objects $obj
# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
create_fileset -srcset sources_1
}
# Set IP repository paths
set obj [get_filesets sources_1]
if { $obj != {} } {
set_property "ip_repo_paths" "[file normalize "$origin_dir/ip_repo/myip_1.0"] [file normalize "$origin_dir/ip/ip_repo"]" $obj
# Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild
}
# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
[file normalize "${origin_dir}/ip/rx_pll/rx_pll/rx_pll.xci"] \
[file normalize "${origin_dir}/ip/tx_pll/tx_pll/tx_pll.xci"] \
[file normalize "${origin_dir}/ip/idelay_refclk_pll/idelay_refclk_pll/idelay_refclk_pll.xci"] \
[file normalize "${origin_dir}/ip/pcie/pcie_s7/pcie_s7.xci"] \
[file normalize "${origin_dir}/litepcie_gen/build/gateware/litepcie_core.v"] \
[file normalize "${origin_dir}/src/hdl/packages/FIFO_PACK.vhd"] \
[file normalize "${origin_dir}/src/hdl/packages/axi_pkg.vhdl"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/bit_pack/synth/pack_48_to_64.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/bit_pack/synth/pack_56_to_64.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/bit_pack/synth/bit_pack.vhd"] \
[file normalize "${origin_dir}/src/hdl/tx_path_top/bit_unpack/synth/unpack_64_to_48.vhd"] \
[file normalize "${origin_dir}/src/hdl/tx_path_top/bit_unpack/synth/unpack_64_to_64.vhd"] \
[file normalize "${origin_dir}/src/hdl/tx_path_top/bit_unpack/synth/bit_unpack_64.vhd"] \
[file normalize "${origin_dir}/src/hdl/general/bus_sync_reg.vhd"] \
[file normalize "${origin_dir}/src/hdl/spi/fpgacfg_pkg.vhd"] \
[file normalize "${origin_dir}/src/hdl/spi/pllcfg_pkg.vhd"] \
[file normalize "${origin_dir}/src/hdl/spi/tstcfg_pkg.vhd"] \
[file normalize "${origin_dir}/src/hdl/spi/periphcfg_pkg.vhd"] \
[file normalize "${origin_dir}/src/hdl/spi/memcfg_pkg.vhd"] \
[file normalize "${origin_dir}/src/hdl/spi/mem_package.vhd"] \
[file normalize "${origin_dir}/src/hdl/revision/revisions_golden.vhd"] \
[file normalize "${origin_dir}/src/hdl/spi/mcfg_components.vhd"] \
[file normalize "${origin_dir}/src/hdl/spi/mcfg32wm_fsm.vhd"] \
[file normalize "${origin_dir}/src/hdl/spi/fpgacfg.vhd"] \
[file normalize "${origin_dir}/src/hdl/spi/pllcfg.vhd"] \
[file normalize "${origin_dir}/src/hdl/spi/tstcfg.vhd"] \
[file normalize "${origin_dir}/src/hdl/spi/periphcfg.vhd"] \
[file normalize "${origin_dir}/src/hdl/spi/memcfg.vhd"] \
[file normalize "${origin_dir}/src/hdl/spi/cfg_top.vhd"] \
[file normalize "${origin_dir}/src/hdl/self_test/clk_no_ref_test.vhd"] \
[file normalize "${origin_dir}/src/hdl/self_test/clock_test.vhd"] \
[file normalize "${origin_dir}/src/hdl/pll_reconfig_ctrl/config_ctrl.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/data2packets/synth/data2packets.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/data2packets/synth/data2packets128.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/data2packets/synth/data2packets_fsm.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/data2packets/synth/data2packets_top.vhd"] \
[file normalize "${origin_dir}/src/hdl/tx_path_top/fifo2diq/synth/edge_delay.vhd"] \
[file normalize "${origin_dir}/src/hdl/altera_inst/fifo_inst.vhd"] \
[file normalize "${origin_dir}/src/hdl/general/general_pkg.vhd"] \
[file normalize "${origin_dir}/src/hdl/self_test/gnss_data_gen.vhd"] \
[file normalize "${origin_dir}/src/hdl/uart/synth/uart.vhd"] \
[file normalize "${origin_dir}/src/hdl/self_test/gnss_uart_test.vhd"] \
[file normalize "${origin_dir}/src/hdl/altera_inst/lpm_cnt_inst.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/smpl_cnt/synth/iq_smpl_cnt.vhd"] \
[file normalize "${origin_dir}/src/hdl/misc/led_ctrl_golden.vhd"] \
[file normalize "${origin_dir}/src/hdl/litepcie/litepcie_pkg.vhd"] \
[file normalize "${origin_dir}/src/hdl/litepcie/litepcie_top.vhd"] \
[file normalize "${origin_dir}/src/hdl/altera_inst/lms7002_ddin.vhd"] \
[file normalize "${origin_dir}/src/hdl/altera_inst/lms7002_ddout.vhd"] \
[file normalize "${origin_dir}/src/hdl/general/sync_reg.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/diq2fifo/synth/rxiq_siso_sdr.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/diq2fifo/synth/rxiq_siso_ddr.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/diq2fifo/synth/rxiq_siso.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/diq2fifo/synth/rxiq_mimo_ddr.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/diq2fifo/synth/rxiq_pulse_ddr.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/diq2fifo/synth/rxiq_mimo.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/diq2fifo/synth/rxiq.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/diq2fifo/synth/test_data_dd.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/smpl_cmp/synth/smpl_cmp.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/diq2fifo/synth/diq2fifo.vhd"] \
[file normalize "${origin_dir}/src/hdl/tx_path_top/fifo2diq/synth/txiq.vhd"] \
[file normalize "${origin_dir}/src/hdl/tx_path_top/fifo2diq/synth/txiq_ctrl.vhd"] \
[file normalize "${origin_dir}/src/hdl/tx_path_top/fifo2diq/synth/fifo2diq.vhd"] \
[file normalize "${origin_dir}/src/hdl/txiqmux/synth/txiq_tst_ptrn.vhd"] \
[file normalize "${origin_dir}/src/hdl/txiqmux/synth/txiqmux.vhd"] \
[file normalize "${origin_dir}/src/hdl/lms7002/synth/lms7002_tx.vhd"] \
[file normalize "${origin_dir}/src/hdl/lms7002/lms7002_top.vhd"] \
[file normalize "${origin_dir}/src/hdl/tx_path_top/pct_separate/synth/pct_separate_fsm.vhd"] \
[file normalize "${origin_dir}/src/hdl/tx_path_top/pct_separate/synth/one_pct_fifo.vhd"] \
[file normalize "${origin_dir}/src/hdl/altera_inst/lpm_compare_inst.vhd"] \
[file normalize "${origin_dir}/src/hdl/tx_path_top/packets2data/synth/p2d_rd.vhd"] \
[file normalize "${origin_dir}/src/hdl/tx_path_top/packets2data/synth/p2d_wr_fsm.vhd"] \
[file normalize "${origin_dir}/src/hdl/tx_path_top/packets2data/synth/packets2data.vhd"] \
[file normalize "${origin_dir}/src/hdl/wfm_ram_buffer/pct_payload_extrct.vhd"] \
[file normalize "${origin_dir}/src/hdl/pcie/wr_stream_buff.vhd"] \
[file normalize "${origin_dir}/src/hdl/general/shift_reg.vhd"] \
[file normalize "${origin_dir}/src/hdl/pcie/wr_control_buff.vhd"] \
[file normalize "${origin_dir}/src/hdl/pcie/rd_stream_buff.vhd"] \
[file normalize "${origin_dir}/src/hdl/resize_fifoword/resize_fifoword.vhd"] \
[file normalize "${origin_dir}/src/hdl/pcie/rd_control_buff.vhd"] \
[file normalize "${origin_dir}/src/hdl/pcie/pcie_top.vhd"] \
[file normalize "${origin_dir}/src/hdl/packages/pll_top_blackbox_pkg.vhd"] \
[file normalize "${origin_dir}/src/hdl/tx_path_top/pulse_gen/synth/pulse_gen.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/smpl_cnt/synth/smpl_cnt.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_path_top/rx_path/synth/rx_path_top.vhd"] \
[file normalize "${origin_dir}/src/hdl/self_test/singl_clk_with_ref_test.vhd"] \
[file normalize "${origin_dir}/src/hdl/tx_path_top/tx_path/synth/sync_fifo_rw.vhd"] \
[file normalize "${origin_dir}/src/hdl/misc/tdd_control.vhd"] \
[file normalize "${origin_dir}/src/hdl/self_test/tst_top.vhd"] \
[file normalize "${origin_dir}/src/hdl/tx_path_top/bit_unpack/synth/unpack_128_to_48.vhd"] \
[file normalize "${origin_dir}/src/hdl/tx_path_top/packets2data/synth/packets2data_top.vhd"] \
[file normalize "${origin_dir}/src/hdl/tx_path_top/tx_path/synth/tx_path_top.vhd"] \
[file normalize "${origin_dir}/src/hdl/tx_pll_top/synth/tx_pll_top.vhd"] \
[file normalize "${origin_dir}/src/hdl/cpu/cpu_top.vhd"] \
[file normalize "${origin_dir}/src/hdl/rx_pll_top/synth/rx_pll_top.vhd"] \
[file normalize "${origin_dir}/src/hdl/pll_top/pll_top.vhd"] \
[file normalize "${origin_dir}/src/hdl/rxtx_top/synth/rxtx_top.vhd"] \
[file normalize "${origin_dir}/src/hdl/top/LimeSDR_XTRX_top.vhd"] \
[file normalize "${origin_dir}/ip/litex_pcie_phy/pcie_pipe_clock.v"] \
[file normalize "${origin_dir}/ip/litex_pcie_phy/pcie_s7_support.v"] \
[file normalize "${origin_dir}/src/mb_elf/cpu.elf"] \
]
add_files -norecurse -fileset $obj $files
# Set 'sources_1' fileset file properties for remote files
set file "$origin_dir/ip/rx_pll/rx_pll/rx_pll.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "generate_synth_checkpoint" -value "1" -objects $file_obj
}
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
set_property -name "used_in_implementation" -value "1" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/ip/tx_pll/tx_pll/tx_pll.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "generate_synth_checkpoint" -value "1" -objects $file_obj
}
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
set_property -name "used_in_implementation" -value "1" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/ip/idelay_refclk_pll/idelay_refclk_pll/idelay_refclk_pll.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "generate_synth_checkpoint" -value "1" -objects $file_obj
}
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
set_property -name "used_in_implementation" -value "1" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/ip/pcie/pcie_s7/pcie_s7.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "generate_synth_checkpoint" -value "1" -objects $file_obj
}
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
set_property -name "used_in_implementation" -value "1" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/litepcie_gen/build/gateware/litepcie_core.v"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "Verilog" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
set_property -name "used_in_implementation" -value "1" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/packages/FIFO_PACK.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/packages/axi_pkg.vhdl"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/rx_path_top/bit_pack/synth/pack_48_to_64.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/rx_path_top/bit_pack/synth/pack_56_to_64.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/rx_path_top/bit_pack/synth/bit_pack.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/tx_path_top/bit_unpack/synth/unpack_64_to_48.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/tx_path_top/bit_unpack/synth/unpack_64_to_64.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/tx_path_top/bit_unpack/synth/bit_unpack_64.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/general/bus_sync_reg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/spi/fpgacfg_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/spi/pllcfg_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/spi/tstcfg_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/spi/periphcfg_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/spi/memcfg_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/spi/mem_package.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/revision/revisions_golden.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL 2008" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/spi/mcfg_components.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/spi/mcfg32wm_fsm.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/spi/fpgacfg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/spi/pllcfg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/spi/tstcfg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL 2008" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/spi/periphcfg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/spi/memcfg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL 2008" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/spi/cfg_top.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/self_test/clk_no_ref_test.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/self_test/clock_test.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/pll_reconfig_ctrl/config_ctrl.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/rx_path_top/data2packets/synth/data2packets.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/rx_path_top/data2packets/synth/data2packets128.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj
set file "$origin_dir/src/hdl/rx_path_top/data2packets/synth/data2packets_fsm.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj