checklist.md

UART Checklist

This checklist is for Hardware Stage transitions for the UART peripheral. All checklist items refer to the content in the Checklist.

Design Checklist

D1

Type	Item	Resolution	Note/Collaterals
Documentation	SPEC_COMPLETE	Done	UART Spec
Documentation	CSR_DEFINED	Done
RTL	CLKRST_CONNECTED	Done
RTL	IP_TOP	Done
RTL	IP_INSTANTIABLE	Done
RTL	PHYSICAL_MACROS_DEFINED_80	N/A
RTL	FUNC_IMPLEMENTED	Done
RTL	ASSERT_KNOWN_ADDED	Done
Code Quality	LINT_SETUP	Done

D1 Exceptions

PHYSICAL_MACROS_DEFINED_80 is waived as UART doesn't have memories inside.

D2

Type	Item	Resolution	Note/Collaterals
Documentation	NEW_FEATURES	N/A
Documentation	BLOCK_DIAGRAM	N/A
Documentation	DOC_INTERFACE	Done
Documentation	DOC_INTEGRATION_GUIDE	Waived	This checklist item has been added retrospectively.
Documentation	MISSING_FUNC	N/A
Documentation	FEATURE_FROZEN	Done
RTL	FEATURE_COMPLETE	Done
RTL	PORT_FROZEN	Done
RTL	ARCHITECTURE_FROZEN	Done
RTL	REVIEW_TODO	Done
RTL	STYLE_X	Done
RTL	CDC_SYNCMACRO	N/A
Code Quality	LINT_PASS	Done
Code Quality	CDC_SETUP	Waived	No block-level flow available - waived to top-level signoff.
Code Quality	RDC_SETUP	Waived	No block-level flow available - waived to top-level signoff.
Code Quality	AREA_CHECK	Done	Area check done (on FPGA)
Code Quality	TIMING_CHECK	Done	Fmax 50MHz on NexysVideo
Security	SEC_CM_DOCUMENTED	N/A

D2S

Type	Item	Resolution	Note/Collaterals
Security	SEC_CM_ASSETS_LISTED	Done
Security	SEC_CM_IMPLEMENTED	Done
Security	SEC_CM_RND_CNST	N/A
Security	SEC_CM_NON_RESET_FLOPS	N/A
Security	SEC_CM_SHADOW_REGS	N/A
Security	SEC_CM_RTL_REVIEWED	N/A
Security	SEC_CM_COUNCIL_REVIEWED	N/A	This block only contains the bus-integrity CM.

D3

Type	Item	Resolution	Note/Collaterals
Documentation	NEW_FEATURES_D3	N/A
RTL	TODO_COMPLETE	Done
Code Quality	LINT_COMPLETE	Done
Code Quality	CDC_COMPLETE	Waived	No block-level flow available - waived to top-level signoff
Code Quality	RDC_COMPLETE	Waived	No block-level flow available - waived to top-level signoff
Review	REVIEW_RTL	Done
Review	REVIEW_DELETED_FF	Waived	No block-level flow available - waived to top-level signoff
Review	REVIEW_SW_CHANGE	Done	by awill@
Review	REVIEW_SW_ERRATA	Done
Security	[SEC_NON_RESET_FLOPS][]	N/A
Security	[SEC_SHADOW_REGS][]	N/A
Review	Reviewer(s)	Done	eunchan@ jeoong@ weicai@ awill@
Review	Signoff date	Done	2022-06-16

Verification Checklist

V1

Type	Item	Resolution	Note/Collaterals
Documentation	DV_DOC_DRAFT_COMPLETED	Done	UART DV document
Documentation	TESTPLAN_COMPLETED	Done	UART Testplan
Testbench	TB_TOP_CREATED	Done
Testbench	PRELIMINARY_ASSERTION_CHECKS_ADDED	Done
Testbench	SIM_TB_ENV_CREATED	Done
Testbench	SIM_RAL_MODEL_GEN_AUTOMATED	Done
Testbench	CSR_CHECK_GEN_AUTOMATED	waived	Revisit later. Tool setup in progress.
Testbench	TB_GEN_AUTOMATED	N/A
Tests	SIM_SMOKE_TEST_PASSING	Done
Tests	SIM_CSR_MEM_TEST_SUITE_PASSING	Done
Tests	FPV_MAIN_ASSERTIONS_PROVEN	N/A
Tool Setup	SIM_ALT_TOOL_SETUP	Done
Regression	SIM_SMOKE_REGRESSION_SETUP	Done	Exception (implemented in local)
Regression	SIM_NIGHTLY_REGRESSION_SETUP	Done	Exception (implemented in local)
Regression	FPV_REGRESSION_SETUP	N/A
Coverage	SIM_COVERAGE_MODEL_ADDED	Done
Code Quality	TB_LINT_SETUP	Done
Integration	PRE_VERIFIED_SUB_MODULES_V1	N/A	Except for IP module
Review	DESIGN_SPEC_REVIEWED	Done
Review	TESTPLAN_REVIEWED	Done
Review	STD_TEST_CATEGORIES_PLANNED	Done	Exception (Security, Power, Debug)
Review	V2_CHECKLIST_SCOPED	Done

V2

Type	Item	Resolution	Note/Collaterals
Documentation	DESIGN_DELTAS_CAPTURED_V2	N/A
Documentation	DV_DOC_COMPLETED	Done
Testbench	FUNCTIONAL_COVERAGE_IMPLEMENTED	Not Started
Testbench	ALL_INTERFACES_EXERCISED	Done
Testbench	ALL_ASSERTION_CHECKS_ADDED	Done
Testbench	SIM_TB_ENV_COMPLETED	Done
Tests	SIM_ALL_TESTS_PASSING	Done
Tests	FPV_ALL_ASSERTIONS_WRITTEN	N/A
Tests	FPV_ALL_ASSUMPTIONS_REVIEWED	N/A
Tests	SIM_FW_SIMULATED	N/A
Regression	SIM_NIGHTLY_REGRESSION_V2	Done
Coverage	SIM_CODE_COVERAGE_V2	Done
Coverage	SIM_FUNCTIONAL_COVERAGE_V2	Done
Coverage	FPV_CODE_COVERAGE_V2	N/A
Coverage	FPV_COI_COVERAGE_V2	N/A
Issues	NO_HIGH_PRIORITY_ISSUES_PENDING	Done
Issues	ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED	Done
Integration	PRE_VERIFIED_SUB_MODULES_V2	N/A
Review	DV_DOC_TESTPLAN_REVIEWED	Not Started
Review	V3_CHECKLIST_SCOPED	Done

V2S

Type	Item	Resolution	Note/Collaterals
Documentation	SEC_CM_TESTPLAN_COMPLETED	Done
Tests	FPV_SEC_CM_VERIFIED	N/A
Tests	SIM_SEC_CM_VERIFIED	Done
Coverage	SIM_COVERAGE_REVIEWED	Done
Review	SEC_CM_DV_REVIEWED	Done	Waived the V2S review meeting, since only 1 standard sec_cm - bus integrity.

V3

Type	Item	Resolution	Note/Collaterals
Documentation	DESIGN_DELTAS_CAPTURED_V3	N/A
Tests	X_PROP_ANALYSIS_COMPLETED	Waived	Revisit later. Tool setup in progress
Tests	FPV_ASSERTIONS_PROVEN_AT_V3	N/A
Regression	SIM_NIGHTLY_REGRESSION_AT_V3	Done
Coverage	SIM_CODE_COVERAGE_AT_100	Done	common_cov_excl.cfg, uart_cov_excl.el
Coverage	SIM_FUNCTIONAL_COVERAGE_AT_100	Done
Coverage	FPV_CODE_COVERAGE_AT_100	N/A
Coverage	FPV_COI_COVERAGE_AT_100	N/A
Code Quality	ALL_TODOS_RESOLVED	Done
Code Quality	NO_TOOL_WARNINGS_THROWN	Done
Code Quality	TB_LINT_COMPLETE	Not Started
Integration	PRE_VERIFIED_SUB_MODULES_V3	N/A
Issues	NO_ISSUES_PENDING	Done
Review	Reviewer(s)	Done	@eunchan @sjgitty @sriyerg
Review	Signoff date	Done	2019-11-01