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dinoeggs.asm
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dinoeggs.asm
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// project created by mikroman
// June 18,2024
// [ ][$][0-z][0-z][0-z]
.import source "dino_labels.asm"
#define no_error // comment this line for read_error build
//#define read_error // uncomment this line for read_error build
#if read_error
BasicUpstart2(error) // SYS2064 ($0810)
#elif no_error
BasicUpstart2(start) // SYS2178 ($0882)
#endif
* = $0810 "read_error"
error:
jmp L_JMP_0819_0810 // Do Read Error check/continue or reset
L_JSR_0813_50AD:
L_JSR_0813_5422:
jmp L_JMP_1BB2_0813 //
L_JSR_0816_341D:
L_JSR_0816_3441:
L_JSR_0816_346E:
L_JSR_0816_349E:
jmp L_JMP_7C38_0816 //
L_JMP_0819_0810: // Disk protection check
jsr CLALL // Close All Channels And Files
lda #$00
jsr SETNAM // Set Filename
lda #$0F
ldx #$08
ldy #$0F
jsr SETLFS // Set Logical File Parameters
jsr OPEN // Open Channel
lda #$01
ldx #$96
ldy #$1D
jsr SETNAM // Set Filename
lda #$05
ldx #$08
ldy #$05
jsr SETLFS // Set Logical File Parameters
jsr OPEN // Open Vector
ldx #$0F
jsr CHKOUT // Set Output
ldx #$00
L_BRS_0849_0852: // perform Block Read (U1) of T,S = 18,18 to look for a checksum error
lda BlockRead,X // get a byte from U1 command string
jsr CHROUT // Output Vector, chrout
inx
cpx #$0C
bne L_BRS_0849_0852
jsr CLRCHN // Restore I/O Vector
ldx #$0F
jsr CHKIN // Set Input
ldx #$00
jsr CHRIN // Input Vector, chrin
cmp #$32
bne L_BRS_086C_0863
jsr CHRIN // Input Vector, chrin
cmp #$33
beq L_BRS_0870_086A
L_BRS_086C_0863:
sei
jmp (RESET_vector)
L_BRS_0870_086A:
ldx #$14
L_BRS_0872_0876:
jsr CHRIN // Input Vector, chrin
dex
bne L_BRS_0872_0876
lda #$05
jsr CLOSE // Close Vector
lda #$0F
jsr CLOSE // Close Vector
start: // 10 SYS2178 entry: skip disk error check
sei
ldx #$1E
L_BRS_0885_088C: // prep VIC $D010-D01E
lda table_6060,X
sta MSIGX,X // Sprites 0-7 MSB of X coordinate
dex
bpl L_BRS_0885_088C
ldx #$0F
L_BRS_0890_089D: // prep CIA1 and CIA2
lda table_60C2,X
sta D1PRA,X // Data Port A (Keyboard, Joystick, Paddles)
lda table_60D2,X
sta D2PRA,X // Data Port A (Serial Bus, RS232, VIC Base Mem.)
dex
bpl L_BRS_0890_089D
lda #$00
ldx #$20
ldy #$86
jsr L_JSR_660C_08A5
lda #$BA
sta NMI_vector // Vector: NMI
lda #$1C
sta NMI_vector + 1
lda #$95
sta D2PRA // Data Port A (Serial Bus, RS232, VIC Base Mem.)
sta $0203
lda #$19
sta $01
ldx #$00
L_BRS_08C0_08D5:
lda SP0X,X // Sprite 0 X Pos
sta $CE00,X
lda $D100,X
sta $CF00,X
lda #$00
sta $0400,X
sta FRELO1,X // Voice 1: Frequency Control - Low-Byte
inx
bne L_BRS_08C0_08D5
dec $0400
ldx #$07
L_BRS_08DC_08E9:
lda table_1C92,X
sta $CFE0,X
lda table_1C9A,X
sta $CFF0,X
dex
bpl L_BRS_08DC_08E9
lda #$0F
sta SIGVOL // Select Filter Mode and Volume
lda #$08
sta VCREG1 // Voice 1: Control Register
lda #$1D
sta $01
ldx #$02
lda #$00
L_BRS_08FD_0900:
sta $00,X
inx
bne L_BRS_08FD_0900
jsr L_JSR_6124_0902
lda #$C0
sta $E0
lda #$FE
sta $E2
ldx #$BC
stx $E1
inx
stx $E3
ldy #$00
L_BRS_0916_093C:
sty $EF
ldx table_627B,Y
ldy #$02
L_BRS_091D_092B:
lda table_625F,X
sta ($E0),Y
lda table_625F + 1,X
sta ($E2),Y
iny
inx
cpy #$08
bne L_BRS_091D_092B
ldy #$01
jsr L_JSR_61C2_092F
ldx #$02
jsr L_JSR_61DE_0934
ldy $EF
iny
cpy #$28
bne L_BRS_0916_093C
ldx #$00
L_BRS_0940_0953:
lda $BCC0,X
sta $FCC0,X
lda $BDC0,X
sta $FDC0,X
lda $BEC0,X
sta $FEC0,X
inx
bne L_BRS_0940_0953
dex
stx $DE
lda #$6C
sta v_1D95
L_JMP_095D_1204:
lda #$7F
sta IRQ_vector // Vector: IRQ
lda #$60
sta IRQ_vector + 1
lda #$85
sta LOOP_632A
L_JMP_096C_10B3:
L_JMP_096C_18AE:
lda #$00
ldx #$F8
txs
ldx #$03
stx $1E
bit $DE
bmi L_BRS_097E_0977
L_BRS_0979_097C:
sta $D0,X
dex
bpl L_BRS_0979_097C
L_BRS_097E_0977:
lda #$00
ldx #$FF
stx $CF
jsr L_JSR_656A_0984
ldx #$1C
bit $DE
bpl L_BRS_098E_098B
inx
L_BRS_098E_098B:
cli
jsr L_JSR_3200_098F
lda #$03
sta SPMC // Sprites Multi-Color Mode Select
lda #$06
sta SP0COL // Sprite 0 Color
sta SP1COL // Sprite 1 Color
lda #$FF
sta SPENA // Sprite display Enable
L_JMP_09A4_1738:
lda $20
and #$01
tax
lda table_67A7,X
sta $29
ldy #$27
sty $EF
bit $29
bvc L_BRS_09B8_09B4
ldy #$4F
L_BRS_09B8_09B4:
L_BRS_09B8_09E7:
lda $0410,Y
beq L_BRS_09E4_09BB
sec
sbc #$01
sta $0410,Y
sty $EE
lda $0460,Y
ldx $0370,Y
bmi L_BRS_09E4_09CB
jsr L_JSR_6E5C_09CD
lda $E0
ldy $E1
jsr L_JSR_665F_09D4
ldy #$17
lda #$00
L_BRS_09DB_09E0:
sta ($E0),Y
sta ($E2),Y
dey
bpl L_BRS_09DB_09E0
ldy $EE
L_BRS_09E4_09BB:
L_BRS_09E4_09CB:
dey
dec $EF
bpl L_BRS_09B8_09E7
ldx #$03
L_JMP_09EB_0A80:
lda $BFF8,X
bne L_BRS_09F3_09EE
jmp L_JMP_0A7D_09F0
L_BRS_09F3_09EE:
dec $BFF8,X
stx $EF
lda $BFFC,X
tax
dex
lda table_7CCD,X
beq L_BRS_0A1F_0A00
ldy table_7CCC,X
beq L_BRS_0A1F_0A05
ldy $09
ora table_1C6A,Y
tay
ldx #$05
lda $05
beq L_BRS_0A14_0A11
inx
L_BRS_0A14_0A11:
L_BRS_0A14_0A1B:
lda #$04
sta $0580,Y
iny
dex
bne L_BRS_0A14_0A1B
beq L_BRS_0A7B_0A1D
L_BRS_0A1F_0A00:
L_BRS_0A1F_0A05:
lda $09
jsr L_JSR_6E5A_0A21
ldx #$00
jsr L_JSR_6762_0A26
ldy $EF
ldx $BFFC,Y
ldy #$5F
lda $05
beq L_BRS_0A36_0A32
ldy #$7F
L_BRS_0A36_0A32:
cpx #$04
bcs L_BRS_0A74_0A38
lda $E0
sta $0A49
lda $E1
and #$1F
ora #$28
sta $0A4A
L_BRS_0A48_0A4E:
lda $F000,Y
sta ($E0),Y
dey
bpl L_BRS_0A48_0A4E
lda $0C
bpl L_BRS_0A71_0A52
lda table_1C86,X
clc
adc $CE
tay
lda table_6EB9,Y
jsr L_JSR_1C4D_0A5E
lda $E5
and #$1F
ora #$D8
sta $E5
ldy $CE
lda table_6ED7,Y
jsr L_JSR_1C4D_0A6E
L_BRS_0A71_0A52:
jmp L_JMP_0A7B_0A71
L_BRS_0A74_0A38:
lda #$00
L_BRS_0A76_0A79:
sta ($E0),Y
dey
bpl L_BRS_0A76_0A79
L_BRS_0A7B_0A1D:
L_JMP_0A7B_0A71:
ldx $EF
L_JMP_0A7D_09F0:
dex
bmi L_BRS_0A83_0A7E
jmp L_JMP_09EB_0A80
L_BRS_0A83_0A7E:
jsr L_JSR_692D_0A83
lda $05
beq L_BRS_0AC7_0A88
sec
ror $0C
lda #$0C
sta $09
lda $04
sec
sbc #$44
bcc L_BRS_0AAE_0A96
lsr
lsr
lsr
tax
inx
ldy #$03
L_BRS_0A9F_0AAC:
txa
sta $BFFC,Y
lda #$02
sta $BFF8,Y
dey
bmi L_BRS_0AAE_0AA9
dex
bne L_BRS_0A9F_0AAC
L_BRS_0AAE_0A96:
L_BRS_0AAE_0AA9:
jsr L_JSR_31FA_0AAE
lda $05
bne L_BRS_0ABB_0AB3
txa
bmi L_BRS_0ABB_0AB6
jmp L_JMP_1204_0AB8
L_BRS_0ABB_0AB3:
L_BRS_0ABB_0AB6:
lda #$40
sta $0204
lda #$10
sta $D5
jmp L_JMP_0FE8_0AC4
L_BRS_0AC7_0A88:
bit $DE
bpl L_BRS_0AE0_0AC9
bvc L_BRS_0ADB_0ACB
lda $20
cmp #$E0
bcs L_BRS_0ADB_0AD1
lda #$30
sta $21
lda #$E0
sta $20
L_BRS_0ADB_0ACB:
L_BRS_0ADB_0AD1:
lda #$60
sta LOOP_632A
L_BRS_0AE0_0AC9:
ldx #$04
L_BRS_0AE2_0AEE:
lda $4E,X
bne L_BRS_0AF3_0AE4
sta $72,X
sta $78,X
sta $71,X
L_JMP_0AEC_0BBC:
L_JMP_0AEC_0DB5:
dex
dex
bpl L_BRS_0AE2_0AEE
jmp L_JMP_0DB8_0AF0
L_BRS_0AF3_0AE4:
stx $EE
lda $4F,X
beq L_BRS_0B6F_0AF7
bmi L_BRS_0B2B_0AF9
lda #$00
sta $72,X
jsr L_JSR_71FE_0AFF
pha
lda $4E,X
lsr
lsr
lsr
tax
inx
inx
pla
jsr L_JSR_6E5C_0B0C
ldx $EE
lda $4F,X
ldx #$17
cmp #$38
bcs L_BRS_0B1B_0B17
ldx #$2F
L_BRS_0B1B_0B17:
ldy #$17
L_BRS_0B1D_0B26:
lda ($E0),Y
and $9F70,X
sta ($E0),Y
dex
dey
bpl L_BRS_0B1D_0B26
jmp L_JMP_0CA3_0B28
L_BRS_0B2B_0AF9:
cmp #$C0
bcs L_BRS_0B60_0B2D
lda $77,X
and #$FC
clc
adc #$0D
asl
sta $48,X
lda #$00
rol
sta $49,X
dec $4F,X
bmi L_BRS_0B6C_0B40
lda #$00
sta FREHI1 // Voice 1: Frequency Control - High-Byte
sta VCREG1 // Voice 1: Control Register
ldy $02D7
inc $02D7
lda table_7CCA,Y
pha
jsr L_JSR_722D_0B54
dey
tax
pla
jsr L_JSR_71D6_0B5A
jmp L_JMP_0B6C_0B5D
L_BRS_0B60_0B2D:
inc $4F,X
bne L_BRS_0B6C_0B62
jsr L_JSR_722D_0B64
ldx #$01
jsr L_JSR_717B_0B69
L_BRS_0B6C_0B40:
L_JMP_0B6C_0B5D:
L_BRS_0B6C_0B62:
jmp L_JMP_0CA3_0B6C
L_BRS_0B6F_0AF7:
lda $72,X
beq L_BRS_0BCA_0B71
cmp #$04
bcc L_BRS_0B96_0B75
jsr L_JSR_6200_0B77
and #$07
beq L_BRS_0B85_0B7C
lda #$00
sta $72,X
jmp L_JMP_0C3A_0B82
L_BRS_0B85_0B7C:
jsr L_JSR_71FE_0B85
ldy #$00
cmp $72,X
bcc L_BRS_0B8F_0B8C
iny
L_BRS_0B8F_0B8C:
lda #$00
sta $72,X
jmp L_JMP_0C26_0B93
L_BRS_0B96_0B75:
jsr L_JSR_7CF1_0B96
inc $4E,X
inc $5B,X
ldy $4E,X
cpy #$B3
bcc L_BRS_0BBF_0BA1
jsr L_JSR_722D_0BA3
dey
dey
tax
lda #$90
jsr L_JSR_71D6_0BAB
ldx $EE
ldy $72,X
dey
cpy #$03
bcs L_BRS_0BBC_0BB5
lda #$01
sta $00A7,Y
L_BRS_0BBC_0BB5:
jmp L_JMP_0AEC_0BBC
L_BRS_0BBF_0BA1:
lda $5A,X
and #$0F
sta $EA
jsr L_JSR_4FFD_0BC5
sta $5A,X
L_BRS_0BCA_0B71:
lda $5B,X
beq L_BRS_0BD8_0BCC
dec $5B,X
lda $55,X
ora #$80
sta $55,X
bmi L_BRS_0C50_0BD6
L_BRS_0BD8_0BCC:
lda $71,X
beq L_BRS_0C01_0BDA
lda $77,X
and #$FC
sta $E1
jsr L_JSR_71FE_0BE2
sec
sbc $E1
clc
adc #$20
ldy $54,X
cmp table_7CB6,Y
bcs L_BRS_0BFA_0BF0
cmp table_7CB9,Y
bcs L_BRS_0C3A_0BF5
lda #$00
.byte $2C
L_BRS_0BFA_0BF0:
lda #$01
sta $55,X
jmp L_JMP_0C50_0BFE
L_BRS_0C01_0BDA:
lda $13
ora $02
ora $DE
bne L_BRS_0C3A_0C07
lda $D5
ora $D4
beq L_BRS_0C3A_0C0D
lda $2A
bne L_BRS_0C33_0C11
lda $16
ldy $5A,X
jsr L_JSR_7208_0C17
beq L_BRS_0C3A_0C1A
ldy #$00
jsr L_JSR_71FE_0C1E
cmp $15
bcc L_BRS_0C26_0C23
iny
L_JMP_0C26_0B93:
L_BRS_0C26_0C23:
lda $55,X
and #$7F
sta $E0
tya
cmp $E0
sta $55,X
beq L_BRS_0C50_0C31
L_BRS_0C33_0C11:
lda #$05
sta $5B,X
jmp L_JMP_0C50_0C37
L_JMP_0C3A_0B82:
L_BRS_0C3A_0BF5:
L_BRS_0C3A_0C07:
L_BRS_0C3A_0C0D:
L_BRS_0C3A_0C1A:
jsr L_JSR_6200_0C3A
cmp #$F0
bcc L_BRS_0C50_0C3F
tay
lda $55,X
eor #$80
bmi L_BRS_0C4E_0C46
cpy #$F8
bcc L_BRS_0C4E_0C4A
eor #$81
L_BRS_0C4E_0C46:
L_BRS_0C4E_0C4A:
sta $55,X
L_BRS_0C50_0BD6:
L_JMP_0C50_0BFE:
L_BRS_0C50_0C31:
L_JMP_0C50_0C37:
L_BRS_0C50_0C3F:
L_JMP_0C50_1BA8:
lda #$01
ldy $55,X
beq L_BRS_0C5C_0C54
bmi L_BRS_0C7D_0C56
ldy #$FF
lda #$FF
L_BRS_0C5C_0C54:
clc
adc $48,X
sta $48,X
tya
adc $49,X
sta $49,X
lda $48,X
cmp #$18
bne L_BRS_0C70_0C6A
lda $49,X
beq L_BRS_0C7A_0C6E
L_BRS_0C70_0C6A:
lda $48,X
cmp #$4A
bne L_BRS_0C7D_0C74
lda $49,X
beq L_BRS_0C7D_0C78
L_BRS_0C7A_0C6E:
jmp L_JMP_1BA2_0C7A
L_BRS_0C7D_0C56:
L_BRS_0C7D_0C74:
L_BRS_0C7D_0C78:
lda $71,X
bne L_BRS_0CA3_0C7F
ldy $54,X
lda table_7CBF,Y
pha
lda $4E,X
pha
jsr L_JSR_71FE_0C8A
sec
sbc table_7CBC,Y
tax
pla
clc
adc #$08
tay
pla
jsr L_JSR_1BB2_0C98
beq L_BRS_0CA3_0C9B
ldx $EE
lda #$E8
sta $4F,X
L_JMP_0CA3_0B28:
L_JMP_0CA3_0B6C:
L_BRS_0CA3_0C7F:
L_BRS_0CA3_0C9B:
ldx $EE
jsr L_JSR_71FE_0CA5
clc
adc #$06
ldy #$FF
sec
L_BRS_0CAE_0CB1:
sbc #$0C
iny
bcs L_BRS_0CAE_0CB1
sty $EF
lda $5A,X
and #$F0
ora $EF
sta $5A,X
tay
lda $72,X
bne L_BRS_0CCC_0CC0
lda $0510,Y
and #$03
bne L_BRS_0CCC_0CC7
jmp L_JMP_1BA2_0CC9
L_BRS_0CCC_0CC0:
L_BRS_0CCC_0CC7:
lda $4F,X
bne L_BRS_0CDC_0CCE
tya
jsr L_JSR_6E38_0CD1
bne L_BRS_0CDC_0CD4
ldx $EE
lda #$E8
sta $4F,X
L_BRS_0CDC_0CCE:
L_BRS_0CDC_0CD4:
ldx $EE
lda $4F,X
beq L_BRS_0D1F_0CE0
bpl L_BRS_0CF4_0CE2
cmp #$87
bcs L_BRS_0D1F_0CE6
and #$7F
pha
jsr L_JSR_1D7D_0CEB
pla
clc
adc #$24
bne L_BRS_0D4D_0CF2
L_BRS_0CF4_0CE2:
ldy $5A,X
lda #$04
sta $0590,Y
lda $4F,X
dec $4F,X
bne L_BRS_0D17_0CFF
lda $0510,Y
and #$3C
beq L_BRS_0D15_0D06
cmp #$10
bcs L_BRS_0D15_0D0A
lda $0510,Y
sec
sbc #$04
sta $0510,Y
L_BRS_0D15_0D06:
L_BRS_0D15_0D0A:
lda #$01
L_BRS_0D17_0CFF:
lsr
lsr
lsr
clc
adc #$2B
bne L_BRS_0D4D_0D1D
L_BRS_0D1F_0CE0:
L_BRS_0D1F_0CE6:
lda $54,X
asl
asl
ldy $55,X
beq L_BRS_0D43_0D25
bpl L_BRS_0D41_0D27
asl
cpy #$80
beq L_BRS_0D30_0D2C
ora #$04
L_BRS_0D30_0D2C:
tay
lda $20
lsr
lsr
and #$03
sta $E0
tya
ora $E0
clc
adc #$0C
bcc L_BRS_0D4D_0D3F
L_BRS_0D41_0D27:
ora #$02
L_BRS_0D43_0D25:
tay
lda $20
lsr
and #$01
beq L_BRS_0D4C_0D49
iny
L_BRS_0D4C_0D49:
tya
L_BRS_0D4D_0CF2:
L_BRS_0D4D_0D1D:
L_BRS_0D4D_0D3F:
asl
tay
lda table_68C1,Y
pha
lda table_68C1 + 1,Y
ldy table_6927,X
sta MOON,Y
pla
sta MOON-1,Y
lda #$1F
sta $E0
lda $55,X
and #$80
ora $72,X
ora $4F,X
beq L_BRS_0D70_0D6C
lsr $E0
L_BRS_0D70_0D6C:
jsr L_JSR_6200_0D70
and #$03
ora $20
and $E0
ora $71,X
bne L_BRS_0DB5_0D7B
stx $EF
jsr L_JSR_6200_0D7F
and #$0F
sta $E0
jsr L_JSR_6200_0D86
and #$1F
ora #$E0
sta $E1
lda #$11
sta VCREG1 // Voice 1: Control Register
L_BRS_0D94_0DAC:
lda $E1
sta FREHI1 // Voice 1: Frequency Control - High-Byte
lda #$00
sta ATDCY1 // Voice 1: Attack / Decay Cycle Control
lda #$E0
sta SUREL1 // Voice 1: Sustain / Release Cycle Control