diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.cproject b/tutorial01-stm32-pio-01/pio-01-02_olivia/.cproject
new file mode 100644
index 0000000..c2acbda
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.cproject
@@ -0,0 +1,182 @@
+
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\ No newline at end of file
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.gitignore b/tutorial01-stm32-pio-01/pio-01-02_olivia/.gitignore
new file mode 100644
index 0000000..36df4e6
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.gitignore
@@ -0,0 +1,8 @@
+# Ignore all .log files
+*.log
+
+# Ignore the build directory
+build/
+
+# Ignore files in the temp directory
+temp/*
\ No newline at end of file
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.gitmodules b/tutorial01-stm32-pio-01/pio-01-02_olivia/.gitmodules
new file mode 100644
index 0000000..aaa2390
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.gitmodules
@@ -0,0 +1,6 @@
+[submodule "ThirdParty/FreeRTOS-Kernel-Partner-Supported-Ports"]
+ path = portable/ThirdParty/Partner-Supported-Ports
+ url = https://github.com/FreeRTOS/FreeRTOS-Kernel-Partner-Supported-Ports
+[submodule "ThirdParty/FreeRTOS-Kernel-Community-Supported-Ports"]
+ path = portable/ThirdParty/Community-Supported-Ports
+ url = https://github.com/FreeRTOS/FreeRTOS-Kernel-Community-Supported-Ports
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.lock b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.lock
new file mode 100644
index 0000000..e69de29
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.log4j.xml b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.log4j.xml
new file mode 100644
index 0000000..5e79a17
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.log4j.xml
@@ -0,0 +1,18 @@
+
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\ No newline at end of file
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/com.st.stm32cube.ide.mcu.informationcenter/2.1.500.202211100823 b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/com.st.stm32cube.ide.mcu.informationcenter/2.1.500.202211100823
new file mode 100644
index 0000000..e69de29
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.cdt.core/FreeRTOS_LED.1679135758468.pdom b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.cdt.core/FreeRTOS_LED.1679135758468.pdom
new file mode 100644
index 0000000..2ebb9db
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.cdt.core/FreeRTOS_LED.1679135758468.pdom differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.cdt.core/FreeRTOS_LED.language.settings.xml b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.cdt.core/FreeRTOS_LED.language.settings.xml
new file mode 100644
index 0000000..69004fd
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.cdt.core/FreeRTOS_LED.language.settings.xml
@@ -0,0 +1 @@
+
\ No newline at end of file
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c
@@ -0,0 +1 @@
+
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp
@@ -0,0 +1 @@
+
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.cdt.managedbuilder.core/spec.c b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.cdt.managedbuilder.core/spec.c
new file mode 100644
index 0000000..e69de29
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.cdt.managedbuilder.core/spec.cpp b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.cdt.managedbuilder.core/spec.cpp
new file mode 100644
index 0000000..e69de29
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/39/30e46b3185c5001d13d6fe58f0709e0f b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/39/30e46b3185c5001d13d6fe58f0709e0f
new file mode 100644
index 0000000..130d916
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/39/30e46b3185c5001d13d6fe58f0709e0f
@@ -0,0 +1,229 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+osThreadId defaultTaskHandle;
+osThreadId BlinkLEDHandle;
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+void StartDefaultTask(void const * argument);
+void StartTask02(void const * argument);
+void blinkaled(void);
+
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ /* MCU Configuration--------------------------------------------------------*/
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+ /* Configure the system clock */
+ SystemClock_Config();
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+
+ /* Create the thread(s) */
+ /* definition and creation of defaultTask */
+ osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 128);
+ defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
+
+ /* definition and creation of BlinkLED */
+ osThreadDef(blinkaled, StartTask02, osPriorityIdle, 0, 128);
+ BlinkLEDHandle = osThreadCreate(osThread(blinkaled), NULL);
+
+ /* Start scheduler */
+ osKernelStart();
+
+ /* We should never get here as control is now taken by the scheduler */
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ {
+ }
+ /* USER CODE END 3 */
+}
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16;
+ RCC_OscInitStruct.PLL.PLLN = 336;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+
+/**
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin : B1_Pin */
+ GPIO_InitStruct.Pin = B1_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
+
+ /*Configure GPIO pin : LD2_Pin */
+ GPIO_InitStruct.Pin = LD2_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+
+/* USER CODE BEGIN Header_StartDefaultTask */
+/**
+ * @brief Function implementing the defaultTask thread.
+ * @param argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void const * argument)
+{
+ /* USER CODE BEGIN 5 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END 5 */
+}
+
+/* USER CODE BEGIN Header_StartTask02 */
+/**
+* @brief Function implementing the blinkaled thread.
+* @param argument: Not used
+* @retval None
+*/
+/* USER CODE END Header_StartTask02 */
+void StartTask02(void const * argument)
+{
+ /* USER CODE BEGIN StartTask02 */
+ /* Infinite loop */
+ for(;;)
+ {
+ blinkaled();
+ }
+ /* USER CODE END StartTask02 */
+}
+
+/*
+ * Function: blinkled
+ * Blinks an LED connected to GPIOA Pin 5 by setting it high for 1 second and then low for 1 second.
+ * Parameters: None
+ * Returns: None
+ */
+void blinkaled(void)
+{
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET);
+ HAL_Delay(1000);
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET);
+ HAL_Delay(1000);
+}
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/3e/e05e38db7ac5001d13d6fe58f0709e0f b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/3e/e05e38db7ac5001d13d6fe58f0709e0f
new file mode 100644
index 0000000..1a527d4
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/3e/e05e38db7ac5001d13d6fe58f0709e0f
@@ -0,0 +1,4 @@
+635E684B79701B039C64EA45C3F84D30=2B8A1A14D46119CD49E4AAC54D250F3F
+66BE74F758C12D739921AEA421D593D3=1
+DC22A860405A8BF2F2C095E5B6529F12=F90B087FDAEC68C8F01B9C0344FA7B26
+eclipse.preferences.version=1
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/48/c0c0109d80c5001d13d6fe58f0709e0f b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/48/c0c0109d80c5001d13d6fe58f0709e0f
new file mode 100644
index 0000000..2d72519
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/48/c0c0109d80c5001d13d6fe58f0709e0f
@@ -0,0 +1,226 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+
+osThreadId defaultTaskHandle;
+osThreadId BlinkLEDHandle;
+
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+void StartDefaultTask(void const * argument);
+void StartTask02(void const * argument);
+void blinkaled(void);
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ /* MCU Configuration--------------------------------------------------------*/
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+ /* Configure the system clock */
+ SystemClock_Config();
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+
+ /* Create the thread(s) */
+ /* definition and creation of defaultTask */
+ osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 128);
+ defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
+
+ /* definition and creation of BlinkLED */
+ osThreadDef(blinkaled, StartTask02, osPriorityIdle, 0, 128);
+ BlinkLEDHandle = osThreadCreate(osThread(blinkaled), NULL);
+
+ /* Start scheduler */
+ osKernelStart();
+
+ /* We should never get here as control is now taken by the scheduler */
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ {
+ /* USER CODE END WHILE */
+
+ /* USER CODE BEGIN 3 */
+ }
+ /* USER CODE END 3 */
+}
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16;
+ RCC_OscInitStruct.PLL.PLLN = 336;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+
+/**
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin : B1_Pin */
+ GPIO_InitStruct.Pin = B1_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
+
+ /*Configure GPIO pin : LD2_Pin */
+ GPIO_InitStruct.Pin = LD2_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+
+/* USER CODE BEGIN Header_StartDefaultTask */
+/**
+ * @brief Function implementing the defaultTask thread.
+ * @param argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void const * argument)
+{
+ /* USER CODE BEGIN 5 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END 5 */
+}
+
+/* USER CODE BEGIN Header_StartTask02 */
+/**
+* @brief Function implementing the blinkaled thread.
+* @param argument: Not used
+* @retval None
+*/
+/* USER CODE END Header_StartTask02 */
+void StartTask02(void const * argument)
+{
+ /* USER CODE BEGIN StartTask02 */
+ /* Infinite loop */
+ for(;;)
+ {
+ blinkaled();
+ }
+ /* USER CODE END StartTask02 */
+}
+
+void blinkaled(void)
+{
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET);
+ HAL_Delay(1000);
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET);
+ HAL_Delay(1000);
+}
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/52/80848b7d7ec5001d13d6fe58f0709e0f b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/52/80848b7d7ec5001d13d6fe58f0709e0f
new file mode 100644
index 0000000..ead6c3e
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/52/80848b7d7ec5001d13d6fe58f0709e0f
@@ -0,0 +1,226 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+
+osThreadId defaultTaskHandle;
+osThreadId BlinkLEDHandle;
+
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+void StartDefaultTask(void const * argument);
+void StartTask02(void const * argument);
+
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ /* MCU Configuration--------------------------------------------------------*/
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+ /* Configure the system clock */
+ SystemClock_Config();
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+
+ /* Create the thread(s) */
+ /* definition and creation of defaultTask */
+ osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 128);
+ defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
+
+ /* definition and creation of BlinkLED */
+ osThreadDef(blinkaled, StartTask02, osPriorityIdle, 0, 128);
+ BlinkLEDHandle = osThreadCreate(osThread(blinkaled), NULL);
+
+ /* Start scheduler */
+ osKernelStart();
+
+ /* We should never get here as control is now taken by the scheduler */
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ {
+ /* USER CODE END WHILE */
+
+ /* USER CODE BEGIN 3 */
+ }
+ /* USER CODE END 3 */
+}
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16;
+ RCC_OscInitStruct.PLL.PLLN = 336;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+
+/**
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin : B1_Pin */
+ GPIO_InitStruct.Pin = B1_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
+
+ /*Configure GPIO pin : LD2_Pin */
+ GPIO_InitStruct.Pin = LD2_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+
+/* USER CODE BEGIN Header_StartDefaultTask */
+/**
+ * @brief Function implementing the defaultTask thread.
+ * @param argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void const * argument)
+{
+ /* USER CODE BEGIN 5 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END 5 */
+}
+
+/* USER CODE BEGIN Header_StartTask02 */
+/**
+* @brief Function implementing the BlinkLED thread.
+* @param argument: Not used
+* @retval None
+*/
+/* USER CODE END Header_StartTask02 */
+void StartTask02(void const * argument)
+{
+ /* USER CODE BEGIN StartTask02 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END StartTask02 */
+}
+
+void blinkaled(void)
+{
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET);
+ HAL_Delay(1000);
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET);
+ HAL_Delay(1000);
+}
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/52/a059856480c5001d13d6fe58f0709e0f b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/52/a059856480c5001d13d6fe58f0709e0f
new file mode 100644
index 0000000..d19980e
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/52/a059856480c5001d13d6fe58f0709e0f
@@ -0,0 +1,226 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+
+osThreadId defaultTaskHandle;
+osThreadId BlinkLEDHandle;
+
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+void StartDefaultTask(void const * argument);
+void StartTask02(void const * argument);
+void blinkaled(void);
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ /* MCU Configuration--------------------------------------------------------*/
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+ /* Configure the system clock */
+ SystemClock_Config();
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+
+ /* Create the thread(s) */
+ /* definition and creation of defaultTask */
+ osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 128);
+ defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
+
+ /* definition and creation of BlinkLED */
+ osThreadDef(blinkaled, StartTask02, osPriorityIdle, 0, 128);
+ BlinkLEDHandle = osThreadCreate(osThread(blinkaled), NULL);
+
+ /* Start scheduler */
+ osKernelStart();
+
+ /* We should never get here as control is now taken by the scheduler */
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ {
+ /* USER CODE END WHILE */
+
+ /* USER CODE BEGIN 3 */
+ }
+ /* USER CODE END 3 */
+}
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16;
+ RCC_OscInitStruct.PLL.PLLN = 336;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+
+/**
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin : B1_Pin */
+ GPIO_InitStruct.Pin = B1_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
+
+ /*Configure GPIO pin : LD2_Pin */
+ GPIO_InitStruct.Pin = LD2_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+
+/* USER CODE BEGIN Header_StartDefaultTask */
+/**
+ * @brief Function implementing the defaultTask thread.
+ * @param argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void const * argument)
+{
+ /* USER CODE BEGIN 5 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END 5 */
+}
+
+/* USER CODE BEGIN Header_StartTask02 */
+/**
+* @brief Function implementing the BlinkLED thread.
+* @param argument: Not used
+* @retval None
+*/
+/* USER CODE END Header_StartTask02 */
+void StartTask02(void const * argument)
+{
+ /* USER CODE BEGIN StartTask02 */
+ /* Infinite loop */
+ for(;;)
+ {
+ blinkaled();
+ }
+ /* USER CODE END StartTask02 */
+}
+
+void blinkaled(void)
+{
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET);
+ HAL_Delay(1000);
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET);
+ HAL_Delay(1000);
+}
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/57/00b38daf78c5001d13d6fe58f0709e0f b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/57/00b38daf78c5001d13d6fe58f0709e0f
new file mode 100644
index 0000000..2b4222f
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/57/00b38daf78c5001d13d6fe58f0709e0f
@@ -0,0 +1,3 @@
+635E684B79701B039C64EA45C3F84D30=2B8A1A14D46119CD49E4AAC54D250F3F
+DC22A860405A8BF2F2C095E5B6529F12=F90B087FDAEC68C8F01B9C0344FA7B26
+eclipse.preferences.version=1
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/5c/e082ac857ec5001d13d6fe58f0709e0f b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/5c/e082ac857ec5001d13d6fe58f0709e0f
new file mode 100644
index 0000000..b0633dd
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/5c/e082ac857ec5001d13d6fe58f0709e0f
@@ -0,0 +1,226 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+
+osThreadId defaultTaskHandle;
+osThreadId BlinkLEDHandle;
+
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+void StartDefaultTask(void const * argument);
+void StartTask02(void const * argument);
+void blinkaled(void)
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ /* MCU Configuration--------------------------------------------------------*/
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+ /* Configure the system clock */
+ SystemClock_Config();
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+
+ /* Create the thread(s) */
+ /* definition and creation of defaultTask */
+ osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 128);
+ defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
+
+ /* definition and creation of BlinkLED */
+ osThreadDef(blinkaled, StartTask02, osPriorityIdle, 0, 128);
+ BlinkLEDHandle = osThreadCreate(osThread(blinkaled), NULL);
+
+ /* Start scheduler */
+ osKernelStart();
+
+ /* We should never get here as control is now taken by the scheduler */
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ {
+ /* USER CODE END WHILE */
+
+ /* USER CODE BEGIN 3 */
+ }
+ /* USER CODE END 3 */
+}
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16;
+ RCC_OscInitStruct.PLL.PLLN = 336;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+
+/**
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin : B1_Pin */
+ GPIO_InitStruct.Pin = B1_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
+
+ /*Configure GPIO pin : LD2_Pin */
+ GPIO_InitStruct.Pin = LD2_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+
+/* USER CODE BEGIN Header_StartDefaultTask */
+/**
+ * @brief Function implementing the defaultTask thread.
+ * @param argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void const * argument)
+{
+ /* USER CODE BEGIN 5 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END 5 */
+}
+
+/* USER CODE BEGIN Header_StartTask02 */
+/**
+* @brief Function implementing the BlinkLED thread.
+* @param argument: Not used
+* @retval None
+*/
+/* USER CODE END Header_StartTask02 */
+void StartTask02(void const * argument)
+{
+ /* USER CODE BEGIN StartTask02 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END StartTask02 */
+}
+
+void blinkaled(void)
+{
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET);
+ HAL_Delay(1000);
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET);
+ HAL_Delay(1000);
+}
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/73/9026441f7cc5001d13d6fe58f0709e0f b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/73/9026441f7cc5001d13d6fe58f0709e0f
new file mode 100644
index 0000000..c8f66ab
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/73/9026441f7cc5001d13d6fe58f0709e0f
@@ -0,0 +1,250 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+UART_HandleTypeDef huart2;
+
+osThreadId defaultTaskHandle;
+osThreadId BlinkLEDHandle;
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_USART2_UART_Init(void);
+void StartDefaultTask(void const * argument);
+void StartTask02(void const * argument);
+
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ /* MCU Configuration--------------------------------------------------------*/
+
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+
+ /* Configure the system clock */
+ SystemClock_Config();
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+
+ /* Create the thread(s) */
+ /* definition and creation of defaultTask */
+ osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 128);
+ defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
+
+ /* definition and creation of BlinkLED */
+ osThreadDef(BlinkLED, StartTask02, osPriorityIdle, 0, 128);
+ BlinkLEDHandle = osThreadCreate(osThread(BlinkLED), NULL);
+
+ /* USER CODE BEGIN RTOS_THREADS */
+ /* add threads, ... */
+ /* USER CODE END RTOS_THREADS */
+
+ /* Start scheduler */
+ osKernelStart();
+
+ /* We should never get here as control is now taken by the scheduler */
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ {
+ /* USER CODE END WHILE */
+
+ /* USER CODE BEGIN 3 */
+ }
+ /* USER CODE END 3 */
+}
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16;
+ RCC_OscInitStruct.PLL.PLLN = 336;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+
+/**
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin : B1_Pin */
+ GPIO_InitStruct.Pin = B1_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
+
+ /*Configure GPIO pin : LD2_Pin */
+ GPIO_InitStruct.Pin = LD2_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+
+/* USER CODE BEGIN Header_StartDefaultTask */
+/**
+ * @brief Function implementing the defaultTask thread.
+ * @param argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void const * argument)
+{
+ /* USER CODE BEGIN 5 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END 5 */
+}
+
+/* USER CODE BEGIN Header_StartTask02 */
+/**
+* @brief Function implementing the BlinkLED thread.
+* @param argument: Not used
+* @retval None
+*/
+/* USER CODE END Header_StartTask02 */
+void StartTask02(void const * argument)
+{
+ /* USER CODE BEGIN StartTask02 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END StartTask02 */
+}
+
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/8f/709053d17ac5001d13d6fe58f0709e0f b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/8f/709053d17ac5001d13d6fe58f0709e0f
new file mode 100644
index 0000000..65407d2
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/8f/709053d17ac5001d13d6fe58f0709e0f
@@ -0,0 +1,4 @@
+635E684B79701B039C64EA45C3F84D30=2B8A1A14D46119CD49E4AAC54D250F3F
+66BE74F758C12D739921AEA421D593D3=0
+DC22A860405A8BF2F2C095E5B6529F12=F90B087FDAEC68C8F01B9C0344FA7B26
+eclipse.preferences.version=1
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/9/a06a581285c5001d13d6fe58f0709e0f b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/9/a06a581285c5001d13d6fe58f0709e0f
new file mode 100644
index 0000000..9e878b1
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/9/a06a581285c5001d13d6fe58f0709e0f
@@ -0,0 +1,236 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+
+osThreadId defaultTaskHandle;
+osThreadId BlinkLEDHandle;
+
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+void StartDefaultTask(void const * argument);
+void StartTask02(void const * argument);
+void blinkaled(void);
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ /* MCU Configuration--------------------------------------------------------*/
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+ /* Configure the system clock */
+ SystemClock_Config();
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+
+ /* Create the thread(s) */
+ /* definition and creation of defaultTask */
+ osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 128);
+ defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
+
+ /* definition and creation of BlinkLED */
+ osThreadDef(blinkaled, StartTask02, osPriorityIdle, 0, 128);
+ BlinkLEDHandle = osThreadCreate(osThread(blinkaled), NULL);
+
+ /* Start scheduler */
+ osKernelStart();
+
+ /* We should never get here as control is now taken by the scheduler */
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ {
+ /* USER CODE END WHILE */
+
+ /* USER CODE BEGIN 3 */
+ }
+ /* USER CODE END 3 */
+}
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16;
+ RCC_OscInitStruct.PLL.PLLN = 336;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+
+/**
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin : B1_Pin */
+ GPIO_InitStruct.Pin = B1_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
+
+ /*Configure GPIO pin : LD2_Pin */
+ GPIO_InitStruct.Pin = LD2_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+
+/* USER CODE BEGIN Header_StartDefaultTask */
+/**
+ * @brief Function implementing the defaultTask thread.
+ * @param argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void const * argument)
+{
+ /* USER CODE BEGIN 5 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END 5 */
+}
+
+/* USER CODE BEGIN Header_StartTask02 */
+/**
+* @brief Function implementing the blinkaled thread.
+* @param argument: Not used
+* @retval None
+*/
+/* USER CODE END Header_StartTask02 */
+void StartTask02(void const * argument)
+{
+ /* USER CODE BEGIN StartTask02 */
+ /* Infinite loop */
+ for(;;)
+ {
+ blinkaled();
+ }
+ /* USER CODE END StartTask02 */
+}
+
+/*
+ * Function: blinkled
+ * Blinks an LED connected to GPIOA Pin 5 by setting it high for 1 second and then low for 1 second.
+ * Parameters: None
+ * Returns: None
+ */
+void blinkaled(void)
+{
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET);
+ HAL_Delay(1000);
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET);
+ HAL_Delay(1000);
+}
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/a1/90e171dc80c5001d13d6fe58f0709e0f b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/a1/90e171dc80c5001d13d6fe58f0709e0f
new file mode 100644
index 0000000..978b55f
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/a1/90e171dc80c5001d13d6fe58f0709e0f
@@ -0,0 +1,232 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+
+osThreadId defaultTaskHandle;
+osThreadId BlinkLEDHandle;
+
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+void StartDefaultTask(void const * argument);
+void StartTask02(void const * argument);
+void blinkaled(void);
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ /* MCU Configuration--------------------------------------------------------*/
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+ /* Configure the system clock */
+ SystemClock_Config();
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+
+ /* Create the thread(s) */
+ /* definition and creation of defaultTask */
+ osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 128);
+ defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
+
+ /* definition and creation of BlinkLED */
+ osThreadDef(blinkaled, StartTask02, osPriorityIdle, 0, 128);
+ BlinkLEDHandle = osThreadCreate(osThread(blinkaled), NULL);
+
+ /* Start scheduler */
+ osKernelStart();
+
+ /* We should never get here as control is now taken by the scheduler */
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ {
+ /* USER CODE END WHILE */
+
+ /* USER CODE BEGIN 3 */
+ }
+ /* USER CODE END 3 */
+}
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16;
+ RCC_OscInitStruct.PLL.PLLN = 336;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+
+/**
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin : B1_Pin */
+ GPIO_InitStruct.Pin = B1_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
+
+ /*Configure GPIO pin : LD2_Pin */
+ GPIO_InitStruct.Pin = LD2_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+
+/* USER CODE BEGIN Header_StartDefaultTask */
+/**
+ * @brief Function implementing the defaultTask thread.
+ * @param argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void const * argument)
+{
+ /* USER CODE BEGIN 5 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END 5 */
+}
+
+/* USER CODE BEGIN Header_StartTask02 */
+/**
+* @brief Function implementing the blinkaled thread.
+* @param argument: Not used
+* @retval None
+*/
+/* USER CODE END Header_StartTask02 */
+void StartTask02(void const * argument)
+{
+ /* USER CODE BEGIN StartTask02 */
+ /* Infinite loop */
+ for(;;)
+ {
+ blinkaled();
+ }
+ /* USER CODE END StartTask02 */
+}
+
+/*
+ * Function: blinkled
+ * Blinks an LED connected to GPIOA Pin 5 by setting it high for 1 second and then low for 1 second.
+ * Parameters: None
+ * Returns: None
+ */
+void blinkaled(void)
+{
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET);
+ HAL_Delay(1000);
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET);
+ HAL_Delay(1000);
+}
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/a5/70e720af78c5001d13d6fe58f0709e0f b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/a5/70e720af78c5001d13d6fe58f0709e0f
new file mode 100644
index 0000000..000a47c
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/a5/70e720af78c5001d13d6fe58f0709e0f
@@ -0,0 +1,2 @@
+635E684B79701B039C64EA45C3F84D30=2B8A1A14D46119CD49E4AAC54D250F3F
+eclipse.preferences.version=1
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/bd/7075fe0d7cc5001d13d6fe58f0709e0f b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/bd/7075fe0d7cc5001d13d6fe58f0709e0f
new file mode 100644
index 0000000..1d5839e
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/bd/7075fe0d7cc5001d13d6fe58f0709e0f
@@ -0,0 +1,327 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+UART_HandleTypeDef huart2;
+
+osThreadId defaultTaskHandle;
+osThreadId BlinkLEDHandle;
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_USART2_UART_Init(void);
+void StartDefaultTask(void const * argument);
+void StartTask02(void const * argument);
+
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ /* USER CODE BEGIN 1 */
+
+ /* USER CODE END 1 */
+
+ /* MCU Configuration--------------------------------------------------------*/
+
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+
+ /* USER CODE BEGIN Init */
+
+ /* USER CODE END Init */
+
+ /* Configure the system clock */
+ SystemClock_Config();
+
+ /* USER CODE BEGIN SysInit */
+
+ /* USER CODE END SysInit */
+
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+ MX_USART2_UART_Init();
+ /* USER CODE BEGIN 2 */
+
+ /* USER CODE END 2 */
+
+ /* USER CODE BEGIN RTOS_MUTEX */
+ /* add mutexes, ... */
+ /* USER CODE END RTOS_MUTEX */
+
+ /* USER CODE BEGIN RTOS_SEMAPHORES */
+ /* add semaphores, ... */
+ /* USER CODE END RTOS_SEMAPHORES */
+
+ /* USER CODE BEGIN RTOS_TIMERS */
+ /* start timers, add new ones, ... */
+ /* USER CODE END RTOS_TIMERS */
+
+ /* USER CODE BEGIN RTOS_QUEUES */
+ /* add queues, ... */
+ /* USER CODE END RTOS_QUEUES */
+
+ /* Create the thread(s) */
+ /* definition and creation of defaultTask */
+ osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 128);
+ defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
+
+ /* definition and creation of BlinkLED */
+ osThreadDef(BlinkLED, StartTask02, osPriorityIdle, 0, 128);
+ BlinkLEDHandle = osThreadCreate(osThread(BlinkLED), NULL);
+
+ /* USER CODE BEGIN RTOS_THREADS */
+ /* add threads, ... */
+ /* USER CODE END RTOS_THREADS */
+
+ /* Start scheduler */
+ osKernelStart();
+
+ /* We should never get here as control is now taken by the scheduler */
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ {
+ /* USER CODE END WHILE */
+
+ /* USER CODE BEGIN 3 */
+ }
+ /* USER CODE END 3 */
+}
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16;
+ RCC_OscInitStruct.PLL.PLLN = 336;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+/**
+ * @brief USART2 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_USART2_UART_Init(void)
+{
+
+ /* USER CODE BEGIN USART2_Init 0 */
+
+ /* USER CODE END USART2_Init 0 */
+
+ /* USER CODE BEGIN USART2_Init 1 */
+
+ /* USER CODE END USART2_Init 1 */
+ huart2.Instance = USART2;
+ huart2.Init.BaudRate = 115200;
+ huart2.Init.WordLength = UART_WORDLENGTH_8B;
+ huart2.Init.StopBits = UART_STOPBITS_1;
+ huart2.Init.Parity = UART_PARITY_NONE;
+ huart2.Init.Mode = UART_MODE_TX_RX;
+ huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ huart2.Init.OverSampling = UART_OVERSAMPLING_16;
+ if (HAL_UART_Init(&huart2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN USART2_Init 2 */
+
+ /* USER CODE END USART2_Init 2 */
+
+}
+
+/**
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin : B1_Pin */
+ GPIO_InitStruct.Pin = B1_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
+
+ /*Configure GPIO pin : LD2_Pin */
+ GPIO_InitStruct.Pin = LD2_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/* USER CODE BEGIN Header_StartDefaultTask */
+/**
+ * @brief Function implementing the defaultTask thread.
+ * @param argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void const * argument)
+{
+ /* USER CODE BEGIN 5 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END 5 */
+}
+
+/* USER CODE BEGIN Header_StartTask02 */
+/**
+* @brief Function implementing the BlinkLED thread.
+* @param argument: Not used
+* @retval None
+*/
+/* USER CODE END Header_StartTask02 */
+void StartTask02(void const * argument)
+{
+ /* USER CODE BEGIN StartTask02 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END StartTask02 */
+}
+
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/bd/a0bac3217ec5001d13d6fe58f0709e0f b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/bd/a0bac3217ec5001d13d6fe58f0709e0f
new file mode 100644
index 0000000..1dccd52
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/bd/a0bac3217ec5001d13d6fe58f0709e0f
@@ -0,0 +1,250 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+UART_HandleTypeDef huart2;
+
+osThreadId defaultTaskHandle;
+osThreadId BlinkLEDHandle;
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+void StartDefaultTask(void const * argument);
+void StartTask02(void const * argument);
+
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ /* MCU Configuration--------------------------------------------------------*/
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+ /* Configure the system clock */
+ SystemClock_Config();
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+
+ /* Create the thread(s) */
+ /* definition and creation of defaultTask */
+ osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 128);
+ defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
+
+ /* definition and creation of BlinkLED */
+ osThreadDef(blinkaled, StartTask02, osPriorityIdle, 0, 128);
+ BlinkLEDHandle = osThreadCreate(osThread(blinkaled), NULL);
+
+ /* Start scheduler */
+ osKernelStart();
+
+ /* We should never get here as control is now taken by the scheduler */
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ {
+ /* USER CODE END WHILE */
+
+ /* USER CODE BEGIN 3 */
+ }
+ /* USER CODE END 3 */
+}
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16;
+ RCC_OscInitStruct.PLL.PLLN = 336;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+
+/**
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin : B1_Pin */
+ GPIO_InitStruct.Pin = B1_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
+
+ /*Configure GPIO pin : LD2_Pin */
+ GPIO_InitStruct.Pin = LD2_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+
+/* USER CODE BEGIN Header_StartDefaultTask */
+/**
+ * @brief Function implementing the defaultTask thread.
+ * @param argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void const * argument)
+{
+ /* USER CODE BEGIN 5 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END 5 */
+}
+
+/* USER CODE BEGIN Header_StartTask02 */
+/**
+* @brief Function implementing the BlinkLED thread.
+* @param argument: Not used
+* @retval None
+*/
+/* USER CODE END Header_StartTask02 */
+void StartTask02(void const * argument)
+{
+ /* USER CODE BEGIN StartTask02 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END StartTask02 */
+}
+
+void blinkaled(void)
+{
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET);
+ HAL_Delay(1000);
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET);
+ HAL_Delay(1000);
+}
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/f2/a03d30fb7dc5001d13d6fe58f0709e0f b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/f2/a03d30fb7dc5001d13d6fe58f0709e0f
new file mode 100644
index 0000000..ae202cb
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/f2/a03d30fb7dc5001d13d6fe58f0709e0f
@@ -0,0 +1,249 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+UART_HandleTypeDef huart2;
+
+osThreadId defaultTaskHandle;
+osThreadId BlinkLEDHandle;
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+void StartDefaultTask(void const * argument);
+void StartTask02(void const * argument);
+
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ /* MCU Configuration--------------------------------------------------------*/
+
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+
+ /* Configure the system clock */
+ SystemClock_Config();
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+
+ /* Create the thread(s) */
+ /* definition and creation of defaultTask */
+ osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 128);
+ defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
+
+ /* definition and creation of BlinkLED */
+ osThreadDef(BlinkLED, StartTask02, osPriorityIdle, 0, 128);
+ BlinkLEDHandle = osThreadCreate(osThread(BlinkLED), NULL);
+
+ /* USER CODE BEGIN RTOS_THREADS */
+ /* add threads, ... */
+ /* USER CODE END RTOS_THREADS */
+
+ /* Start scheduler */
+ osKernelStart();
+
+ /* We should never get here as control is now taken by the scheduler */
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ {
+ /* USER CODE END WHILE */
+
+ /* USER CODE BEGIN 3 */
+ }
+ /* USER CODE END 3 */
+}
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16;
+ RCC_OscInitStruct.PLL.PLLN = 336;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+
+/**
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin : B1_Pin */
+ GPIO_InitStruct.Pin = B1_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
+
+ /*Configure GPIO pin : LD2_Pin */
+ GPIO_InitStruct.Pin = LD2_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+
+/* USER CODE BEGIN Header_StartDefaultTask */
+/**
+ * @brief Function implementing the defaultTask thread.
+ * @param argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void const * argument)
+{
+ /* USER CODE BEGIN 5 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END 5 */
+}
+
+/* USER CODE BEGIN Header_StartTask02 */
+/**
+* @brief Function implementing the BlinkLED thread.
+* @param argument: Not used
+* @retval None
+*/
+/* USER CODE END Header_StartTask02 */
+void StartTask02(void const * argument)
+{
+ /* USER CODE BEGIN StartTask02 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END StartTask02 */
+}
+
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/ff/b0366ba17fc5001d13d6fe58f0709e0f b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.resources/.history/ff/b0366ba17fc5001d13d6fe58f0709e0f
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@@ -0,0 +1,226 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+
+osThreadId defaultTaskHandle;
+osThreadId BlinkLEDHandle;
+
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+void StartDefaultTask(void const * argument);
+void StartTask02(void const * argument);
+void blinkaled(void);
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ /* MCU Configuration--------------------------------------------------------*/
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+ /* Configure the system clock */
+ SystemClock_Config();
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+
+ /* Create the thread(s) */
+ /* definition and creation of defaultTask */
+ osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 128);
+ defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
+
+ /* definition and creation of BlinkLED */
+ osThreadDef(blinkaled, StartTask02, osPriorityIdle, 0, 128);
+ BlinkLEDHandle = osThreadCreate(osThread(blinkaled), NULL);
+
+ /* Start scheduler */
+ osKernelStart();
+
+ /* We should never get here as control is now taken by the scheduler */
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ {
+ /* USER CODE END WHILE */
+
+ /* USER CODE BEGIN 3 */
+ }
+ /* USER CODE END 3 */
+}
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16;
+ RCC_OscInitStruct.PLL.PLLN = 336;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+
+/**
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin : B1_Pin */
+ GPIO_InitStruct.Pin = B1_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
+
+ /*Configure GPIO pin : LD2_Pin */
+ GPIO_InitStruct.Pin = LD2_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+
+/* USER CODE BEGIN Header_StartDefaultTask */
+/**
+ * @brief Function implementing the defaultTask thread.
+ * @param argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void const * argument)
+{
+ /* USER CODE BEGIN 5 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END 5 */
+}
+
+/* USER CODE BEGIN Header_StartTask02 */
+/**
+* @brief Function implementing the BlinkLED thread.
+* @param argument: Not used
+* @retval None
+*/
+/* USER CODE END Header_StartTask02 */
+void StartTask02(void const * argument)
+{
+ /* USER CODE BEGIN StartTask02 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END StartTask02 */
+}
+
+void blinkaled(void)
+{
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET);
+ HAL_Delay(1000);
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET);
+ HAL_Delay(1000);
+}
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
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diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs
new file mode 100644
index 0000000..dffc6b5
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
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diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs
new file mode 100644
index 0000000..c8e90d4
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs
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+//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.debug.gdbjtag.launchConfigurationType=org.eclipse.cdt.debug.gdbjtag.core.dsfLaunchDelegate,debug,;
+//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.applicationLaunchType=org.eclipse.cdt.dsf.gdb.launch.localCLaunch,debug,;org.eclipse.cdt.cdi.launch.localCLaunch,run,;
+//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.attachLaunchType=org.eclipse.cdt.dsf.gdb.launch.attachCLaunch,debug,;
+//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.postmortemLaunchType=org.eclipse.cdt.dsf.gdb.launch.coreCLaunch,debug,;
+//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.remoteApplicationLaunchType=org.eclipse.rse.remotecdt.dsf.debug,debug,;
+eclipse.preferences.version=1
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs
new file mode 100644
index 0000000..f83fb63
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs
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+eclipse.preferences.version=1
+org.eclipse.debug.ui.PREF_LAUNCH_PERSPECTIVES=\r\n\r\n
+preferredTargets=org.eclipse.cdt.debug.ui.toggleCBreakpointTarget,org.eclipse.cdt.debug.ui.toggleCDynamicPrintfTarget\:org.eclipse.cdt.debug.ui.toggleCBreakpointTarget|
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.launchbar.core.prefs b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.launchbar.core.prefs
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+LaunchTargetManager/org.eclipse.launchbar.core.launchTargetType.local,Local/arch=x86_64
+LaunchTargetManager/org.eclipse.launchbar.core.launchTargetType.local,Local/name=Local
+LaunchTargetManager/org.eclipse.launchbar.core.launchTargetType.local,Local/os=win32
+configDescList=org.eclipse.cdt.dsf.gdb.gdbRemotedescriptorType\:FreeRTOS_LED
+eclipse.preferences.version=1
+org.eclipse.cdt.dsf.gdb.gdbRemotedescriptorType\:FreeRTOS_LED/activeLaunchMode=run
+org.eclipse.cdt.dsf.gdb.gdbRemotedescriptorType\:FreeRTOS_LED/activeLaunchTarget=null\:---
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.navigator.prefs b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.navigator.prefs
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+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.navigator.prefs
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+eclipse.preferences.version=1
+org.eclipse.ui.navigator.ProjectExplorer.filterActivation=\:org.eclipse.ui.navigator.resources.filters.startsWithDot\:org.eclipse.cdt.ui.navigator.filters.AnonymousStructFilter\:org.eclipse.ui.navigator.resources.nested.HideTopLevelProjectIfNested\:org.eclipse.ui.navigator.resources.nested.HideFolderWhenProjectIsShownAsNested\:org.eclipse.cdt.ui.navigator.filters.ForwardDeclarationFilter\:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs
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+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs
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+eclipse.preferences.version=1
+showIntro=false
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs
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index 0000000..83ca6f6
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+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs
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+UIActivities.org.eclipse.cdt.debug.dsfgdbActivity=true
+eclipse.preferences.version=1
+org.eclipse.ui.workbench.ACTIVE_NOFOCUS_TAB_BG_END=255,255,255
+org.eclipse.ui.workbench.ACTIVE_NOFOCUS_TAB_BG_START=255,255,255
+org.eclipse.ui.workbench.ACTIVE_NOFOCUS_TAB_TEXT_COLOR=16,16,16
+org.eclipse.ui.workbench.ACTIVE_TAB_BG_END=255,255,255
+org.eclipse.ui.workbench.ACTIVE_TAB_BG_START=255,255,255
+org.eclipse.ui.workbench.INACTIVE_TAB_BG_START=242,242,242
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.urischeme.prefs b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.urischeme.prefs
new file mode 100644
index 0000000..855d634
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.urischeme.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+processedSchemes=,eclipse+command,eclipse+mpc
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml
new file mode 100644
index 0000000..a1adbe6
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml
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diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi
new file mode 100644
index 0000000..e2d90ba
--- /dev/null
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diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml
new file mode 100644
index 0000000..35be43f
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml
@@ -0,0 +1,6 @@
+
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diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml
new file mode 100644
index 0000000..d57254a
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml
@@ -0,0 +1,4 @@
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\ No newline at end of file
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/version.ini b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/version.ini
new file mode 100644
index 0000000..49433ed
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.metadata/version.ini
@@ -0,0 +1,3 @@
+#Sat Mar 18 11:32:46 CET 2023
+org.eclipse.core.runtime=2
+org.eclipse.platform=4.23.0.v20220308-0310
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.mxproject b/tutorial01-stm32-pio-01/pio-01-02_olivia/.mxproject
new file mode 100644
index 0000000..7327952
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.mxproject
@@ -0,0 +1,27 @@
+[PreviousLibFiles]
+LibFiles=Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_bus.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_system.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_utils.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dmamux.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usart.h;Middlewares\Third_Party\FreeRTOS\Source\include\croutine.h;Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h;Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h;Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h;Middlewares\Third_Party\FreeRTOS\Source\include\list.h;Middlewares\Third_Party\FreeRTOS\Source\include\message_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_prototypes.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h;Middlewares\Third_Party\FreeRTOS\Source\include\portable.h;Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h;Middlewares\Third_Party\FreeRTOS\Source\include\queue.h;Middlewares\Third_Party\FreeRTOS\Source\include\semphr.h;Middlewares\Third_Party\FreeRTOS\Source\include\stack_macros.h;Middlewares\Third_Party\FreeRTOS\Source\include\StackMacros.h;Middlewares\Third_Party\FreeRTOS\Source\include\stream_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\task.h;Middlewares\Third_Party\FreeRTOS\Source\include\timers.h;Middlewares\Third_Party\FreeRTOS\Source\include\atomic.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS\cmsis_os.h;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\portmacro.h;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS\cmsis_os.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_bus.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_system.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_utils.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dmamux.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usart.h;Middlewares\Third_Party\FreeRTOS\Source\include\croutine.h;Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h;Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h;Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h;Middlewares\Third_Party\FreeRTOS\Source\include\list.h;Middlewares\Third_Party\FreeRTOS\Source\include\message_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_prototypes.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h;Middlewares\Third_Party\FreeRTOS\Source\include\portable.h;Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h;Middlewares\Third_Party\FreeRTOS\Source\include\queue.h;Middlewares\Third_Party\FreeRTOS\Source\include\semphr.h;Middlewares\Third_Party\FreeRTOS\Source\include\stack_macros.h;Middlewares\Third_Party\FreeRTOS\Source\include\StackMacros.h;Middlewares\Third_Party\FreeRTOS\Source\include\stream_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\task.h;Middlewares\Third_Party\FreeRTOS\Source\include\timers.h;Middlewares\Third_Party\FreeRTOS\Source\include\atomic.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS\cmsis_os.h;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\portmacro.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f446xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
+
+[PreviousUsedCubeIDEFiles]
+SourceFiles=Core\Src\main.c;Core\Src\freertos.c;Core\Src\stm32f4xx_it.c;Core\Src\stm32f4xx_hal_msp.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS\cmsis_os.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;Core\Src\system_stm32f4xx.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS\cmsis_os.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;Core\Src\system_stm32f4xx.c;;;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS\cmsis_os.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;
+HeaderPath=Drivers\STM32F4xx_HAL_Driver\Inc;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;Middlewares\Third_Party\FreeRTOS\Source\include;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F;Drivers\CMSIS\Device\ST\STM32F4xx\Include;Drivers\CMSIS\Include;Core\Inc;
+CDefines=USE_HAL_DRIVER;STM32F446xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
+[PreviousGenFiles]
+AdvancedFolderStructure=true
+HeaderFileListSize=4
+HeaderFiles#0=..\Core\Inc\FreeRTOSConfig.h
+HeaderFiles#1=..\Core\Inc\stm32f4xx_it.h
+HeaderFiles#2=..\Core\Inc\stm32f4xx_hal_conf.h
+HeaderFiles#3=..\Core\Inc\main.h
+HeaderFolderListSize=1
+HeaderPath#0=..\Core\Inc
+HeaderFiles=;
+SourceFileListSize=4
+SourceFiles#0=..\Core\Src\freertos.c
+SourceFiles#1=..\Core\Src\stm32f4xx_it.c
+SourceFiles#2=..\Core\Src\stm32f4xx_hal_msp.c
+SourceFiles#3=..\Core\Src\main.c
+SourceFolderListSize=1
+SourcePath#0=..\Core\Src
+SourceFiles=;
+
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.project b/tutorial01-stm32-pio-01/pio-01-02_olivia/.project
new file mode 100644
index 0000000..929aa37
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.project
@@ -0,0 +1,32 @@
+
+
+ FreeRTOS_LED
+
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ com.st.stm32cube.ide.mcu.MCUProjectNature
+ com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+ org.eclipse.cdt.core.cnature
+ com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature
+ com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature
+ com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+ com.st.stm32cube.ide.mcu.MCURootProjectNature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.settings/language.settings.xml b/tutorial01-stm32-pio-01/pio-01-02_olivia/.settings/language.settings.xml
new file mode 100644
index 0000000..d35b802
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/.settings/stm32cubeide.project.prefs b/tutorial01-stm32-pio-01/pio-01-02_olivia/.settings/stm32cubeide.project.prefs
new file mode 100644
index 0000000..e0008a6
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/.settings/stm32cubeide.project.prefs
@@ -0,0 +1,5 @@
+635E684B79701B039C64EA45C3F84D30=2B8A1A14D46119CD49E4AAC54D250F3F
+66BE74F758C12D739921AEA421D593D3=1
+8DF89ED150041C4CBC7CB9A9CAA90856=F90B087FDAEC68C8F01B9C0344FA7B26
+DC22A860405A8BF2F2C095E5B6529F12=F90B087FDAEC68C8F01B9C0344FA7B26
+eclipse.preferences.version=1
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/CMakeLists.txt b/tutorial01-stm32-pio-01/pio-01-02_olivia/CMakeLists.txt
new file mode 100644
index 0000000..5b048d2
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/CMakeLists.txt
@@ -0,0 +1,208 @@
+cmake_minimum_required(VERSION 3.15)
+
+# User is responsible to set two mandatory options:
+# FREERTOS_CONFIG_FILE_DIRECTORY
+# FREERTOS_PORT
+#
+# User can choose which heap implementation to use (either the implementations
+# included with FreeRTOS [1..5] or a custom implementation ) by providing the
+# option FREERTOS_HEAP. If the option is not set, the cmake will default to
+# using heap_4.c.
+
+# Absolute path to FreeRTOS config file directory
+set(FREERTOS_CONFIG_FILE_DIRECTORY "" CACHE STRING "Absolute path to the directory with FreeRTOSConfig.h")
+
+if(NOT FREERTOS_CONFIG_FILE_DIRECTORY)
+ message(FATAL_ERROR " FreeRTOSConfig.h file directory not specified. Please specify absolute path to it from top-level CMake file:\n"
+ " set(FREERTOS_CONFIG_FILE_DIRECTORY CACHE STRING \"\")\n"
+ " or from CMake command line option:\n"
+ " -DFREERTOS_CONFIG_FILE_DIRECTORY='/absolute_path/to/FreeRTOSConfig.h/directory'")
+elseif(NOT EXISTS ${FREERTOS_CONFIG_FILE_DIRECTORY}/FreeRTOSConfig.h)
+ message(FATAL_ERROR " FreeRTOSConfig.h file not found in the directory specified (${FREERTOS_CONFIG_FILE_DIRECTORY})\n"
+ " Please specify absolute path to it from top-level CMake file:\n"
+ " set(FREERTOS_CONFIG_FILE_DIRECTORY CACHE STRING \"\")\n"
+ " or from CMake command line option:\n"
+ " -DFREERTOS_CONFIG_FILE_DIRECTORY='/absolute_path/to/FreeRTOSConfig.h/directory'")
+endif()
+
+# Heap number or absolute path to custom heap implementation provided by user
+set(FREERTOS_HEAP "4" CACHE STRING "FreeRTOS heap model number. 1 .. 5. Or absolute path to custom heap source file")
+
+# FreeRTOS port option
+set(FREERTOS_PORT "" CACHE STRING "FreeRTOS port name")
+
+if(NOT FREERTOS_PORT)
+ message(FATAL_ERROR " FREERTOS_PORT is not set. Please specify it from top-level CMake file (example):\n"
+ " set(FREERTOS_PORT GCC_ARM_CM4F CACHE STRING \"\")\n"
+ " or from CMake command line option:\n"
+ " -DFREERTOS_PORT=GCC_ARM_CM4F\n"
+ " \n"
+ " Available port options:\n"
+ " BCC_16BIT_DOS_FLSH186 - Compiller: BCC Target: 16 bit DOS Flsh186\n"
+ " BCC_16BIT_DOS_PC - Compiller: BCC Target: 16 bit DOS PC\n"
+ " CCS_ARM_CM3 - Compiller: CCS Target: ARM Cortex-M3\n"
+ " CCS_ARM_CM4F - Compiller: CCS Target: ARM Cortex-M4 with FPU\n"
+ " CCS_ARM_CR4 - Compiller: CCS Target: ARM Cortex-R4\n"
+ " CCS_MSP430X - Compiller: CCS Target: MSP430X\n"
+ " CODEWARRIOR_COLDFIRE_V1 - Compiller: CoreWarrior Target: ColdFire V1\n"
+ " CODEWARRIOR_COLDFIRE_V2 - Compiller: CoreWarrior Target: ColdFire V2\n"
+ " CODEWARRIOR_HCS12 - Compiller: CoreWarrior Target: HCS12\n"
+ " GCC_ARM_CA9 - Compiller: GCC Target: ARM Cortex-A9\n"
+ " GCC_ARM_CA53_64_BIT - Compiller: GCC Target: ARM Cortex-A53 64 bit\n"
+ " GCC_ARM_CA53_64_BIT_SRE - Compiller: GCC Target: ARM Cortex-A53 64 bit SRE\n"
+ " GCC_ARM_CM0 - Compiller: GCC Target: ARM Cortex-M0\n"
+ " GCC_ARM_CM3 - Compiller: GCC Target: ARM Cortex-M3\n"
+ " GCC_ARM_CM3_MPU - Compiller: GCC Target: ARM Cortex-M3 with MPU\n"
+ " GCC_ARM_CM4_MPU - Compiller: GCC Target: ARM Cortex-M4 with MPU\n"
+ " GCC_ARM_CM4F - Compiller: GCC Target: ARM Cortex-M4 with FPU\n"
+ " GCC_ARM_CM7 - Compiller: GCC Target: ARM Cortex-M7\n"
+ " GCC_ARM_CM23_NONSECURE - Compiller: GCC Target: ARM Cortex-M23 non-secure\n"
+ " GCC_ARM_CM23_SECURE - Compiller: GCC Target: ARM Cortex-M23 secure\n"
+ " GCC_ARM_CM23_NTZ_NONSECURE - Compiller: GCC Target: ARM Cortex-M23 non-trustzone non-secure\n"
+ " GCC_ARM_CM33_NONSECURE - Compiller: GCC Target: ARM Cortex-M33 non-secure\n"
+ " GCC_ARM_CM33_SECURE - Compiller: GCC Target: ARM Cortex-M33 secure\n"
+ " GCC_ARM_CM33_NTZ_NONSECURE - Compiller: GCC Target: ARM Cortex-M33 non-trustzone non-secure\n"
+ " GCC_ARM_CM33_TFM - Compiller: GCC Target: ARM Cortex-M33 non-secure for TF-M\n"
+ " GCC_ARM_CM55_NONSECURE - Compiller: GCC Target: ARM Cortex-M55 non-secure\n"
+ " GCC_ARM_CM55_SECURE - Compiller: GCC Target: ARM Cortex-M55 secure\n"
+ " GCC_ARM_CM55_NTZ_NONSECURE - Compiller: GCC Target: ARM Cortex-M55 non-trustzone non-secure\n"
+ " GCC_ARM_CM55_TFM - Compiller: GCC Target: ARM Cortex-M55 non-secure for TF-M\n"
+ " GCC_ARM_CM85_NONSECURE - Compiller: GCC Target: ARM Cortex-M85 non-secure\n"
+ " GCC_ARM_CM85_SECURE - Compiller: GCC Target: ARM Cortex-M85 secure\n"
+ " GCC_ARM_CM85_NTZ_NONSECURE - Compiller: GCC Target: ARM Cortex-M85 non-trustzone non-secure\n"
+ " GCC_ARM_CM85_TFM - Compiller: GCC Target: ARM Cortex-M85 non-secure for TF-M\n"
+ " GCC_ARM_CR5 - Compiller: GCC Target: ARM Cortex-R5\n"
+ " GCC_ARM_CRX_NOGIC - Compiller: GCC Target: ARM Cortex-Rx no GIC\n"
+ " GCC_ARM7_AT91FR40008 - Compiller: GCC Target: ARM7 Atmel AT91R40008\n"
+ " GCC_ARM7_AT91SAM7S - Compiller: GCC Target: ARM7 Atmel AT91SAM7S\n"
+ " GCC_ARM7_LPC2000 - Compiller: GCC Target: ARM7 LPC2000\n"
+ " GCC_ARM7_LPC23XX - Compiller: GCC Target: ARM7 LPC23xx\n"
+ " GCC_ATMEGA323 - Compiller: GCC Target: ATMega323\n"
+ " GCC_AVR32_UC3 - Compiller: GCC Target: AVR32 UC3\n"
+ " GCC_COLDFIRE_V2 - Compiller: GCC Target: ColdFire V2\n"
+ " GCC_CORTUS_APS3 - Compiller: GCC Target: CORTUS APS3\n"
+ " GCC_H8S2329 - Compiller: GCC Target: H8S2329\n"
+ " GCC_HCS12 - Compiller: GCC Target: HCS12\n"
+ " GCC_IA32_FLAT - Compiller: GCC Target: IA32 flat\n"
+ " GCC_MICROBLAZE - Compiller: GCC Target: MicroBlaze\n"
+ " GCC_MICROBLAZE_V8 - Compiller: GCC Target: MicroBlaze V8\n"
+ " GCC_MICROBLAZE_V9 - Compiller: GCC Target: MicroBlaze V9\n"
+ " GCC_MSP430F449 - Compiller: GCC Target: MSP430F449\n"
+ " GCC_NIOSII - Compiller: GCC Target: NiosII\n"
+ " GCC_PPC405_XILINX - Compiller: GCC Target: Xilinx PPC405\n"
+ " GCC_PPC440_XILINX - Compiller: GCC Target: Xilinx PPC440\n"
+ " GCC_RISC_V - Compiller: GCC Target: RISC-V\n"
+ " GCC_RISC_V_PULPINO_VEGA_RV32M1RM - Compiller: GCC Target: RISC-V Pulpino Vega RV32M1RM\n"
+ " GCC_RL78 - Compiller: GCC Target: Renesas RL78\n"
+ " GCC_RX100 - Compiller: GCC Target: Renesas RX100\n"
+ " GCC_RX200 - Compiller: GCC Target: Renesas RX200\n"
+ " GCC_RX600 - Compiller: GCC Target: Renesas RX600\n"
+ " GCC_RX600_V2 - Compiller: GCC Target: Renesas RX600 v2\n"
+ " GCC_RX700_V3_DPFPU - Compiller: GCC Target: Renesas RX700 v3 with DPFPU\n"
+ " GCC_STR75X - Compiller: GCC Target: STR75x\n"
+ " GCC_TRICORE_1782 - Compiller: GCC Target: TriCore 1782\n"
+ " GCC_ARC_EM_HS - Compiller: GCC Target: DesignWare ARC EM HS\n"
+ " GCC_ARC_V1 - Compiller: GCC Target: DesignWare ARC v1\n"
+ " GCC_ATMEGA - Compiller: GCC Target: ATmega\n"
+ " GCC_POSIX - Compiller: GCC Target: Posix\n"
+ " GCC_RP2040 - Compiller: GCC Target: RP2040 ARM Cortex-M0+\n"
+ " GCC_XTENSA_ESP32 - Compiller: GCC Target: Xtensa ESP32\n"
+ " GCC_AVRDX - Compiller: GCC Target: AVRDx\n"
+ " GCC_AVR_MEGA0 - Compiller: GCC Target: AVR Mega0\n"
+ " IAR_78K0K - Compiller: IAR Target: Renesas 78K0K\n"
+ " IAR_ARM_CA5_NOGIC - Compiller: IAR Target: ARM Cortex-A5 no GIC\n"
+ " IAR_ARM_CA9 - Compiller: IAR Target: ARM Cortex-A9\n"
+ " IAR_ARM_CM0 - Compiller: IAR Target: ARM Cortex-M0\n"
+ " IAR_ARM_CM3 - Compiller: IAR Target: ARM Cortex-M3\n"
+ " IAR_ARM_CM4F - Compiller: IAR Target: ARM Cortex-M4 with FPU\n"
+ " IAR_ARM_CM4F_MPU - Compiller: IAR Target: ARM Cortex-M4 with FPU and MPU\n"
+ " IAR_ARM_CM7 - Compiller: IAR Target: ARM Cortex-M7\n"
+ " IAR_ARM_CM23_NONSECURE - Compiller: IAR Target: ARM Cortex-M23 non-secure\n"
+ " IAR_ARM_CM23_SECURE - Compiller: IAR Target: ARM Cortex-M23 secure\n"
+ " IAR_ARM_CM23_NTZ_NONSECURE - Compiller: IAR Target: ARM Cortex-M23 non-trustzone non-secure\n"
+ " IAR_ARM_CM33_NONSECURE - Compiller: IAR Target: ARM Cortex-M33 non-secure\n"
+ " IAR_ARM_CM33_SECURE - Compiller: IAR Target: ARM Cortex-M33 secure\n"
+ " IAR_ARM_CM33_NTZ_NONSECURE - Compiller: IAR Target: ARM Cortex-M33 non-trustzone non-secure\n"
+ " IAR_ARM_CM55_NONSECURE - Compiller: IAR Target: ARM Cortex-M55 non-secure\n"
+ " IAR_ARM_CM55_SECURE - Compiller: IAR Target: ARM Cortex-M55 secure\n"
+ " IAR_ARM_CM55_NTZ_NONSECURE - Compiller: IAR Target: ARM Cortex-M55 non-trustzone non-secure\n"
+ " IAR_ARM_CM85_NONSECURE - Compiller: IAR Target: ARM Cortex-M85 non-secure\n"
+ " IAR_ARM_CM85_SECURE - Compiller: IAR Target: ARM Cortex-M85 secure\n"
+ " IAR_ARM_CM85_NTZ_NONSECURE - Compiller: IAR Target: ARM Cortex-M85 non-trustzone non-secure\n"
+ " IAR_ARM_CRX_NOGIC - Compiller: IAR Target: ARM Cortex-Rx no GIC\n"
+ " IAR_ATMEGA323 - Compiller: IAR Target: ATMega323\n"
+ " IAR_ATMEL_SAM7S64 - Compiller: IAR Target: Atmel SAM7S64\n"
+ " IAR_ATMEL_SAM9XE - Compiller: IAR Target: Atmel SAM9XE\n"
+ " IAR_AVR_AVRDX - Compiller: IAR Target: AVRDx\n"
+ " IAR_AVR_MEGA0 - Compiller: IAR Target: AVR Mega0\n"
+ " IAR_AVR32_UC3 - Compiller: IAR Target: AVR32 UC3\n"
+ " IAR_LPC2000 - Compiller: IAR Target: LPC2000\n"
+ " IAR_MSP430 - Compiller: IAR Target: MSP430\n"
+ " IAR_MSP430X - Compiller: IAR Target: MSP430X\n"
+ " IAR_RISC_V - Compiller: IAR Target: RISC-V\n"
+ " IAR_RL78 - Compiller: IAR Target: Renesas RL78\n"
+ " IAR_RX100 - Compiller: IAR Target: Renesas RX100\n"
+ " IAR_RX600 - Compiller: IAR Target: Renesas RX600\n"
+ " IAR_RX700_V3_DPFPU - Compiller: IAR Target: Renesas RX700 v3 with DPFPU\n"
+ " IAR_RX_V2 - Compiller: IAR Target: Renesas RX v2\n"
+ " IAR_STR71X - Compiller: IAR Target: STR71x\n"
+ " IAR_STR75X - Compiller: IAR Target: STR75x\n"
+ " IAR_STR91X - Compiller: IAR Target: STR91x\n"
+ " IAR_V850ES_FX3 - Compiller: IAR Target: Renesas V850ES/Fx3\n"
+ " IAR_V850ES_HX3 - Compiller: IAR Target: Renesas V850ES/Hx3\n"
+ " MIKROC_ARM_CM4F - Compiller: MikroC Target: ARM Cortex-M4 with FPU\n"
+ " MPLAB_PIC18F - Compiller: MPLAB Target: PIC18F\n"
+ " MPLAB_PIC24 - Compiller: MPLAB Target: PIC24\n"
+ " MPLAB_PIC32MEC14XX - Compiller: MPLAB Target: PIC32MEC14xx\n"
+ " MPLAB_PIC32MX - Compiller: MPLAB Target: PIC32MX\n"
+ " MPLAB_PIC32MZ - Compiller: MPLAB Target: PIC32MZ\n"
+ " MSVC_MINGW - Compiller: MSVC or MinGW Target: x86\n"
+ " OWATCOM_16BIT_DOS_FLSH186 - Compiller: Open Watcom Target: 16 bit DOS Flsh186\n"
+ " OWATCOM_16BIT_DOS_PC - Compiller: Open Watcom Target: 16 bit DOS PC\n"
+ " PARADIGM_TERN_EE_LARGE - Compiller: Paradigm Target: Tern EE large\n"
+ " PARADIGM_TERN_EE_SMALL - Compiller: Paradigm Target: Tern EE small\n"
+ " RENESAS_RX100 - Compiller: Renesas Target: RX100\n"
+ " RENESAS_RX200 - Compiller: Renesas Target: RX200\n"
+ " RENESAS_RX600 - Compiller: Renesas Target: RX600\n"
+ " RENESAS_RX600_V2 - Compiller: Renesas Target: RX600 v2\n"
+ " RENESAS_RX700_V3_DPFPU - Compiller: Renesas Target: RX700 v3 with DPFPU\n"
+ " RENESAS_SH2A_FPU - Compiller: Renesas Target: SH2A with FPU\n"
+ " ROWLEY_MSP430F449 - Compiller: Rowley Target: MSP430F449\n"
+ " RVDS_ARM_CA9 - Compiller: RVDS Target: ARM Cortex-A9\n"
+ " RVDS_ARM_CM0 - Compiller: RVDS Target: ARM Cortex-M0\n"
+ " RVDS_ARM_CM3 - Compiller: RVDS Target: ARM Cortex-M3\n"
+ " RVDS_ARM_CM4_MPU - Compiller: RVDS Target: ARM Cortex-M4 with MPU\n"
+ " RVDS_ARM_CM4F - Compiller: RVDS Target: ARM Cortex-M4 with FPU\n"
+ " RVDS_ARM_CM7 - Compiller: RVDS Target: ARM Cortex-M7\n"
+ " RVDS_ARM7_LPC21XX - Compiller: RVDS Target: ARM7 LPC21xx\n"
+ " SDCC_CYGNAL - Compiller: SDCC Target: Cygnal\n"
+ " SOFTUNE_MB91460 - Compiller: Softune Target: MB91460\n"
+ " SOFTUNE_MB96340 - Compiller: Softune Target: MB96340\n"
+ " TASKING_ARM_CM4F - Compiller: Tasking Target: ARM Cortex-M4 with FPU\n"
+ " CDK_THEAD_CK802 - Compiller: CDK Target: T-head CK802\n"
+ " XCC_XTENSA - Compiller: XCC Target: Xtensa\n"
+ " WIZC_PIC18 - Compiller: WizC Target: PIC18")
+endif()
+
+add_subdirectory(portable)
+
+add_library(freertos_kernel STATIC
+ croutine.c
+ event_groups.c
+ list.c
+ queue.c
+ stream_buffer.c
+ tasks.c
+ timers.c
+
+ # If FREERTOS_HEAP is digit between 1 .. 5 - it is heap number, otherwise - it is path to custom heap source file
+ $>,${FREERTOS_HEAP},portable/MemMang/heap_${FREERTOS_HEAP}.c>
+)
+
+target_include_directories(freertos_kernel
+ PUBLIC
+ include
+ ${FREERTOS_CONFIG_FILE_DIRECTORY}
+)
+
+target_link_libraries(freertos_kernel freertos_kernel_port)
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Inc/FreeRTOSConfig.h b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Inc/FreeRTOSConfig.h
new file mode 100644
index 0000000..15e22ca
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Inc/FreeRTOSConfig.h
@@ -0,0 +1,140 @@
+/* USER CODE BEGIN Header */
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Portion Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Portion Copyright (C) 2019 StMicroelectronics, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+/* USER CODE END Header */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * These parameters and more are described within the 'configuration' section of the
+ * FreeRTOS API documentation available on the FreeRTOS.org web site.
+ *
+ * See http://www.freertos.org/a00110.html
+ *----------------------------------------------------------*/
+
+/* USER CODE BEGIN Includes */
+/* Section where include file can be added */
+/* USER CODE END Includes */
+
+/* Ensure definitions are only used by the compiler, and not by the assembler. */
+#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
+ #include
+ extern uint32_t SystemCoreClock;
+ void xPortSysTickHandler(void);
+#endif
+#define configENABLE_FPU 0
+#define configENABLE_MPU 0
+
+#define configUSE_PREEMPTION 1
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configCPU_CLOCK_HZ ( SystemCoreClock )
+#define configTICK_RATE_HZ ((TickType_t)1000)
+#define configMAX_PRIORITIES ( 7 )
+#define configMINIMAL_STACK_SIZE ((uint16_t)128)
+#define configTOTAL_HEAP_SIZE ((size_t)15360)
+#define configMAX_TASK_NAME_LEN ( 16 )
+#define configUSE_16_BIT_TICKS 0
+#define configUSE_MUTEXES 1
+#define configQUEUE_REGISTRY_SIZE 8
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */
+/* Defaults to size_t for backward compatibility, but can be changed
+ if lengths will always be less than the number of bytes in a size_t. */
+#define configMESSAGE_BUFFER_LENGTH_TYPE size_t
+/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 0
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 0
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1
+
+/* Cortex-M specific definitions. */
+#ifdef __NVIC_PRIO_BITS
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+ #define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+ #define configPRIO_BITS 4
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
+
+/* Interrupt priorities used by the kernel port layer itself. These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* Normal assert() semantics without relying on the provision of an assert.h
+header file. */
+/* USER CODE BEGIN 1 */
+#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );}
+/* USER CODE END 1 */
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+
+/* IMPORTANT: This define is commented when used with STM32Cube firmware, when the timebase source is SysTick,
+ to prevent overwriting SysTick_Handler defined within STM32Cube HAL */
+
+/* #define xPortSysTickHandler SysTick_Handler */
+
+/* USER CODE BEGIN Defines */
+/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */
+/* USER CODE END Defines */
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Inc/app.h b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Inc/app.h
new file mode 100644
index 0000000..3e91442
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Inc/app.h
@@ -0,0 +1,24 @@
+/**
+ ******************************************************************************
+ * @file app.h
+ * @brief This file contains the headers of app.c.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+#ifndef __APP_H
+#define __APP_H
+
+void SystemClock_Config(void);
+
+
+#endif
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Inc/main.h b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Inc/main.h
new file mode 100644
index 0000000..be60ecc
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Inc/main.h
@@ -0,0 +1,83 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.h
+ * @brief : Header for main.c file.
+ * This file contains the common defines of the application.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define B1_Pin GPIO_PIN_13
+#define B1_GPIO_Port GPIOC
+#define USART_TX_Pin GPIO_PIN_2
+#define USART_TX_GPIO_Port GPIOA
+#define USART_RX_Pin GPIO_PIN_3
+#define USART_RX_GPIO_Port GPIOA
+#define LD2_Pin GPIO_PIN_5
+#define LD2_GPIO_Port GPIOA
+#define TMS_Pin GPIO_PIN_13
+#define TMS_GPIO_Port GPIOA
+#define TCK_Pin GPIO_PIN_14
+#define TCK_GPIO_Port GPIOA
+#define SWO_Pin GPIO_PIN_3
+#define SWO_GPIO_Port GPIOB
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Inc/stm32f4xx_hal_conf.h b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Inc/stm32f4xx_hal_conf.h
new file mode 100644
index 0000000..cfeb30f
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Inc/stm32f4xx_hal_conf.h
@@ -0,0 +1,490 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_conf_template.h
+ * @author MCD Application Team
+ * @brief HAL configuration template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32f4xx_hal_conf.h.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+
+ /* #define HAL_CRYP_MODULE_ENABLED */
+/* #define HAL_ADC_MODULE_ENABLED */
+/* #define HAL_CAN_MODULE_ENABLED */
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
+/* #define HAL_DAC_MODULE_ENABLED */
+/* #define HAL_DCMI_MODULE_ENABLED */
+/* #define HAL_DMA2D_MODULE_ENABLED */
+/* #define HAL_ETH_MODULE_ENABLED */
+/* #define HAL_NAND_MODULE_ENABLED */
+/* #define HAL_NOR_MODULE_ENABLED */
+/* #define HAL_PCCARD_MODULE_ENABLED */
+/* #define HAL_SRAM_MODULE_ENABLED */
+/* #define HAL_SDRAM_MODULE_ENABLED */
+/* #define HAL_HASH_MODULE_ENABLED */
+/* #define HAL_I2C_MODULE_ENABLED */
+/* #define HAL_I2S_MODULE_ENABLED */
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_LTDC_MODULE_ENABLED */
+/* #define HAL_RNG_MODULE_ENABLED */
+/* #define HAL_RTC_MODULE_ENABLED */
+/* #define HAL_SAI_MODULE_ENABLED */
+/* #define HAL_SD_MODULE_ENABLED */
+/* #define HAL_MMC_MODULE_ENABLED */
+/* #define HAL_SPI_MODULE_ENABLED */
+/* #define HAL_TIM_MODULE_ENABLED */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_SMBUS_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+/* #define HAL_PCD_MODULE_ENABLED */
+/* #define HAL_HCD_MODULE_ENABLED */
+/* #define HAL_DSI_MODULE_ENABLED */
+/* #define HAL_QSPI_MODULE_ENABLED */
+/* #define HAL_QSPI_MODULE_ENABLED */
+/* #define HAL_CEC_MODULE_ENABLED */
+/* #define HAL_FMPI2C_MODULE_ENABLED */
+/* #define HAL_FMPSMBUS_MODULE_ENABLED */
+/* #define HAL_SPDIFRX_MODULE_ENABLED */
+/* #define HAL_DFSDM_MODULE_ENABLED */
+/* #define HAL_LPTIM_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature.*/
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+ #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External audio frequency in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE 3300U /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority */
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE 1U
+#define INSTRUCTION_CACHE_ENABLE 1U
+#define DATA_CACHE_ENABLE 1U
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
+#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
+#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
+#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
+#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
+#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
+#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
+#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
+#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
+#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
+#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
+#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
+#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */
+#define USE_HAL_FMPSMBUS_REGISTER_CALLBACKS 0U /* FMPSMBUS register callback disabled */
+#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
+#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
+#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
+#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
+#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
+#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
+#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
+#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
+#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
+#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
+#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
+#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
+#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
+#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
+#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
+#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1U */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0 2U
+#define MAC_ADDR1 0U
+#define MAC_ADDR2 0U
+#define MAC_ADDR3 0U
+#define MAC_ADDR4 0U
+#define MAC_ADDR5 0U
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848_PHY_ADDRESS Address*/
+#define DP83848_PHY_ADDRESS 0x01U
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY 0x000000FFU
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY 0x00000FFFU
+
+#define PHY_READ_TO 0x0000FFFFU
+#define PHY_WRITE_TO 0x0000FFFFU
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
+
+/* Section 4: Extended PHY Registers */
+#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */
+
+#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC 0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+ #include "stm32f4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+ #include "stm32f4xx_hal_can_legacy.h"
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f4xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpi2c.h"
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+
+#ifdef HAL_FMPSMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpsmbus.h"
+#endif /* HAL_FMPSMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32f4xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32f4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f4xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Inc/stm32f4xx_it.h b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Inc/stm32f4xx_it.h
new file mode 100644
index 0000000..274aab4
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Inc/stm32f4xx_it.h
@@ -0,0 +1,65 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32f4xx_it.h
+ * @brief This file contains the headers of the interrupt handlers.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_IT_H
+#define __STM32F4xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void DebugMon_Handler(void);
+void SysTick_Handler(void);
+void Error_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_IT_H */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/app.c b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/app.c
new file mode 100644
index 0000000..8d5262c
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/app.c
@@ -0,0 +1,78 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : app.c
+ * @brief : application calls file
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "app.h"
+#include "cmsis_os.h"
+#include "main.h"
+
+void SystemClock_Config(void);
+
+
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16;
+ RCC_OscInitStruct.PLL.PLLN = 336;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+
+
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/freertos.c b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/freertos.c
new file mode 100644
index 0000000..47b8ad4
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/freertos.c
@@ -0,0 +1,74 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * File Name : freertos.c
+ * Description : Code for freertos applications
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "FreeRTOS.h"
+#include "task.h"
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN Variables */
+
+/* USER CODE END Variables */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN FunctionPrototypes */
+
+/* USER CODE END FunctionPrototypes */
+
+/* GetIdleTaskMemory prototype (linked to static allocation support) */
+void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize );
+
+/* USER CODE BEGIN GET_IDLE_TASK_MEMORY */
+static StaticTask_t xIdleTaskTCBBuffer;
+static StackType_t xIdleStack[configMINIMAL_STACK_SIZE];
+
+void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
+{
+ *ppxIdleTaskTCBBuffer = &xIdleTaskTCBBuffer;
+ *ppxIdleTaskStackBuffer = &xIdleStack[0];
+ *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+ /* place for user code */
+}
+/* USER CODE END GET_IDLE_TASK_MEMORY */
+
+/* Private application code --------------------------------------------------*/
+/* USER CODE BEGIN Application */
+
+/* USER CODE END Application */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/main.c b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/main.c
new file mode 100644
index 0000000..3af6d86
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/main.c
@@ -0,0 +1,168 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "app.h"
+#include "cmsis_os.h"
+osThreadId defaultTaskHandle;
+osThreadId BlinkLEDHandle;
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+void StartDefaultTask(void const * argument);
+void StartTask02(void const * argument);
+void blinkaled(void);
+static void MX_GPIO_Init(void);
+
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ /* MCU Configuration--------------------------------------------------------*/
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+ /* Configure the system clock */
+ SystemClock_Config();
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+
+ /* Create the thread(s) */
+ /* definition and creation of defaultTask */
+ osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 128);
+ defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
+
+ /* definition and creation of BlinkLED */
+ osThreadDef(blinkaled, StartTask02, osPriorityIdle, 0, 128);
+ BlinkLEDHandle = osThreadCreate(osThread(blinkaled), NULL);
+
+ /* Start scheduler */
+ osKernelStart();
+
+ /* We should never get here as control is now taken by the scheduler */
+ /* Infinite loop */
+
+ while (1)
+ {
+ }
+
+}
+
+/**
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+
+static void MX_GPIO_Init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+ /* GPIO Ports Clock Enable */
+
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin : LD2_Pin */
+ GPIO_InitStruct.Pin = LD2_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+
+
+/**
+ * @brief Function implementing the defaultTask thread.
+ * @param argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void const * argument)
+{
+ /* USER CODE BEGIN 5 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ }
+ /* USER CODE END 5 */
+}
+
+
+
+/**
+* @brief Function implementing the blinkaled thread.
+* @param argument: Not used
+* @retval None
+*/
+/* USER CODE END Header_StartTask02 */
+void StartTask02(void const * argument)
+{
+ /* USER CODE BEGIN StartTask02 */
+ /* Infinite loop */
+ for(;;)
+ {
+ blinkaled();
+ }
+ /* USER CODE END StartTask02 */
+}
+
+/*
+ * Function: blinkled
+ * Blinks an LED connected to GPIOA Pin 5 by setting it high for 1 second and then low for 1 second.
+ * Parameters: None
+ * Returns: None
+ */
+void blinkaled(void)
+{
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET);
+ osDelay(1000);
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET);
+ osDelay(1000);
+}
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/stm32f4xx_hal_msp.c b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/stm32f4xx_hal_msp.c
new file mode 100644
index 0000000..7f7beff
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/stm32f4xx_hal_msp.c
@@ -0,0 +1,148 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_msp.c
+ * @brief This file provides code for the MSP Initialization
+ * and de-Initialization codes.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+ * Initializes the Global MSP.
+ */
+void HAL_MspInit(void)
+{
+ /* USER CODE BEGIN MspInit 0 */
+
+ /* USER CODE END MspInit 0 */
+
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* System interrupt init*/
+ /* PendSV_IRQn interrupt configuration */
+ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
+
+ /* USER CODE BEGIN MspInit 1 */
+
+ /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ if(huart->Instance==USART2)
+ {
+ /* USER CODE BEGIN USART2_MspInit 0 */
+
+ /* USER CODE END USART2_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_USART2_CLK_ENABLE();
+
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ /**USART2 GPIO Configuration
+ PA2 ------> USART2_TX
+ PA3 ------> USART2_RX
+ */
+ GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN USART2_MspInit 1 */
+
+ /* USER CODE END USART2_MspInit 1 */
+ }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+ if(huart->Instance==USART2)
+ {
+ /* USER CODE BEGIN USART2_MspDeInit 0 */
+
+ /* USER CODE END USART2_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_USART2_CLK_DISABLE();
+
+ /**USART2 GPIO Configuration
+ PA2 ------> USART2_TX
+ PA3 ------> USART2_RX
+ */
+ HAL_GPIO_DeInit(GPIOA, USART_TX_Pin|USART_RX_Pin);
+
+ /* USER CODE BEGIN USART2_MspDeInit 1 */
+
+ /* USER CODE END USART2_MspDeInit 1 */
+ }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/stm32f4xx_it.c b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/stm32f4xx_it.c
new file mode 100644
index 0000000..0d3897d
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/stm32f4xx_it.c
@@ -0,0 +1,200 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32f4xx_it.c
+ * @brief Interrupt Service Routines.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32f4xx_it.h"
+#include "FreeRTOS.h"
+#include "task.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/* Cortex-M4 Processor Interruption and Exception Handlers */
+/******************************************************************************/
+/**
+ * @brief This function handles Non maskable interrupt.
+ */
+void NMI_Handler(void)
+{
+ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+ /* USER CODE END NonMaskableInt_IRQn 0 */
+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+ while (1)
+ {
+ }
+ /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Hard fault interrupt.
+ */
+void HardFault_Handler(void)
+{
+ /* USER CODE BEGIN HardFault_IRQn 0 */
+
+ /* USER CODE END HardFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+ /* USER CODE END W1_HardFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Memory management fault.
+ */
+void MemManage_Handler(void)
+{
+ /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+ /* USER CODE END MemoryManagement_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+ /* USER CODE END W1_MemoryManagement_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Pre-fetch fault, memory access fault.
+ */
+void BusFault_Handler(void)
+{
+ /* USER CODE BEGIN BusFault_IRQn 0 */
+
+ /* USER CODE END BusFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+ /* USER CODE END W1_BusFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Undefined instruction or illegal state.
+ */
+void UsageFault_Handler(void)
+{
+ /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+ /* USER CODE END UsageFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+ /* USER CODE END W1_UsageFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Debug monitor.
+ */
+void DebugMon_Handler(void)
+{
+ /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+ /* USER CODE END DebugMonitor_IRQn 0 */
+ /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+ /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+
+
+/**
+ * @brief This function handles System tick timer.
+ */
+void SysTick_Handler(void)
+{
+ /* USER CODE BEGIN SysTick_IRQn 0 */
+
+ /* USER CODE END SysTick_IRQn 0 */
+ HAL_IncTick();
+#if (INCLUDE_xTaskGetSchedulerState == 1 )
+ if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED)
+ {
+#endif /* INCLUDE_xTaskGetSchedulerState */
+ xPortSysTickHandler();
+#if (INCLUDE_xTaskGetSchedulerState == 1 )
+ }
+#endif /* INCLUDE_xTaskGetSchedulerState */
+ /* USER CODE BEGIN SysTick_IRQn 1 */
+
+ /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32F4xx Peripheral Interrupt Handlers */
+/* Add here the Interrupt Handlers for the used peripherals. */
+/* For the available peripheral interrupt handler names, */
+/* please refer to the startup file (startup_stm32f4xx.s). */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/syscalls.c b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/syscalls.c
new file mode 100644
index 0000000..f4278b7
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/syscalls.c
@@ -0,0 +1,176 @@
+/**
+ ******************************************************************************
+ * @file syscalls.c
+ * @author Auto-generated by STM32CubeIDE
+ * @brief STM32CubeIDE Minimal System calls file
+ *
+ * For more information about which c-functions
+ * need which of these lowlevel functions
+ * please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2020-2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+
+/* Variables */
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+ return 1;
+}
+
+int _kill(int pid, int sig)
+{
+ (void)pid;
+ (void)sig;
+ errno = EINVAL;
+ return -1;
+}
+
+void _exit (int status)
+{
+ _kill(status, -1);
+ while (1) {} /* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+ (void)file;
+ int DataIdx;
+
+ for (DataIdx = 0; DataIdx < len; DataIdx++)
+ {
+ *ptr++ = __io_getchar();
+ }
+
+ return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+ (void)file;
+ int DataIdx;
+
+ for (DataIdx = 0; DataIdx < len; DataIdx++)
+ {
+ __io_putchar(*ptr++);
+ }
+ return len;
+}
+
+int _close(int file)
+{
+ (void)file;
+ return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+ (void)file;
+ st->st_mode = S_IFCHR;
+ return 0;
+}
+
+int _isatty(int file)
+{
+ (void)file;
+ return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+ (void)file;
+ (void)ptr;
+ (void)dir;
+ return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+ (void)path;
+ (void)flags;
+ /* Pretend like we always fail */
+ return -1;
+}
+
+int _wait(int *status)
+{
+ (void)status;
+ errno = ECHILD;
+ return -1;
+}
+
+int _unlink(char *name)
+{
+ (void)name;
+ errno = ENOENT;
+ return -1;
+}
+
+int _times(struct tms *buf)
+{
+ (void)buf;
+ return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+ (void)file;
+ st->st_mode = S_IFCHR;
+ return 0;
+}
+
+int _link(char *old, char *new)
+{
+ (void)old;
+ (void)new;
+ errno = EMLINK;
+ return -1;
+}
+
+int _fork(void)
+{
+ errno = EAGAIN;
+ return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+ (void)name;
+ (void)argv;
+ (void)env;
+ errno = ENOMEM;
+ return -1;
+}
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/sysmem.c b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/sysmem.c
new file mode 100644
index 0000000..54081ac
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/sysmem.c
@@ -0,0 +1,79 @@
+/**
+ ******************************************************************************
+ * @file sysmem.c
+ * @author Generated by STM32CubeIDE
+ * @brief STM32CubeIDE System Memory calls file
+ *
+ * For more information about which C functions
+ * need which of these lowlevel functions
+ * please consult the newlib libc manual
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include
+#include
+
+/**
+ * Pointer to the current high watermark of the heap usage
+ */
+static uint8_t *__sbrk_heap_end = NULL;
+
+/**
+ * @brief _sbrk() allocates memory to the newlib heap and is used by malloc
+ * and others from the C library
+ *
+ * @verbatim
+ * ############################################################################
+ * # .data # .bss # newlib heap # MSP stack #
+ * # # # # Reserved by _Min_Stack_Size #
+ * ############################################################################
+ * ^-- RAM start ^-- _end _estack, RAM end --^
+ * @endverbatim
+ *
+ * This implementation starts allocating at the '_end' linker symbol
+ * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack
+ * The implementation considers '_estack' linker symbol to be RAM end
+ * NOTE: If the MSP stack, at any point during execution, grows larger than the
+ * reserved size, please increase the '_Min_Stack_Size'.
+ *
+ * @param incr Memory size
+ * @return Pointer to allocated memory
+ */
+void *_sbrk(ptrdiff_t incr)
+{
+ extern uint8_t _end; /* Symbol defined in the linker script */
+ extern uint8_t _estack; /* Symbol defined in the linker script */
+ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
+ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
+ const uint8_t *max_heap = (uint8_t *)stack_limit;
+ uint8_t *prev_heap_end;
+
+ /* Initialize heap end at first call */
+ if (NULL == __sbrk_heap_end)
+ {
+ __sbrk_heap_end = &_end;
+ }
+
+ /* Protect heap from growing into the reserved MSP stack */
+ if (__sbrk_heap_end + incr > max_heap)
+ {
+ errno = ENOMEM;
+ return (void *)-1;
+ }
+
+ prev_heap_end = __sbrk_heap_end;
+ __sbrk_heap_end += incr;
+
+ return (void *)prev_heap_end;
+}
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/system_stm32f4xx.c b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/system_stm32f4xx.c
new file mode 100644
index 0000000..3bd40f7
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Src/system_stm32f4xx.c
@@ -0,0 +1,747 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f4xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Includes
+ * @{
+ */
+
+
+#include "stm32f4xx.h"
+
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
+ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+ STM32F412Zx || STM32F412Vx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/* #define DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
+ STM32F479xx */
+
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in Flash or Sram, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in Sram else user remap will be done in Flash. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+uint32_t SystemCoreClock = 16000000;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ #endif
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
+ * depends on the application requirements), user has to ensure that HSE_VALUE
+ * is same as the real frequency of the crystal used. Otherwise, this function
+ * may have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock source */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock source */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock source */
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+ SYSCLK = PLL_VCO / PLL_P
+ */
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+
+ if (pllsource != 0)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+ SystemCoreClock = pllvco/pllp;
+ break;
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK frequency --------------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK frequency */
+ SystemCoreClock >>= tmp;
+}
+
+#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f4xx.s before jump to main.
+ * This function configures the external memories (SRAM/SDRAM)
+ * This SRAM/SDRAM will be used as program data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+ __IO uint32_t tmp = 0x00;
+
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
+ register __IO uint32_t index;
+
+ /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
+ RCC->AHB1ENR |= 0x000001F8;
+
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x00CCC0CC;
+ GPIOD->AFR[1] = 0xCCCCCCCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAAAA0A8A;
+ /* Configure PDx pins speed to 100 MHz */
+ GPIOD->OSPEEDR = 0xFFFF0FCF;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00CC0CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA828A;
+ /* Configure PEx pins speed to 100 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC3CF;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0xCCCCCCCC;
+ GPIOF->AFR[1] = 0xCCCCCCCC;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA800AAA;
+ /* Configure PFx pins speed to 50 MHz */
+ GPIOF->OSPEEDR = 0xAA800AAA;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0xCCCCCCCC;
+ GPIOG->AFR[1] = 0xCCCCCCCC;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0xAAAAAAAA;
+ /* Configure PGx pins speed to 50 MHz */
+ GPIOG->OSPEEDR = 0xAAAAAAAA;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+ /* Connect PHx pins to FMC Alternate function */
+ GPIOH->AFR[0] = 0x00C0CC00;
+ GPIOH->AFR[1] = 0xCCCCCCCC;
+ /* Configure PHx pins in Alternate function mode */
+ GPIOH->MODER = 0xAAAA08A0;
+ /* Configure PHx pins speed to 50 MHz */
+ GPIOH->OSPEEDR = 0xAAAA08A0;
+ /* Configure PHx pins Output type to push-pull */
+ GPIOH->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PHx pins */
+ GPIOH->PUPDR = 0x00000000;
+
+ /* Connect PIx pins to FMC Alternate function */
+ GPIOI->AFR[0] = 0xCCCCCCCC;
+ GPIOI->AFR[1] = 0x00000CC0;
+ /* Configure PIx pins in Alternate function mode */
+ GPIOI->MODER = 0x0028AAAA;
+ /* Configure PIx pins speed to 50 MHz */
+ GPIOI->OSPEEDR = 0x0028AAAA;
+ /* Configure PIx pins Output type to push-pull */
+ GPIOI->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PIx pins */
+ GPIOI->PUPDR = 0x00000000;
+
+/*-- FMC Configuration -------------------------------------------------------*/
+ /* Enable the FMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+ FMC_Bank5_6->SDCR[0] = 0x000019E4;
+ FMC_Bank5_6->SDTR[0] = 0x01115351;
+
+ /* SDRAM initialization sequence */
+ /* Clock enable command */
+ FMC_Bank5_6->SDCMR = 0x00000011;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Delay */
+ for (index = 0; index<1000; index++);
+
+ /* PALL command */
+ FMC_Bank5_6->SDCMR = 0x00000012;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Auto refresh command */
+ FMC_Bank5_6->SDCMR = 0x00000073;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* MRD register program */
+ FMC_Bank5_6->SDCMR = 0x00046014;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Set refresh count */
+ tmpreg = FMC_Bank5_6->SDRTR;
+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+
+ /* Disable write protection */
+ tmpreg = FMC_Bank5_6->SDCR[0];
+ FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1->BTCR[2] = 0x00001011;
+ FMC_Bank1->BTCR[3] = 0x00000201;
+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#if defined(STM32F469xx) || defined(STM32F479xx)
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1->BTCR[2] = 0x00001091;
+ FMC_Bank1->BTCR[3] = 0x00110212;
+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F469xx || STM32F479xx */
+
+ (void)(tmp);
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f4xx.s before jump to main.
+ * This function configures the external memories (SRAM/SDRAM)
+ * This SRAM/SDRAM will be used as program data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+ __IO uint32_t tmp = 0x00;
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined (DATA_IN_ExtSDRAM)
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
+ register __IO uint32_t index;
+
+#if defined(STM32F446xx)
+ /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
+ clock */
+ RCC->AHB1ENR |= 0x0000007D;
+#else
+ /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
+ clock */
+ RCC->AHB1ENR |= 0x000001F8;
+#endif /* STM32F446xx */
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
+
+#if defined(STM32F446xx)
+ /* Connect PAx pins to FMC Alternate function */
+ GPIOA->AFR[0] |= 0xC0000000;
+ GPIOA->AFR[1] |= 0x00000000;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOA->MODER |= 0x00008000;
+ /* Configure PDx pins speed to 50 MHz */
+ GPIOA->OSPEEDR |= 0x00008000;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOA->OTYPER |= 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOA->PUPDR |= 0x00000000;
+
+ /* Connect PCx pins to FMC Alternate function */
+ GPIOC->AFR[0] |= 0x00CC0000;
+ GPIOC->AFR[1] |= 0x00000000;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOC->MODER |= 0x00000A00;
+ /* Configure PDx pins speed to 50 MHz */
+ GPIOC->OSPEEDR |= 0x00000A00;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOC->OTYPER |= 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOC->PUPDR |= 0x00000000;
+#endif /* STM32F446xx */
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x000000CC;
+ GPIOD->AFR[1] = 0xCC000CCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xA02A000A;
+ /* Configure PDx pins speed to 50 MHz */
+ GPIOD->OSPEEDR = 0xA02A000A;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00000CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA800A;
+ /* Configure PEx pins speed to 50 MHz */
+ GPIOE->OSPEEDR = 0xAAAA800A;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0xCCCCCCCC;
+ GPIOF->AFR[1] = 0xCCCCCCCC;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA800AAA;
+ /* Configure PFx pins speed to 50 MHz */
+ GPIOF->OSPEEDR = 0xAA800AAA;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0xCCCCCCCC;
+ GPIOG->AFR[1] = 0xCCCCCCCC;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0xAAAAAAAA;
+ /* Configure PGx pins speed to 50 MHz */
+ GPIOG->OSPEEDR = 0xAAAAAAAA;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx)
+ /* Connect PHx pins to FMC Alternate function */
+ GPIOH->AFR[0] = 0x00C0CC00;
+ GPIOH->AFR[1] = 0xCCCCCCCC;
+ /* Configure PHx pins in Alternate function mode */
+ GPIOH->MODER = 0xAAAA08A0;
+ /* Configure PHx pins speed to 50 MHz */
+ GPIOH->OSPEEDR = 0xAAAA08A0;
+ /* Configure PHx pins Output type to push-pull */
+ GPIOH->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PHx pins */
+ GPIOH->PUPDR = 0x00000000;
+
+ /* Connect PIx pins to FMC Alternate function */
+ GPIOI->AFR[0] = 0xCCCCCCCC;
+ GPIOI->AFR[1] = 0x00000CC0;
+ /* Configure PIx pins in Alternate function mode */
+ GPIOI->MODER = 0x0028AAAA;
+ /* Configure PIx pins speed to 50 MHz */
+ GPIOI->OSPEEDR = 0x0028AAAA;
+ /* Configure PIx pins Output type to push-pull */
+ GPIOI->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PIx pins */
+ GPIOI->PUPDR = 0x00000000;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+/*-- FMC Configuration -------------------------------------------------------*/
+ /* Enable the FMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+ /* Configure and enable SDRAM bank1 */
+#if defined(STM32F446xx)
+ FMC_Bank5_6->SDCR[0] = 0x00001954;
+#else
+ FMC_Bank5_6->SDCR[0] = 0x000019E4;
+#endif /* STM32F446xx */
+ FMC_Bank5_6->SDTR[0] = 0x01115351;
+
+ /* SDRAM initialization sequence */
+ /* Clock enable command */
+ FMC_Bank5_6->SDCMR = 0x00000011;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Delay */
+ for (index = 0; index<1000; index++);
+
+ /* PALL command */
+ FMC_Bank5_6->SDCMR = 0x00000012;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Auto refresh command */
+#if defined(STM32F446xx)
+ FMC_Bank5_6->SDCMR = 0x000000F3;
+#else
+ FMC_Bank5_6->SDCMR = 0x00000073;
+#endif /* STM32F446xx */
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* MRD register program */
+#if defined(STM32F446xx)
+ FMC_Bank5_6->SDCMR = 0x00044014;
+#else
+ FMC_Bank5_6->SDCMR = 0x00046014;
+#endif /* STM32F446xx */
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Set refresh count */
+ tmpreg = FMC_Bank5_6->SDRTR;
+#if defined(STM32F446xx)
+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
+#else
+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+#endif /* STM32F446xx */
+
+ /* Disable write protection */
+ tmpreg = FMC_Bank5_6->SDCR[0];
+ FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+#endif /* DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
+ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
+
+#if defined(DATA_IN_ExtSRAM)
+/*-- GPIOs Configuration -----------------------------------------------------*/
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+ RCC->AHB1ENR |= 0x00000078;
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x00CCC0CC;
+ GPIOD->AFR[1] = 0xCCCCCCCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAAAA0A8A;
+ /* Configure PDx pins speed to 100 MHz */
+ GPIOD->OSPEEDR = 0xFFFF0FCF;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00CC0CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA828A;
+ /* Configure PEx pins speed to 100 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC3CF;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0x00CCCCCC;
+ GPIOF->AFR[1] = 0xCCCC0000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA000AAA;
+ /* Configure PFx pins speed to 100 MHz */
+ GPIOF->OSPEEDR = 0xFF000FFF;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0x00CCCCCC;
+ GPIOG->AFR[1] = 0x000000C0;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0x00085AAA;
+ /* Configure PGx pins speed to 100 MHz */
+ GPIOG->OSPEEDR = 0x000CAFFF;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+/*-- FMC/FSMC Configuration --------------------------------------------------*/
+ /* Enable the FMC/FSMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1->BTCR[2] = 0x00001011;
+ FMC_Bank1->BTCR[3] = 0x00000201;
+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#if defined(STM32F469xx) || defined(STM32F479xx)
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1->BTCR[2] = 0x00001091;
+ FMC_Bank1->BTCR[3] = 0x00110212;
+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F469xx || STM32F479xx */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+ || defined(STM32F412Zx) || defined(STM32F412Vx)
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
+ /* Configure and enable Bank1_SRAM2 */
+ FSMC_Bank1->BTCR[2] = 0x00001011;
+ FSMC_Bank1->BTCR[3] = 0x00000201;
+ FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
+
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
+ (void)(tmp);
+}
+#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Startup/startup_stm32f446retx.s b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Startup/startup_stm32f446retx.s
new file mode 100644
index 0000000..9ce3d8d
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Core/Startup/startup_stm32f446retx.s
@@ -0,0 +1,535 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f446xx.s
+ * @author MCD Application Team
+ * @brief STM32F446xx Devices vector table for GCC based toolchains.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_IRQHandler /* PVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word CAN1_TX_IRQHandler /* CAN1 TX */
+ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
+ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
+ .word CAN1_SCE_IRQHandler /* CAN1 SCE */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
+ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
+ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDIO_IRQHandler /* SDIO */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word CAN2_TX_IRQHandler /* CAN2 TX */
+ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
+ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
+ .word CAN2_SCE_IRQHandler /* CAN2 SCE */
+ .word OTG_FS_IRQHandler /* USB OTG FS */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_IRQHandler /* DCMI */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word FPU_IRQHandler /* FPU */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word SAI2_IRQHandler /* SAI2 */
+ .word QUADSPI_IRQHandler /* QuadSPI */
+ .word CEC_IRQHandler /* CEC */
+ .word SPDIF_RX_IRQHandler /* SPDIF RX */
+ .word FMPI2C1_EV_IRQHandler /* FMPI2C 1 Event */
+ .word FMPI2C1_ER_IRQHandler /* FMPI2C 1 Error */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak CAN1_TX_IRQHandler
+ .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+ .weak CAN1_RX0_IRQHandler
+ .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM9_IRQHandler
+ .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM10_IRQHandler
+ .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM11_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak OTG_FS_WKUP_IRQHandler
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDIO_IRQHandler
+ .thumb_set SDIO_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak CAN2_TX_IRQHandler
+ .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+ .weak CAN2_RX0_IRQHandler
+ .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+
+ .weak CAN2_RX1_IRQHandler
+ .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+
+ .weak CAN2_SCE_IRQHandler
+ .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_IRQHandler
+ .thumb_set DCMI_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak QUADSPI_IRQHandler
+ .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak FMPI2C1_EV_IRQHandler
+ .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler
+
+ .weak FMPI2C1_ER_IRQHandler
+ .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/app.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/app.d
new file mode 100644
index 0000000..8936570
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/app.d
@@ -0,0 +1,89 @@
+Core/Src/app.o: ../Core/Src/app.c ../Core/Inc/app.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Core/Inc/main.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Core/Inc/app.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Core/Inc/main.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/app.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/app.o
new file mode 100644
index 0000000..72cd187
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/app.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/app.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/app.su
new file mode 100644
index 0000000..61e7fa4
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/app.su
@@ -0,0 +1 @@
+../Core/Src/app.c:34:6:SystemClock_Config 88 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/freertos.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/freertos.d
new file mode 100644
index 0000000..c03dce6
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/freertos.d
@@ -0,0 +1,72 @@
+Core/Src/freertos.o: ../Core/Src/freertos.c \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Core/Inc/main.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Core/Inc/main.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/freertos.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/freertos.o
new file mode 100644
index 0000000..3acd588
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/freertos.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/freertos.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/freertos.su
new file mode 100644
index 0000000..ef2a7c6
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/freertos.su
@@ -0,0 +1 @@
+../Core/Src/freertos.c:62:6:vApplicationGetIdleTaskMemory 24 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/main.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/main.d
new file mode 100644
index 0000000..afe7a49
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/main.d
@@ -0,0 +1,90 @@
+Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \
+ ../Core/Inc/app.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
+../Core/Inc/main.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
+../Core/Inc/app.h:
+../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/main.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/main.o
new file mode 100644
index 0000000..0ea1321
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/main.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/main.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/main.su
new file mode 100644
index 0000000..71bc444
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/main.su
@@ -0,0 +1,5 @@
+../Core/Src/main.c:38:5:main 72 static
+../Core/Src/main.c:75:13:MX_GPIO_Init 32 static
+../Core/Src/main.c:104:6:StartDefaultTask 16 static
+../Core/Src/main.c:123:6:StartTask02 16 static
+../Core/Src/main.c:140:6:blinkaled 8 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/stm32f4xx_hal_msp.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/stm32f4xx_hal_msp.d
new file mode 100644
index 0000000..66ff373
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/stm32f4xx_hal_msp.d
@@ -0,0 +1,54 @@
+Core/Src/stm32f4xx_hal_msp.o: ../Core/Src/stm32f4xx_hal_msp.c \
+ ../Core/Inc/main.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Core/Inc/main.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/stm32f4xx_hal_msp.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/stm32f4xx_hal_msp.o
new file mode 100644
index 0000000..486146e
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/stm32f4xx_hal_msp.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/stm32f4xx_hal_msp.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/stm32f4xx_hal_msp.su
new file mode 100644
index 0000000..f8f16b1
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/stm32f4xx_hal_msp.su
@@ -0,0 +1,3 @@
+../Core/Src/stm32f4xx_hal_msp.c:63:6:HAL_MspInit 16 static
+../Core/Src/stm32f4xx_hal_msp.c:87:6:HAL_UART_MspInit 48 static
+../Core/Src/stm32f4xx_hal_msp.c:123:6:HAL_UART_MspDeInit 16 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/stm32f4xx_it.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/stm32f4xx_it.d
new file mode 100644
index 0000000..0fdd35e
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/stm32f4xx_it.d
@@ -0,0 +1,74 @@
+Core/Src/stm32f4xx_it.o: ../Core/Src/stm32f4xx_it.c ../Core/Inc/main.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \
+ ../Core/Inc/stm32f4xx_it.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \
+ ../Core/Inc/FreeRTOSConfig.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \
+ ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h
+../Core/Inc/main.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
+../Core/Inc/stm32f4xx_it.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h:
+../Core/Inc/FreeRTOSConfig.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h:
+../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/task.h:
+../Middlewares/Third_Party/FreeRTOS/Source/include/list.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/stm32f4xx_it.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/stm32f4xx_it.o
new file mode 100644
index 0000000..e9ca0f0
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/stm32f4xx_it.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/stm32f4xx_it.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/stm32f4xx_it.su
new file mode 100644
index 0000000..60c2be7
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/stm32f4xx_it.su
@@ -0,0 +1,8 @@
+../Core/Src/stm32f4xx_it.c:71:6:NMI_Handler 4 static
+../Core/Src/stm32f4xx_it.c:86:6:HardFault_Handler 4 static
+../Core/Src/stm32f4xx_it.c:101:6:MemManage_Handler 4 static
+../Core/Src/stm32f4xx_it.c:116:6:BusFault_Handler 4 static
+../Core/Src/stm32f4xx_it.c:131:6:UsageFault_Handler 4 static
+../Core/Src/stm32f4xx_it.c:146:6:DebugMon_Handler 4 static
+../Core/Src/stm32f4xx_it.c:156:6:Error_Handler 4 static,ignoring_inline_asm
+../Core/Src/stm32f4xx_it.c:172:6:SysTick_Handler 8 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/subdir.mk b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/subdir.mk
new file mode 100644
index 0000000..e068ab2
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/subdir.mk
@@ -0,0 +1,48 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (10.3-2021.10)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../Core/Src/app.c \
+../Core/Src/freertos.c \
+../Core/Src/main.c \
+../Core/Src/stm32f4xx_hal_msp.c \
+../Core/Src/stm32f4xx_it.c \
+../Core/Src/syscalls.c \
+../Core/Src/sysmem.c \
+../Core/Src/system_stm32f4xx.c
+
+OBJS += \
+./Core/Src/app.o \
+./Core/Src/freertos.o \
+./Core/Src/main.o \
+./Core/Src/stm32f4xx_hal_msp.o \
+./Core/Src/stm32f4xx_it.o \
+./Core/Src/syscalls.o \
+./Core/Src/sysmem.o \
+./Core/Src/system_stm32f4xx.o
+
+C_DEPS += \
+./Core/Src/app.d \
+./Core/Src/freertos.d \
+./Core/Src/main.d \
+./Core/Src/stm32f4xx_hal_msp.d \
+./Core/Src/stm32f4xx_it.d \
+./Core/Src/syscalls.d \
+./Core/Src/sysmem.d \
+./Core/Src/system_stm32f4xx.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Core/Src/%.o Core/Src/%.su: ../Core/Src/%.c Core/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F446xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+
+clean: clean-Core-2f-Src
+
+clean-Core-2f-Src:
+ -$(RM) ./Core/Src/app.d ./Core/Src/app.o ./Core/Src/app.su ./Core/Src/freertos.d ./Core/Src/freertos.o ./Core/Src/freertos.su ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/stm32f4xx_hal_msp.d ./Core/Src/stm32f4xx_hal_msp.o ./Core/Src/stm32f4xx_hal_msp.su ./Core/Src/stm32f4xx_it.d ./Core/Src/stm32f4xx_it.o ./Core/Src/stm32f4xx_it.su ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32f4xx.d ./Core/Src/system_stm32f4xx.o ./Core/Src/system_stm32f4xx.su
+
+.PHONY: clean-Core-2f-Src
+
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/syscalls.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/syscalls.d
new file mode 100644
index 0000000..8667c70
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/syscalls.d
@@ -0,0 +1 @@
+Core/Src/syscalls.o: ../Core/Src/syscalls.c
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/syscalls.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/syscalls.o
new file mode 100644
index 0000000..912586a
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/syscalls.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/syscalls.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/syscalls.su
new file mode 100644
index 0000000..50b547a
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/syscalls.su
@@ -0,0 +1,18 @@
+../Core/Src/syscalls.c:44:6:initialise_monitor_handles 4 static
+../Core/Src/syscalls.c:48:5:_getpid 4 static
+../Core/Src/syscalls.c:53:5:_kill 16 static
+../Core/Src/syscalls.c:61:6:_exit 16 static
+../Core/Src/syscalls.c:67:27:_read 32 static
+../Core/Src/syscalls.c:80:27:_write 32 static
+../Core/Src/syscalls.c:92:5:_close 16 static
+../Core/Src/syscalls.c:99:5:_fstat 16 static
+../Core/Src/syscalls.c:106:5:_isatty 16 static
+../Core/Src/syscalls.c:112:5:_lseek 24 static
+../Core/Src/syscalls.c:120:5:_open 12 static
+../Core/Src/syscalls.c:128:5:_wait 16 static
+../Core/Src/syscalls.c:135:5:_unlink 16 static
+../Core/Src/syscalls.c:142:5:_times 16 static
+../Core/Src/syscalls.c:148:5:_stat 16 static
+../Core/Src/syscalls.c:155:5:_link 16 static
+../Core/Src/syscalls.c:163:5:_fork 8 static
+../Core/Src/syscalls.c:169:5:_execve 24 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/sysmem.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/sysmem.d
new file mode 100644
index 0000000..74fecf9
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/sysmem.d
@@ -0,0 +1 @@
+Core/Src/sysmem.o: ../Core/Src/sysmem.c
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/sysmem.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/sysmem.o
new file mode 100644
index 0000000..f84cfe8
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/sysmem.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/sysmem.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/sysmem.su
new file mode 100644
index 0000000..12d5f17
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/sysmem.su
@@ -0,0 +1 @@
+../Core/Src/sysmem.c:53:7:_sbrk 32 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/system_stm32f4xx.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/system_stm32f4xx.d
new file mode 100644
index 0000000..f34cdbb
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/system_stm32f4xx.d
@@ -0,0 +1,53 @@
+Core/Src/system_stm32f4xx.o: ../Core/Src/system_stm32f4xx.c \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/system_stm32f4xx.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/system_stm32f4xx.o
new file mode 100644
index 0000000..a21764f
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/system_stm32f4xx.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/system_stm32f4xx.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/system_stm32f4xx.su
new file mode 100644
index 0000000..96f1cd4
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Src/system_stm32f4xx.su
@@ -0,0 +1,2 @@
+../Core/Src/system_stm32f4xx.c:167:6:SystemInit 4 static
+../Core/Src/system_stm32f4xx.c:220:6:SystemCoreClockUpdate 32 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Startup/startup_stm32f446retx.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Startup/startup_stm32f446retx.d
new file mode 100644
index 0000000..168e9e8
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Startup/startup_stm32f446retx.d
@@ -0,0 +1,2 @@
+Core/Startup/startup_stm32f446retx.o: \
+ ../Core/Startup/startup_stm32f446retx.s
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Startup/startup_stm32f446retx.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Startup/startup_stm32f446retx.o
new file mode 100644
index 0000000..3b4eebe
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Startup/startup_stm32f446retx.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Startup/subdir.mk b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Startup/subdir.mk
new file mode 100644
index 0000000..1ebf864
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Core/Startup/subdir.mk
@@ -0,0 +1,27 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (10.3-2021.10)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+S_SRCS += \
+../Core/Startup/startup_stm32f446retx.s
+
+OBJS += \
+./Core/Startup/startup_stm32f446retx.o
+
+S_DEPS += \
+./Core/Startup/startup_stm32f446retx.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk
+ arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" "$<"
+
+clean: clean-Core-2f-Startup
+
+clean-Core-2f-Startup:
+ -$(RM) ./Core/Startup/startup_stm32f446retx.d ./Core/Startup/startup_stm32f446retx.o
+
+.PHONY: clean-Core-2f-Startup
+
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d
new file mode 100644
index 0000000..4024655
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d
@@ -0,0 +1,54 @@
+Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o: \
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
new file mode 100644
index 0000000..ad839e8
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su
new file mode 100644
index 0000000..424e879
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su
@@ -0,0 +1,27 @@
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:157:19:HAL_Init 8 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:190:19:HAL_DeInit 8 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:219:13:HAL_MspInit 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:230:13:HAL_MspDeInit 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:253:26:HAL_InitTick 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:312:13:HAL_IncTick 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:323:17:HAL_GetTick 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:332:10:HAL_GetTickPrio 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:341:19:HAL_SetTickFreq 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:373:21:HAL_GetTickFreq 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:389:13:HAL_Delay 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:415:13:HAL_SuspendTick 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:431:13:HAL_ResumeTick 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:441:10:HAL_GetHalVersion 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:450:10:HAL_GetREVID 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:459:10:HAL_GetDEVID 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:468:6:HAL_DBGMCU_EnableDBGSleepMode 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:477:6:HAL_DBGMCU_DisableDBGSleepMode 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:486:6:HAL_DBGMCU_EnableDBGStopMode 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:495:6:HAL_DBGMCU_DisableDBGStopMode 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:504:6:HAL_DBGMCU_EnableDBGStandbyMode 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:513:6:HAL_DBGMCU_DisableDBGStandbyMode 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:524:6:HAL_EnableCompensationCell 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:535:6:HAL_DisableCompensationCell 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:544:10:HAL_GetUIDw0 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:553:10:HAL_GetUIDw1 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c:562:10:HAL_GetUIDw2 4 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d
new file mode 100644
index 0000000..1b9b47a
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d
@@ -0,0 +1,54 @@
+Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o: \
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
new file mode 100644
index 0000000..10bb92a
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su
new file mode 100644
index 0000000..6ed4c17
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su
@@ -0,0 +1,32 @@
+../Drivers/CMSIS/Include/core_cm4.h:1657:22:__NVIC_SetPriorityGrouping 24 static
+../Drivers/CMSIS/Include/core_cm4.h:1676:26:__NVIC_GetPriorityGrouping 4 static
+../Drivers/CMSIS/Include/core_cm4.h:1688:22:__NVIC_EnableIRQ 16 static
+../Drivers/CMSIS/Include/core_cm4.h:1724:22:__NVIC_DisableIRQ 16 static,ignoring_inline_asm
+../Drivers/CMSIS/Include/core_cm4.h:1743:26:__NVIC_GetPendingIRQ 16 static
+../Drivers/CMSIS/Include/core_cm4.h:1762:22:__NVIC_SetPendingIRQ 16 static
+../Drivers/CMSIS/Include/core_cm4.h:1777:22:__NVIC_ClearPendingIRQ 16 static
+../Drivers/CMSIS/Include/core_cm4.h:1794:26:__NVIC_GetActive 16 static
+../Drivers/CMSIS/Include/core_cm4.h:1816:22:__NVIC_SetPriority 16 static
+../Drivers/CMSIS/Include/core_cm4.h:1838:26:__NVIC_GetPriority 16 static
+../Drivers/CMSIS/Include/core_cm4.h:1863:26:NVIC_EncodePriority 40 static
+../Drivers/CMSIS/Include/core_cm4.h:1890:22:NVIC_DecodePriority 40 static
+../Drivers/CMSIS/Include/core_cm4.h:1939:34:__NVIC_SystemReset 4 static,ignoring_inline_asm
+../Drivers/CMSIS/Include/core_cm4.h:2022:26:SysTick_Config 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:141:6:HAL_NVIC_SetPriorityGrouping 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:163:6:HAL_NVIC_SetPriority 32 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:185:6:HAL_NVIC_EnableIRQ 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:201:6:HAL_NVIC_DisableIRQ 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:214:6:HAL_NVIC_SystemReset 8 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:227:10:HAL_SYSTICK_Config 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:256:6:HAL_MPU_Disable 4 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:279:6:HAL_MPU_Enable 16 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:298:6:HAL_MPU_ConfigRegion 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:342:10:HAL_NVIC_GetPriorityGrouping 8 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:369:6:HAL_NVIC_GetPriority 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:384:6:HAL_NVIC_SetPendingIRQ 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:402:10:HAL_NVIC_GetPendingIRQ 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:418:6:HAL_NVIC_ClearPendingIRQ 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:435:10:HAL_NVIC_GetActive 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:452:6:HAL_SYSTICK_CLKSourceConfig 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:470:6:HAL_SYSTICK_IRQHandler 8 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c:479:13:HAL_SYSTICK_Callback 4 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d
new file mode 100644
index 0000000..529e1aa
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d
@@ -0,0 +1,54 @@
+Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o: \
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
new file mode 100644
index 0000000..1f518bf
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su
new file mode 100644
index 0000000..6c24b90
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su
@@ -0,0 +1,15 @@
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:170:19:HAL_DMA_Init 32 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:309:19:HAL_DMA_DeInit 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:407:19:HAL_DMA_Start 32 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:451:19:HAL_DMA_Start_IT 32 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:513:19:HAL_DMA_Abort 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:580:19:HAL_DMA_Abort_IT 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:610:19:HAL_DMA_PollForTransfer 48 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:746:6:HAL_DMA_IRQHandler 32 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:967:19:HAL_DMA_RegisterCallback 32 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1029:19:HAL_DMA_UnRegisterCallback 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1114:22:HAL_DMA_GetState 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1125:10:HAL_DMA_GetError 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1151:13:DMA_SetConfig 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1185:17:DMA_CalcBaseAndBitshift 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c:1213:26:DMA_CheckFifoParam 24 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d
new file mode 100644
index 0000000..b6e0cc6
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d
@@ -0,0 +1,54 @@
+Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o: \
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
new file mode 100644
index 0000000..d43413d
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su
new file mode 100644
index 0000000..9b2268b
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su
@@ -0,0 +1,4 @@
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:100:19:HAL_DMAEx_MultiBufferStart 32 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:154:19:HAL_DMAEx_MultiBufferStart_IT 32 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:239:19:HAL_DMAEx_ChangeMemory 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:276:13:DMA_MultiBufferSetConfig 24 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d
new file mode 100644
index 0000000..e0027af
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d
@@ -0,0 +1,54 @@
+Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o: \
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
new file mode 100644
index 0000000..96d2998
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su
new file mode 100644
index 0000000..be56024
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su
@@ -0,0 +1,9 @@
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:142:19:HAL_EXTI_SetConfigLine 32 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:237:19:HAL_EXTI_GetConfigLine 32 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:316:19:HAL_EXTI_ClearConfigLine 32 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:369:19:HAL_EXTI_RegisterCallback 32 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:394:19:HAL_EXTI_GetHandle 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:434:6:HAL_EXTI_IRQHandler 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:466:10:HAL_EXTI_GetPending 32 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:495:6:HAL_EXTI_ClearPending 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c:516:6:HAL_EXTI_GenerateSWI 24 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d
new file mode 100644
index 0000000..c7fe45f
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d
@@ -0,0 +1,54 @@
+Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o: \
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
new file mode 100644
index 0000000..729768a
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su
new file mode 100644
index 0000000..a5b3ff7
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su
@@ -0,0 +1,17 @@
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:154:19:HAL_FLASH_Program 32 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:212:19:HAL_FLASH_Program_IT 32 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:259:6:HAL_FLASH_IRQHandler 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:382:13:HAL_FLASH_EndOfOperationCallback 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:399:13:HAL_FLASH_OperationErrorCallback 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:431:19:HAL_FLASH_Unlock 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:455:19:HAL_FLASH_Lock 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:467:19:HAL_FLASH_OB_Unlock 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:487:19:HAL_FLASH_OB_Lock 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:499:19:HAL_FLASH_OB_Launch 8 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:536:10:HAL_FLASH_GetError 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:550:19:FLASH_WaitForLastOperation 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:610:13:FLASH_Program_DoubleWord 24 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:644:13:FLASH_Program_Word 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:669:13:FLASH_Program_HalfWord 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:694:13:FLASH_Program_Byte 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c:711:13:FLASH_SetErrorCode 4 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d
new file mode 100644
index 0000000..ff05e54
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d
@@ -0,0 +1,54 @@
+Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o: \
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
new file mode 100644
index 0000000..819a602
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su
new file mode 100644
index 0000000..75051d9
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su
@@ -0,0 +1,22 @@
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:160:19:HAL_FLASHEx_Erase 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:231:19:HAL_FLASHEx_Erase_IT 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:284:19:HAL_FLASHEx_OBProgram 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:343:6:HAL_FLASHEx_OBGetConfig 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:372:19:HAL_FLASHEx_AdvOBProgram 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:428:6:HAL_FLASHEx_AdvOBGetConfig 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:460:19:HAL_FLASHEx_OB_SelectPCROP 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:485:19:HAL_FLASHEx_OB_DeSelectPCROP 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:951:13:FLASH_MassErase 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:980:6:FLASH_Erase_Sector 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1030:26:FLASH_OB_EnableWRP 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1066:26:FLASH_OB_DisableWRP 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1099:26:FLASH_OB_EnablePCROP 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1127:26:FLASH_OB_DisablePCROP 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1160:26:FLASH_OB_RDP_LevelConfig 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1194:26:FLASH_OB_UserConfig 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1229:26:FLASH_OB_BOR_LevelConfig 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1247:16:FLASH_OB_GetUser 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1257:17:FLASH_OB_GetWRP 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1271:16:FLASH_OB_GetRDP 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1299:16:FLASH_OB_GetBOR 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c:1309:6:FLASH_FlushCaches 4 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d
new file mode 100644
index 0000000..8a68788
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d
@@ -0,0 +1,54 @@
+Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o: \
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
new file mode 100644
index 0000000..fd614ee
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su
new file mode 100644
index 0000000..c37958f
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su
@@ -0,0 +1,4 @@
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:94:30:HAL_FLASHEx_StopFlashInterfaceClk 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:111:30:HAL_FLASHEx_StartFlashInterfaceClk 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:128:30:HAL_FLASHEx_EnableFlashSleepMode 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:145:30:HAL_FLASHEx_DisableFlashSleepMode 16 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d
new file mode 100644
index 0000000..ca727b8
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d
@@ -0,0 +1,54 @@
+Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o: \
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
new file mode 100644
index 0000000..ac417c7
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su
new file mode 100644
index 0000000..2ae1321
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su
@@ -0,0 +1,8 @@
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:164:6:HAL_GPIO_Init 40 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:294:6:HAL_GPIO_DeInit 32 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:375:15:HAL_GPIO_ReadPin 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:410:6:HAL_GPIO_WritePin 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:433:6:HAL_GPIO_TogglePin 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:458:19:HAL_GPIO_LockPin 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:492:6:HAL_GPIO_EXTI_IRQHandler 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c:507:13:HAL_GPIO_EXTI_Callback 16 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d
new file mode 100644
index 0000000..fb52aed
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d
@@ -0,0 +1,54 @@
+Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o: \
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
new file mode 100644
index 0000000..9889ecc
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su
new file mode 100644
index 0000000..e0a0182
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su
@@ -0,0 +1,17 @@
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:90:6:HAL_PWR_DeInit 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:108:6:HAL_PWR_EnableBkUpAccess 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:128:6:HAL_PWR_DisableBkUpAccess 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:266:6:HAL_PWR_ConfigPVD 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:309:6:HAL_PWR_EnablePVD 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:318:6:HAL_PWR_DisablePVD 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:332:6:HAL_PWR_EnableWakeUpPin 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:350:6:HAL_PWR_DisableWakeUpPin 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:379:6:HAL_PWR_EnterSLEEPMode 16 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:422:6:HAL_PWR_EnterSTOPMode 16 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:461:6:HAL_PWR_EnterSTANDBYMode 4 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:482:6:HAL_PWR_PVD_IRQHandler 8 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:499:13:HAL_PWR_PVDCallback 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:514:6:HAL_PWR_EnableSleepOnExit 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:526:6:HAL_PWR_DisableSleepOnExit 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:538:6:HAL_PWR_EnableSEVOnPend 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c:550:6:HAL_PWR_DisableSEVOnPend 4 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d
new file mode 100644
index 0000000..8f014c2
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d
@@ -0,0 +1,54 @@
+Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o: \
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
new file mode 100644
index 0000000..c4e6e34
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su
new file mode 100644
index 0000000..afdd077
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su
@@ -0,0 +1,9 @@
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:141:19:HAL_PWREx_EnableBkUpReg 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:165:19:HAL_PWREx_DisableBkUpReg 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:189:6:HAL_PWREx_EnableFlashPowerDown 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:198:6:HAL_PWREx_DisableFlashPowerDown 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:211:10:HAL_PWREx_GetVoltageRange 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:288:19:HAL_PWREx_ControlVoltageScaling 32 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:413:19:HAL_PWREx_EnableOverDrive 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:460:19:HAL_PWREx_DisableOverDrive 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c:536:19:HAL_PWREx_EnterUnderDriveSTOPMode 24 static,ignoring_inline_asm
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d
new file mode 100644
index 0000000..2950da3
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d
@@ -0,0 +1,54 @@
+Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o: \
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
new file mode 100644
index 0000000..cadd55a
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su
new file mode 100644
index 0000000..9dfcbbe
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su
@@ -0,0 +1,14 @@
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:200:26:HAL_RCC_DeInit 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:219:26:HAL_RCC_OscConfig 32 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:591:19:HAL_RCC_ClockConfig 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:775:6:HAL_RCC_MCOConfig 56 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:841:6:HAL_RCC_EnableCSS 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:850:6:HAL_RCC_DisableCSS 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:885:17:HAL_RCC_GetSysClockFreq 112 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:941:10:HAL_RCC_GetHCLKFreq 4 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:952:10:HAL_RCC_GetPCLK1Freq 8 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:964:10:HAL_RCC_GetPCLK2Freq 8 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:977:13:HAL_RCC_GetOscConfig 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1056:6:HAL_RCC_GetClockConfig 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1082:6:HAL_RCC_NMI_IRQHandler 8 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:1099:13:HAL_RCC_CSSCallback 4 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d
new file mode 100644
index 0000000..119c233
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d
@@ -0,0 +1,54 @@
+Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o: \
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
new file mode 100644
index 0000000..2556f6f
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su
new file mode 100644
index 0000000..b3ce977
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su
@@ -0,0 +1,12 @@
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:87:19:HAL_RCCEx_PeriphCLKConfig 56 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:489:6:HAL_RCCEx_GetPeriphCLKConfig 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:569:10:HAL_RCCEx_GetPeriphCLKFreq 40 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2766:6:HAL_RCCEx_SelectLSEMode 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2803:19:HAL_RCCEx_EnablePLLI2S 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2886:19:HAL_RCCEx_DisablePLLI2S 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2916:19:HAL_RCCEx_EnablePLLSAI 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:2990:19:HAL_RCCEx_DisablePLLSAI 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3051:10:HAL_RCC_GetSysClockFreq 216 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3143:19:HAL_RCC_DeInit 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3333:19:HAL_RCC_OscConfig 32 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c:3703:6:HAL_RCC_GetOscConfig 16 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d
new file mode 100644
index 0000000..6ebda9e
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d
@@ -0,0 +1,54 @@
+Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o: \
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o
new file mode 100644
index 0000000..2af186e
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su
new file mode 100644
index 0000000..e69de29
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d
new file mode 100644
index 0000000..3da5d07
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d
@@ -0,0 +1,54 @@
+Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o: \
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o
new file mode 100644
index 0000000..016354a
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su
new file mode 100644
index 0000000..e69de29
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d
new file mode 100644
index 0000000..dd6a601
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d
@@ -0,0 +1,54 @@
+Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o: \
+ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
+ ../Core/Inc/stm32f4xx_hal_conf.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h \
+ ../Drivers/CMSIS/Include/core_cm4.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
+ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
+../Core/Inc/stm32f4xx_hal_conf.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h:
+../Drivers/CMSIS/Include/core_cm4.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
+../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
new file mode 100644
index 0000000..d8e30b7
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.su b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.su
new file mode 100644
index 0000000..75d1e86
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.su
@@ -0,0 +1,61 @@
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:357:19:HAL_UART_Init 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:434:19:HAL_HalfDuplex_Init 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:507:19:HAL_LIN_Init 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:588:19:HAL_MultiProcessor_Init 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:665:19:HAL_UART_DeInit 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:710:13:HAL_UART_MspInit 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:725:13:HAL_UART_MspDeInit 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1136:19:HAL_UART_Transmit 48 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1224:19:HAL_UART_Receive 48 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1315:19:HAL_UART_Transmit_IT 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1360:19:HAL_UART_Receive_IT 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1395:19:HAL_UART_Transmit_DMA 56 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1463:19:HAL_UART_Receive_DMA 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1493:19:HAL_UART_DMAPause 120 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1530:19:HAL_UART_DMAResume 120 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1569:19:HAL_UART_DMAStop 72 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1624:19:HAL_UARTEx_ReceiveToIdle 40 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1751:19:HAL_UARTEx_ReceiveToIdle_IT 56 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1812:19:HAL_UARTEx_ReceiveToIdle_DMA 56 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1869:19:HAL_UART_Abort 136 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:1958:19:HAL_UART_AbortTransmit 64 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2009:19:HAL_UART_AbortReceive 112 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2070:19:HAL_UART_Abort_IT 144 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2205:19:HAL_UART_AbortTransmit_IT 64 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2282:19:HAL_UART_AbortReceive_IT 112 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2360:6:HAL_UART_IRQHandler 240 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2592:13:HAL_UART_TxCpltCallback 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2607:13:HAL_UART_TxHalfCpltCallback 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2622:13:HAL_UART_RxCpltCallback 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2637:13:HAL_UART_RxHalfCpltCallback 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2652:13:HAL_UART_ErrorCallback 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2666:13:HAL_UART_AbortCpltCallback 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2681:13:HAL_UART_AbortTransmitCpltCallback 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2696:13:HAL_UART_AbortReceiveCpltCallback 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2713:13:HAL_UARTEx_RxEventCallback 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2753:19:HAL_LIN_SendBreak 40 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2780:19:HAL_MultiProcessor_EnterMuteMode 40 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2807:19:HAL_MultiProcessor_ExitMuteMode 40 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2834:19:HAL_HalfDuplex_EnableTransmitter 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2869:19:HAL_HalfDuplex_EnableReceiver 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2926:23:HAL_UART_GetState 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2941:10:HAL_UART_GetError 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:2986:13:UART_DMATransmitCplt 72 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3021:13:UART_DMATxHalfCplt 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3040:13:UART_DMAReceiveCplt 120 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3097:13:UART_DMARxHalfCplt 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3132:13:UART_DMAError 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3174:26:UART_WaitOnFlagUntilTimeout 72 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3213:19:UART_Start_Receive_IT 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3251:19:UART_Start_Receive_DMA 104 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3304:13:UART_EndTxTransfer 40 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3318:13:UART_EndRxTransfer 88 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3342:13:UART_DMAAbortOnError 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3366:13:UART_DMATxAbortCallback 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3412:13:UART_DMARxAbortCallback 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3458:13:UART_DMATxOnlyAbortCallback 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3486:13:UART_DMARxOnlyAbortCallback 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3512:26:UART_Transmit_IT 24 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3552:26:UART_EndTransmit_IT 16 static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3577:26:UART_Receive_IT 56 static,ignoring_inline_asm
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c:3675:13:UART_SetConfig 288 static
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk
new file mode 100644
index 0000000..de94547
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk
@@ -0,0 +1,72 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (10.3-2021.10)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c \
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c \
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c \
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c
+
+OBJS += \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
+
+C_DEPS += \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d \
+./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Drivers/STM32F4xx_HAL_Driver/Src/%.o Drivers/STM32F4xx_HAL_Driver/Src/%.su: ../Drivers/STM32F4xx_HAL_Driver/Src/%.c Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F446xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+
+clean: clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src
+
+clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src:
+ -$(RM) ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.su
+
+.PHONY: clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src
+
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/FreeRTOS_LED.elf b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/FreeRTOS_LED.elf
new file mode 100644
index 0000000..4e51f00
Binary files /dev/null and b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/FreeRTOS_LED.elf differ
diff --git a/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/FreeRTOS_LED.list b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/FreeRTOS_LED.list
new file mode 100644
index 0000000..8f1e923
--- /dev/null
+++ b/tutorial01-stm32-pio-01/pio-01-02_olivia/Debug/FreeRTOS_LED.list
@@ -0,0 +1,7892 @@
+
+FreeRTOS_LED.elf: file format elf32-littlearm
+
+Sections:
+Idx Name Size VMA LMA File off Algn
+ 0 .isr_vector 000001c4 08000000 08000000 00010000 2**0
+ CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 1 .text 00002d4c 080001d0 080001d0 000101d0 2**4
+ CONTENTS, ALLOC, LOAD, READONLY, CODE
+ 2 .rodata 00000068 08002f1c 08002f1c 00012f1c 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 3 .ARM.extab 00000000 08002f84 08002f84 00020010 2**0
+ CONTENTS
+ 4 .ARM 00000008 08002f84 08002f84 00012f84 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 5 .preinit_array 00000000 08002f8c 08002f8c 00020010 2**0
+ CONTENTS, ALLOC, LOAD, DATA
+ 6 .init_array 00000004 08002f8c 08002f8c 00012f8c 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 7 .fini_array 00000004 08002f90 08002f90 00012f90 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 8 .data 00000010 20000000 08002f94 00020000 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 9 .bss 00003fd0 20000010 08002fa4 00020010 2**2
+ ALLOC
+ 10 ._user_heap_stack 00000600 20003fe0 08002fa4 00023fe0 2**0
+ ALLOC
+ 11 .ARM.attributes 00000030 00000000 00000000 00020010 2**0
+ CONTENTS, READONLY
+ 12 .debug_info 00009d75 00000000 00000000 00020040 2**0
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 13 .debug_abbrev 00001ffe 00000000 00000000 00029db5 2**0
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 14 .debug_aranges 00000960 00000000 00000000 0002bdb8 2**3
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 15 .debug_ranges 00000858 00000000 00000000 0002c718 2**3
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 16 .debug_macro 00021cde 00000000 00000000 0002cf70 2**0
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 17 .debug_line 0000b31c 00000000 00000000 0004ec4e 2**0
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 18 .debug_str 000cf5eb 00000000 00000000 00059f6a 2**0
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 19 .comment 00000050 00000000 00000000 00129555 2**0
+ CONTENTS, READONLY
+ 20 .debug_frame 000023e4 00000000 00000000 001295a8 2**2
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+
+Disassembly of section .text:
+
+080001d0 <__do_global_dtors_aux>:
+ 80001d0: b510 push {r4, lr}
+ 80001d2: 4c05 ldr r4, [pc, #20] ; (80001e8 <__do_global_dtors_aux+0x18>)
+ 80001d4: 7823 ldrb r3, [r4, #0]
+ 80001d6: b933 cbnz r3, 80001e6 <__do_global_dtors_aux+0x16>
+ 80001d8: 4b04 ldr r3, [pc, #16] ; (80001ec <__do_global_dtors_aux+0x1c>)
+ 80001da: b113 cbz r3, 80001e2 <__do_global_dtors_aux+0x12>
+ 80001dc: 4804 ldr r0, [pc, #16] ; (80001f0 <__do_global_dtors_aux+0x20>)
+ 80001de: f3af 8000 nop.w
+ 80001e2: 2301 movs r3, #1
+ 80001e4: 7023 strb r3, [r4, #0]
+ 80001e6: bd10 pop {r4, pc}
+ 80001e8: 20000010 .word 0x20000010
+ 80001ec: 00000000 .word 0x00000000
+ 80001f0: 08002f04 .word 0x08002f04
+
+080001f4 :
+ 80001f4: b508 push {r3, lr}
+ 80001f6: 4b03 ldr r3, [pc, #12] ; (8000204 )
+ 80001f8: b11b cbz r3, 8000202
+ 80001fa: 4903 ldr r1, [pc, #12] ; (8000208 )
+ 80001fc: 4803 ldr r0, [pc, #12] ; (800020c )
+ 80001fe: f3af 8000 nop.w
+ 8000202: bd08 pop {r3, pc}
+ 8000204: 00000000 .word 0x00000000
+ 8000208: 20000014 .word 0x20000014
+ 800020c: 08002f04 .word 0x08002f04
+
+08000210 <__aeabi_uldivmod>:
+ 8000210: b953 cbnz r3, 8000228 <__aeabi_uldivmod+0x18>
+ 8000212: b94a cbnz r2, 8000228 <__aeabi_uldivmod+0x18>
+ 8000214: 2900 cmp r1, #0
+ 8000216: bf08 it eq
+ 8000218: 2800 cmpeq r0, #0
+ 800021a: bf1c itt ne
+ 800021c: f04f 31ff movne.w r1, #4294967295
+ 8000220: f04f 30ff movne.w r0, #4294967295
+ 8000224: f000 b974 b.w 8000510 <__aeabi_idiv0>
+ 8000228: f1ad 0c08 sub.w ip, sp, #8
+ 800022c: e96d ce04 strd ip, lr, [sp, #-16]!
+ 8000230: f000 f806 bl 8000240 <__udivmoddi4>
+ 8000234: f8dd e004 ldr.w lr, [sp, #4]
+ 8000238: e9dd 2302 ldrd r2, r3, [sp, #8]
+ 800023c: b004 add sp, #16
+ 800023e: 4770 bx lr
+
+08000240 <__udivmoddi4>:
+ 8000240: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
+ 8000244: 9d08 ldr r5, [sp, #32]
+ 8000246: 4604 mov r4, r0
+ 8000248: 468e mov lr, r1
+ 800024a: 2b00 cmp r3, #0
+ 800024c: d14d bne.n 80002ea <__udivmoddi4+0xaa>
+ 800024e: 428a cmp r2, r1
+ 8000250: 4694 mov ip, r2
+ 8000252: d969 bls.n 8000328 <__udivmoddi4+0xe8>
+ 8000254: fab2 f282 clz r2, r2
+ 8000258: b152 cbz r2, 8000270 <__udivmoddi4+0x30>
+ 800025a: fa01 f302 lsl.w r3, r1, r2
+ 800025e: f1c2 0120 rsb r1, r2, #32
+ 8000262: fa20 f101 lsr.w r1, r0, r1
+ 8000266: fa0c fc02 lsl.w ip, ip, r2
+ 800026a: ea41 0e03 orr.w lr, r1, r3
+ 800026e: 4094 lsls r4, r2
+ 8000270: ea4f 481c mov.w r8, ip, lsr #16
+ 8000274: 0c21 lsrs r1, r4, #16
+ 8000276: fbbe f6f8 udiv r6, lr, r8
+ 800027a: fa1f f78c uxth.w r7, ip
+ 800027e: fb08 e316 mls r3, r8, r6, lr
+ 8000282: ea41 4303 orr.w r3, r1, r3, lsl #16
+ 8000286: fb06 f107 mul.w r1, r6, r7
+ 800028a: 4299 cmp r1, r3
+ 800028c: d90a bls.n 80002a4 <__udivmoddi4+0x64>
+ 800028e: eb1c 0303 adds.w r3, ip, r3
+ 8000292: f106 30ff add.w r0, r6, #4294967295
+ 8000296: f080 811f bcs.w 80004d8 <__udivmoddi4+0x298>
+ 800029a: 4299 cmp r1, r3
+ 800029c: f240 811c bls.w 80004d8 <__udivmoddi4+0x298>
+ 80002a0: 3e02 subs r6, #2
+ 80002a2: 4463 add r3, ip
+ 80002a4: 1a5b subs r3, r3, r1
+ 80002a6: b2a4 uxth r4, r4
+ 80002a8: fbb3 f0f8 udiv r0, r3, r8
+ 80002ac: fb08 3310 mls r3, r8, r0, r3
+ 80002b0: ea44 4403 orr.w r4, r4, r3, lsl #16
+ 80002b4: fb00 f707 mul.w r7, r0, r7
+ 80002b8: 42a7 cmp r7, r4
+ 80002ba: d90a bls.n 80002d2 <__udivmoddi4+0x92>
+ 80002bc: eb1c 0404 adds.w r4, ip, r4
+ 80002c0: f100 33ff add.w r3, r0, #4294967295
+ 80002c4: f080 810a bcs.w 80004dc <__udivmoddi4+0x29c>
+ 80002c8: 42a7 cmp r7, r4
+ 80002ca: f240 8107 bls.w 80004dc <__udivmoddi4+0x29c>
+ 80002ce: 4464 add r4, ip
+ 80002d0: 3802 subs r0, #2
+ 80002d2: ea40 4006 orr.w r0, r0, r6, lsl #16
+ 80002d6: 1be4 subs r4, r4, r7
+ 80002d8: 2600 movs r6, #0
+ 80002da: b11d cbz r5, 80002e4 <__udivmoddi4+0xa4>
+ 80002dc: 40d4 lsrs r4, r2
+ 80002de: 2300 movs r3, #0
+ 80002e0: e9c5 4300 strd r4, r3, [r5]
+ 80002e4: 4631 mov r1, r6
+ 80002e6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+ 80002ea: 428b cmp r3, r1
+ 80002ec: d909 bls.n 8000302 <__udivmoddi4+0xc2>
+ 80002ee: 2d00 cmp r5, #0
+ 80002f0: f000 80ef beq.w 80004d2 <__udivmoddi4+0x292>
+ 80002f4: 2600 movs r6, #0
+ 80002f6: e9c5 0100 strd r0, r1, [r5]
+ 80002fa: 4630 mov r0, r6
+ 80002fc: 4631 mov r1, r6
+ 80002fe: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+ 8000302: fab3 f683 clz r6, r3
+ 8000306: 2e00 cmp r6, #0
+ 8000308: d14a bne.n 80003a0 <__udivmoddi4+0x160>
+ 800030a: 428b cmp r3, r1
+ 800030c: d302 bcc.n 8000314 <__udivmoddi4+0xd4>
+ 800030e: 4282 cmp r2, r0
+ 8000310: f200 80f9 bhi.w 8000506 <__udivmoddi4+0x2c6>
+ 8000314: 1a84 subs r4, r0, r2
+ 8000316: eb61 0303 sbc.w r3, r1, r3
+ 800031a: 2001 movs r0, #1
+ 800031c: 469e mov lr, r3
+ 800031e: 2d00 cmp r5, #0
+ 8000320: d0e0 beq.n 80002e4 <__udivmoddi4+0xa4>
+ 8000322: e9c5 4e00 strd r4, lr, [r5]
+ 8000326: e7dd b.n 80002e4 <__udivmoddi4+0xa4>
+ 8000328: b902 cbnz r2, 800032c <__udivmoddi4+0xec>
+ 800032a: deff udf #255 ; 0xff
+ 800032c: fab2 f282 clz r2, r2
+ 8000330: 2a00 cmp r2, #0
+ 8000332: f040 8092 bne.w 800045a <__udivmoddi4+0x21a>
+ 8000336: eba1 010c sub.w r1, r1, ip
+ 800033a: ea4f 471c mov.w r7, ip, lsr #16
+ 800033e: fa1f fe8c uxth.w lr, ip
+ 8000342: 2601 movs r6, #1
+ 8000344: 0c20 lsrs r0, r4, #16
+ 8000346: fbb1 f3f7 udiv r3, r1, r7
+ 800034a: fb07 1113 mls r1, r7, r3, r1
+ 800034e: ea40 4101 orr.w r1, r0, r1, lsl #16
+ 8000352: fb0e f003 mul.w r0, lr, r3
+ 8000356: 4288 cmp r0, r1
+ 8000358: d908 bls.n 800036c <__udivmoddi4+0x12c>
+ 800035a: eb1c 0101 adds.w r1, ip, r1
+ 800035e: f103 38ff add.w r8, r3, #4294967295
+ 8000362: d202 bcs.n 800036a <__udivmoddi4+0x12a>
+ 8000364: 4288 cmp r0, r1
+ 8000366: f200 80cb bhi.w 8000500 <__udivmoddi4+0x2c0>
+ 800036a: 4643 mov r3, r8
+ 800036c: 1a09 subs r1, r1, r0
+ 800036e: b2a4 uxth r4, r4
+ 8000370: fbb1 f0f7 udiv r0, r1, r7
+ 8000374: fb07 1110 mls r1, r7, r0, r1
+ 8000378: ea44 4401 orr.w r4, r4, r1, lsl #16
+ 800037c: fb0e fe00 mul.w lr, lr, r0
+ 8000380: 45a6 cmp lr, r4
+ 8000382: d908 bls.n 8000396 <__udivmoddi4+0x156>
+ 8000384: eb1c 0404 adds.w r4, ip, r4
+ 8000388: f100 31ff add.w r1, r0, #4294967295
+ 800038c: d202 bcs.n 8000394 <__udivmoddi4+0x154>
+ 800038e: 45a6 cmp lr, r4
+ 8000390: f200 80bb bhi.w 800050a <__udivmoddi4+0x2ca>
+ 8000394: 4608 mov r0, r1
+ 8000396: eba4 040e sub.w r4, r4, lr
+ 800039a: ea40 4003 orr.w r0, r0, r3, lsl #16
+ 800039e: e79c b.n 80002da <__udivmoddi4+0x9a>
+ 80003a0: f1c6 0720 rsb r7, r6, #32
+ 80003a4: 40b3 lsls r3, r6
+ 80003a6: fa22 fc07 lsr.w ip, r2, r7
+ 80003aa: ea4c 0c03 orr.w ip, ip, r3
+ 80003ae: fa20 f407 lsr.w r4, r0, r7
+ 80003b2: fa01 f306 lsl.w r3, r1, r6
+ 80003b6: 431c orrs r4, r3
+ 80003b8: 40f9 lsrs r1, r7
+ 80003ba: ea4f 491c mov.w r9, ip, lsr #16
+ 80003be: fa00 f306 lsl.w r3, r0, r6
+ 80003c2: fbb1 f8f9 udiv r8, r1, r9
+ 80003c6: 0c20 lsrs r0, r4, #16
+ 80003c8: fa1f fe8c uxth.w lr, ip
+ 80003cc: fb09 1118 mls r1, r9, r8, r1
+ 80003d0: ea40 4101 orr.w r1, r0, r1, lsl #16
+ 80003d4: fb08 f00e mul.w r0, r8, lr
+ 80003d8: 4288 cmp r0, r1
+ 80003da: fa02 f206 lsl.w r2, r2, r6
+ 80003de: d90b bls.n 80003f8 <__udivmoddi4+0x1b8>
+ 80003e0: eb1c 0101 adds.w r1, ip, r1
+ 80003e4: f108 3aff add.w sl, r8, #4294967295
+ 80003e8: f080 8088 bcs.w 80004fc <__udivmoddi4+0x2bc>
+ 80003ec: 4288 cmp r0, r1
+ 80003ee: f240 8085 bls.w 80004fc <__udivmoddi4+0x2bc>
+ 80003f2: f1a8 0802 sub.w r8, r8, #2
+ 80003f6: 4461 add r1, ip
+ 80003f8: 1a09 subs r1, r1, r0
+ 80003fa: b2a4 uxth r4, r4
+ 80003fc: fbb1 f0f9 udiv r0, r1, r9
+ 8000400: fb09 1110 mls r1, r9, r0, r1
+ 8000404: ea44 4101 orr.w r1, r4, r1, lsl #16
+ 8000408: fb00 fe0e mul.w lr, r0, lr
+ 800040c: 458e cmp lr, r1
+ 800040e: d908 bls.n 8000422 <__udivmoddi4+0x1e2>
+ 8000410: eb1c 0101 adds.w r1, ip, r1
+ 8000414: f100 34ff add.w r4, r0, #4294967295
+ 8000418: d26c bcs.n 80004f4 <__udivmoddi4+0x2b4>
+ 800041a: 458e cmp lr, r1
+ 800041c: d96a bls.n 80004f4 <__udivmoddi4+0x2b4>
+ 800041e: 3802 subs r0, #2
+ 8000420: 4461 add r1, ip
+ 8000422: ea40 4008 orr.w r0, r0, r8, lsl #16
+ 8000426: fba0 9402 umull r9, r4, r0, r2
+ 800042a: eba1 010e sub.w r1, r1, lr
+ 800042e: 42a1 cmp r1, r4
+ 8000430: 46c8 mov r8, r9
+ 8000432: 46a6 mov lr, r4
+ 8000434: d356 bcc.n 80004e4 <__udivmoddi4+0x2a4>
+ 8000436: d053 beq.n 80004e0 <__udivmoddi4+0x2a0>
+ 8000438: b15d cbz r5, 8000452 <__udivmoddi4+0x212>
+ 800043a: ebb3 0208 subs.w r2, r3, r8
+ 800043e: eb61 010e sbc.w r1, r1, lr
+ 8000442: fa01 f707 lsl.w r7, r1, r7
+ 8000446: fa22 f306 lsr.w r3, r2, r6
+ 800044a: 40f1 lsrs r1, r6
+ 800044c: 431f orrs r7, r3
+ 800044e: e9c5 7100 strd r7, r1, [r5]
+ 8000452: 2600 movs r6, #0
+ 8000454: 4631 mov r1, r6
+ 8000456: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+ 800045a: f1c2 0320 rsb r3, r2, #32
+ 800045e: 40d8 lsrs r0, r3
+ 8000460: fa0c fc02 lsl.w ip, ip, r2
+ 8000464: fa21 f303 lsr.w r3, r1, r3
+ 8000468: 4091 lsls r1, r2
+ 800046a: 4301 orrs r1, r0
+ 800046c: ea4f 471c mov.w r7, ip, lsr #16
+ 8000470: fa1f fe8c uxth.w lr, ip
+ 8000474: fbb3 f0f7 udiv r0, r3, r7
+ 8000478: fb07 3610 mls r6, r7, r0, r3
+ 800047c: 0c0b lsrs r3, r1, #16
+ 800047e: ea43 4306 orr.w r3, r3, r6, lsl #16
+ 8000482: fb00 f60e mul.w r6, r0, lr
+ 8000486: 429e cmp r6, r3
+ 8000488: fa04 f402 lsl.w r4, r4, r2
+ 800048c: d908 bls.n 80004a0 <__udivmoddi4+0x260>
+ 800048e: eb1c 0303 adds.w r3, ip, r3
+ 8000492: f100 38ff add.w r8, r0, #4294967295
+ 8000496: d22f bcs.n 80004f8 <__udivmoddi4+0x2b8>
+ 8000498: 429e cmp r6, r3
+ 800049a: d92d bls.n 80004f8 <__udivmoddi4+0x2b8>
+ 800049c: 3802 subs r0, #2
+ 800049e: 4463 add r3, ip
+ 80004a0: 1b9b subs r3, r3, r6
+ 80004a2: b289 uxth r1, r1
+ 80004a4: fbb3 f6f7 udiv r6, r3, r7
+ 80004a8: fb07 3316 mls r3, r7, r6, r3
+ 80004ac: ea41 4103 orr.w r1, r1, r3, lsl #16
+ 80004b0: fb06 f30e mul.w r3, r6, lr
+ 80004b4: 428b cmp r3, r1
+ 80004b6: d908 bls.n 80004ca <__udivmoddi4+0x28a>
+ 80004b8: eb1c 0101 adds.w r1, ip, r1
+ 80004bc: f106 38ff add.w r8, r6, #4294967295
+ 80004c0: d216 bcs.n 80004f0 <__udivmoddi4+0x2b0>
+ 80004c2: 428b cmp r3, r1
+ 80004c4: d914 bls.n 80004f0 <__udivmoddi4+0x2b0>
+ 80004c6: 3e02 subs r6, #2
+ 80004c8: 4461 add r1, ip
+ 80004ca: 1ac9 subs r1, r1, r3
+ 80004cc: ea46 4600 orr.w r6, r6, r0, lsl #16
+ 80004d0: e738 b.n 8000344 <__udivmoddi4+0x104>
+ 80004d2: 462e mov r6, r5
+ 80004d4: 4628 mov r0, r5
+ 80004d6: e705 b.n 80002e4 <__udivmoddi4+0xa4>
+ 80004d8: 4606 mov r6, r0
+ 80004da: e6e3 b.n 80002a4 <__udivmoddi4+0x64>
+ 80004dc: 4618 mov r0, r3
+ 80004de: e6f8 b.n 80002d2 <__udivmoddi4+0x92>
+ 80004e0: 454b cmp r3, r9
+ 80004e2: d2a9 bcs.n 8000438 <__udivmoddi4+0x1f8>
+ 80004e4: ebb9 0802 subs.w r8, r9, r2
+ 80004e8: eb64 0e0c sbc.w lr, r4, ip
+ 80004ec: 3801 subs r0, #1
+ 80004ee: e7a3 b.n 8000438 <__udivmoddi4+0x1f8>
+ 80004f0: 4646 mov r6, r8
+ 80004f2: e7ea b.n 80004ca <__udivmoddi4+0x28a>
+ 80004f4: 4620 mov r0, r4
+ 80004f6: e794 b.n 8000422 <__udivmoddi4+0x1e2>
+ 80004f8: 4640 mov r0, r8
+ 80004fa: e7d1 b.n 80004a0 <__udivmoddi4+0x260>
+ 80004fc: 46d0 mov r8, sl
+ 80004fe: e77b b.n 80003f8 <__udivmoddi4+0x1b8>
+ 8000500: 3b02 subs r3, #2
+ 8000502: 4461 add r1, ip
+ 8000504: e732 b.n 800036c <__udivmoddi4+0x12c>
+ 8000506: 4630 mov r0, r6
+ 8000508: e709 b.n 800031e <__udivmoddi4+0xde>
+ 800050a: 4464 add r4, ip
+ 800050c: 3802 subs r0, #2
+ 800050e: e742 b.n 8000396 <__udivmoddi4+0x156>
+
+08000510 <__aeabi_idiv0>:
+ 8000510: 4770 bx lr
+ 8000512: bf00 nop
+
+08000514 :
+ * @brief System Clock Configuration
+ * @retval None
+ */
+
+void SystemClock_Config(void)
+{
+ 8000514: b580 push {r7, lr}
+ 8000516: b094 sub sp, #80 ; 0x50
+ 8000518: af00 add r7, sp, #0
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ 800051a: f107 031c add.w r3, r7, #28
+ 800051e: 2234 movs r2, #52 ; 0x34
+ 8000520: 2100 movs r1, #0
+ 8000522: 4618 mov r0, r3
+ 8000524: f002 fce6 bl 8002ef4
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ 8000528: f107 0308 add.w r3, r7, #8
+ 800052c: 2200 movs r2, #0
+ 800052e: 601a str r2, [r3, #0]
+ 8000530: 605a str r2, [r3, #4]
+ 8000532: 609a str r2, [r3, #8]
+ 8000534: 60da str r2, [r3, #12]
+ 8000536: 611a str r2, [r3, #16]
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ 8000538: 2300 movs r3, #0
+ 800053a: 607b str r3, [r7, #4]
+ 800053c: 4b2a ldr r3, [pc, #168] ; (80005e8 )
+ 800053e: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8000540: 4a29 ldr r2, [pc, #164] ; (80005e8 )
+ 8000542: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 8000546: 6413 str r3, [r2, #64] ; 0x40
+ 8000548: 4b27 ldr r3, [pc, #156] ; (80005e8 )
+ 800054a: 6c1b ldr r3, [r3, #64] ; 0x40
+ 800054c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8000550: 607b str r3, [r7, #4]
+ 8000552: 687b ldr r3, [r7, #4]
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+ 8000554: 2300 movs r3, #0
+ 8000556: 603b str r3, [r7, #0]
+ 8000558: 4b24 ldr r3, [pc, #144] ; (80005ec )
+ 800055a: 681b ldr r3, [r3, #0]
+ 800055c: f423 4340 bic.w r3, r3, #49152 ; 0xc000
+ 8000560: 4a22 ldr r2, [pc, #136] ; (80005ec )
+ 8000562: f443 4380 orr.w r3, r3, #16384 ; 0x4000
+ 8000566: 6013 str r3, [r2, #0]
+ 8000568: 4b20 ldr r3, [pc, #128] ; (80005ec )
+ 800056a: 681b ldr r3, [r3, #0]
+ 800056c: f403 4340 and.w r3, r3, #49152 ; 0xc000
+ 8000570: 603b str r3, [r7, #0]
+ 8000572: 683b ldr r3, [r7, #0]
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ 8000574: 2302 movs r3, #2
+ 8000576: 61fb str r3, [r7, #28]
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ 8000578: 2301 movs r3, #1
+ 800057a: 62bb str r3, [r7, #40] ; 0x28
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ 800057c: 2310 movs r3, #16
+ 800057e: 62fb str r3, [r7, #44] ; 0x2c
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ 8000580: 2302 movs r3, #2
+ 8000582: 637b str r3, [r7, #52] ; 0x34
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ 8000584: 2300 movs r3, #0
+ 8000586: 63bb str r3, [r7, #56] ; 0x38
+ RCC_OscInitStruct.PLL.PLLM = 16;
+ 8000588: 2310 movs r3, #16
+ 800058a: 63fb str r3, [r7, #60] ; 0x3c
+ RCC_OscInitStruct.PLL.PLLN = 336;
+ 800058c: f44f 73a8 mov.w r3, #336 ; 0x150
+ 8000590: 643b str r3, [r7, #64] ; 0x40
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+ 8000592: 2304 movs r3, #4
+ 8000594: 647b str r3, [r7, #68] ; 0x44
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ 8000596: 2302 movs r3, #2
+ 8000598: 64bb str r3, [r7, #72] ; 0x48
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ 800059a: 2302 movs r3, #2
+ 800059c: 64fb str r3, [r7, #76] ; 0x4c
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ 800059e: f107 031c add.w r3, r7, #28
+ 80005a2: 4618 mov r0, r3
+ 80005a4: f000 ff7c bl 80014a0
+ 80005a8: 4603 mov r3, r0
+ 80005aa: 2b00 cmp r3, #0
+ 80005ac: d001 beq.n 80005b2
+ {
+ Error_Handler();
+ 80005ae: f000 f90d bl 80007cc
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ 80005b2: 230f movs r3, #15
+ 80005b4: 60bb str r3, [r7, #8]
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ 80005b6: 2302 movs r3, #2
+ 80005b8: 60fb str r3, [r7, #12]
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ 80005ba: 2300 movs r3, #0
+ 80005bc: 613b str r3, [r7, #16]
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ 80005be: f44f 5380 mov.w r3, #4096 ; 0x1000
+ 80005c2: 617b str r3, [r7, #20]
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ 80005c4: 2300 movs r3, #0
+ 80005c6: 61bb str r3, [r7, #24]
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ 80005c8: f107 0308 add.w r3, r7, #8
+ 80005cc: 2102 movs r1, #2
+ 80005ce: 4618 mov r0, r3
+ 80005d0: f000 fc50 bl 8000e74
+ 80005d4: 4603 mov r3, r0
+ 80005d6: 2b00 cmp r3, #0
+ 80005d8: d001 beq.n 80005de
+ {
+ Error_Handler();
+ 80005da: f000 f8f7 bl 80007cc
+ }
+}
+ 80005de: bf00 nop
+ 80005e0: 3750 adds r7, #80 ; 0x50
+ 80005e2: 46bd mov sp, r7
+ 80005e4: bd80 pop {r7, pc}
+ 80005e6: bf00 nop
+ 80005e8: 40023800 .word 0x40023800
+ 80005ec: 40007000 .word 0x40007000
+
+080005f0 :
+/* USER CODE BEGIN GET_IDLE_TASK_MEMORY */
+static StaticTask_t xIdleTaskTCBBuffer;
+static StackType_t xIdleStack[configMINIMAL_STACK_SIZE];
+
+void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
+{
+ 80005f0: b480 push {r7}
+ 80005f2: b085 sub sp, #20
+ 80005f4: af00 add r7, sp, #0
+ 80005f6: 60f8 str r0, [r7, #12]
+ 80005f8: 60b9 str r1, [r7, #8]
+ 80005fa: 607a str r2, [r7, #4]
+ *ppxIdleTaskTCBBuffer = &xIdleTaskTCBBuffer;
+ 80005fc: 68fb ldr r3, [r7, #12]
+ 80005fe: 4a07 ldr r2, [pc, #28] ; (800061c )
+ 8000600: 601a str r2, [r3, #0]
+ *ppxIdleTaskStackBuffer = &xIdleStack[0];
+ 8000602: 68bb ldr r3, [r7, #8]
+ 8000604: 4a06 ldr r2, [pc, #24] ; (8000620 )
+ 8000606: 601a str r2, [r3, #0]
+ *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+ 8000608: 687b ldr r3, [r7, #4]
+ 800060a: 2280 movs r2, #128 ; 0x80
+ 800060c: 601a str r2, [r3, #0]
+ /* place for user code */
+}
+ 800060e: bf00 nop
+ 8000610: 3714 adds r7, #20
+ 8000612: 46bd mov sp, r7
+ 8000614: f85d 7b04 ldr.w r7, [sp], #4
+ 8000618: 4770 bx lr
+ 800061a: bf00 nop
+ 800061c: 2000002c .word 0x2000002c
+ 8000620: 20000080 .word 0x20000080
+
+08000624 :
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ 8000624: b5b0 push {r4, r5, r7, lr}
+ 8000626: b08e sub sp, #56 ; 0x38
+ 8000628: af00 add r7, sp, #0
+ /* MCU Configuration--------------------------------------------------------*/
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+ 800062a: f000 f91d bl 8000868
+ /* Configure the system clock */
+ SystemClock_Config();
+ 800062e: f7ff ff71 bl 8000514
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+ 8000632: f000 f82f bl 8000694
+
+ /* Create the thread(s) */
+ /* definition and creation of defaultTask */
+ osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 128);
+ 8000636: 4b13 ldr r3, [pc, #76] ; (8000684 )
+ 8000638: f107 041c add.w r4, r7, #28
+ 800063c: 461d mov r5, r3
+ 800063e: cd0f ldmia r5!, {r0, r1, r2, r3}
+ 8000640: c40f stmia r4!, {r0, r1, r2, r3}
+ 8000642: e895 0007 ldmia.w r5, {r0, r1, r2}
+ 8000646: e884 0007 stmia.w r4, {r0, r1, r2}
+ defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
+ 800064a: f107 031c add.w r3, r7, #28
+ 800064e: 2100 movs r1, #0
+ 8000650: 4618 mov r0, r3
+ 8000652: f001 f9e2 bl 8001a1a
+ 8000656: 4603 mov r3, r0
+ 8000658: 4a0b ldr r2, [pc, #44] ; (8000688 )
+ 800065a: 6013 str r3, [r2, #0]
+
+ /* definition and creation of BlinkLED */
+ osThreadDef(blinkaled, StartTask02, osPriorityIdle, 0, 128);
+ 800065c: 4b0b ldr r3, [pc, #44] ; (800068c )
+ 800065e: 463c mov r4, r7
+ 8000660: 461d mov r5, r3
+ 8000662: cd0f ldmia r5!, {r0, r1, r2, r3}
+ 8000664: c40f stmia r4!, {r0, r1, r2, r3}
+ 8000666: e895 0007 ldmia.w r5, {r0, r1, r2}
+ 800066a: e884 0007 stmia.w r4, {r0, r1, r2}
+ BlinkLEDHandle = osThreadCreate(osThread(blinkaled), NULL);
+ 800066e: 463b mov r3, r7
+ 8000670: 2100 movs r1, #0
+ 8000672: 4618 mov r0, r3
+ 8000674: f001 f9d1 bl 8001a1a
+ 8000678: 4603 mov r3, r0
+ 800067a: 4a05 ldr r2, [pc, #20] ; (8000690 )
+ 800067c: 6013 str r3, [r2, #0]
+
+ /* Start scheduler */
+ osKernelStart();
+ 800067e: f001 f9c5 bl 8001a0c
+
+ /* We should never get here as control is now taken by the scheduler */
+ /* Infinite loop */
+
+ while (1)
+ 8000682: e7fe b.n 8000682
+ 8000684: 08002f34 .word 0x08002f34
+ 8000688: 20000280 .word 0x20000280
+ 800068c: 08002f50 .word 0x08002f50
+ 8000690: 20000284 .word 0x20000284
+
+08000694 :
+ * @param None
+ * @retval None
+ */
+
+static void MX_GPIO_Init(void)
+{
+ 8000694: b580 push {r7, lr}
+ 8000696: b086 sub sp, #24
+ 8000698: af00 add r7, sp, #0
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 800069a: 1d3b adds r3, r7, #4
+ 800069c: 2200 movs r2, #0
+ 800069e: 601a str r2, [r3, #0]
+ 80006a0: 605a str r2, [r3, #4]
+ 80006a2: 609a str r2, [r3, #8]
+ 80006a4: 60da str r2, [r3, #12]
+ 80006a6: 611a str r2, [r3, #16]
+
+ /* GPIO Ports Clock Enable */
+
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ 80006a8: 2300 movs r3, #0
+ 80006aa: 603b str r3, [r7, #0]
+ 80006ac: 4b10 ldr r3, [pc, #64] ; (80006f0 )
+ 80006ae: 6b1b ldr r3, [r3, #48] ; 0x30
+ 80006b0: 4a0f ldr r2, [pc, #60] ; (80006f0 )
+ 80006b2: f043 0301 orr.w r3, r3, #1
+ 80006b6: 6313 str r3, [r2, #48] ; 0x30
+ 80006b8: 4b0d ldr r3, [pc, #52] ; (80006f0 )
+ 80006ba: 6b1b ldr r3, [r3, #48] ; 0x30
+ 80006bc: f003 0301 and.w r3, r3, #1
+ 80006c0: 603b str r3, [r7, #0]
+ 80006c2: 683b ldr r3, [r7, #0]
+
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
+ 80006c4: 2200 movs r2, #0
+ 80006c6: 2120 movs r1, #32
+ 80006c8: 480a ldr r0, [pc, #40] ; (80006f4 )
+ 80006ca: f000 fbb9 bl 8000e40
+
+ /*Configure GPIO pin : LD2_Pin */
+ GPIO_InitStruct.Pin = LD2_Pin;
+ 80006ce: 2320 movs r3, #32
+ 80006d0: 607b str r3, [r7, #4]
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 80006d2: 2301 movs r3, #1
+ 80006d4: 60bb str r3, [r7, #8]
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 80006d6: 2300 movs r3, #0
+ 80006d8: 60fb str r3, [r7, #12]
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 80006da: 2300 movs r3, #0
+ 80006dc: 613b str r3, [r7, #16]
+ HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
+ 80006de: 1d3b adds r3, r7, #4
+ 80006e0: 4619 mov r1, r3
+ 80006e2: 4804 ldr r0, [pc, #16] ; (80006f4 )
+ 80006e4: f000 fa18 bl 8000b18
+
+}
+ 80006e8: bf00 nop
+ 80006ea: 3718 adds r7, #24
+ 80006ec: 46bd mov sp, r7
+ 80006ee: bd80 pop {r7, pc}
+ 80006f0: 40023800 .word 0x40023800
+ 80006f4: 40020000 .word 0x40020000
+
+080006f8 :
+ * @param argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void const * argument)
+{
+ 80006f8: b580 push {r7, lr}
+ 80006fa: b082 sub sp, #8
+ 80006fc: af00 add r7, sp, #0
+ 80006fe: 6078 str r0, [r7, #4]
+ /* USER CODE BEGIN 5 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1);
+ 8000700: 2001 movs r0, #1
+ 8000702: f001 f9d6 bl 8001ab2
+ 8000706: e7fb b.n 8000700
+
+08000708 :
+* @param argument: Not used
+* @retval None
+*/
+/* USER CODE END Header_StartTask02 */
+void StartTask02(void const * argument)
+{
+ 8000708: b580 push {r7, lr}
+ 800070a: b082 sub sp, #8
+ 800070c: af00 add r7, sp, #0
+ 800070e: 6078 str r0, [r7, #4]
+ /* USER CODE BEGIN StartTask02 */
+ /* Infinite loop */
+ for(;;)
+ {
+ blinkaled();
+ 8000710: f000 f802 bl 8000718
+ 8000714: e7fc b.n 8000710
+ ...
+
+08000718 :
+ * Blinks an LED connected to GPIOA Pin 5 by setting it high for 1 second and then low for 1 second.
+ * Parameters: None
+ * Returns: None
+ */
+void blinkaled(void)
+{
+ 8000718: b580 push {r7, lr}
+ 800071a: af00 add r7, sp, #0
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET);
+ 800071c: 2201 movs r2, #1
+ 800071e: 2120 movs r1, #32
+ 8000720: 4808 ldr r0, [pc, #32] ; (8000744 )
+ 8000722: f000 fb8d bl 8000e40
+ osDelay(1000);
+ 8000726: f44f 707a mov.w r0, #1000 ; 0x3e8
+ 800072a: f001 f9c2 bl 8001ab2
+ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET);
+ 800072e: 2200 movs r2, #0
+ 8000730: 2120 movs r1, #32
+ 8000732: 4804 ldr r0, [pc, #16] ; (8000744 )
+ 8000734: f000 fb84 bl 8000e40
+ osDelay(1000);
+ 8000738: f44f 707a mov.w r0, #1000 ; 0x3e8
+ 800073c: f001 f9b9 bl 8001ab2
+}
+ 8000740: bf00 nop
+ 8000742: bd80 pop {r7, pc}
+ 8000744: 40020000 .word 0x40020000
+
+08000748 :
+/* USER CODE END 0 */
+/**
+ * Initializes the Global MSP.
+ */
+void HAL_MspInit(void)
+{
+ 8000748: b580 push {r7, lr}
+ 800074a: b082 sub sp, #8
+ 800074c: af00 add r7, sp, #0
+ /* USER CODE BEGIN MspInit 0 */
+
+ /* USER CODE END MspInit 0 */
+
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 800074e: 2300 movs r3, #0
+ 8000750: 607b str r3, [r7, #4]
+ 8000752: 4b12 ldr r3, [pc, #72] ; (800079c )
+ 8000754: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8000756: 4a11 ldr r2, [pc, #68] ; (800079c )
+ 8000758: f443 4380 orr.w r3, r3, #16384 ; 0x4000
+ 800075c: 6453 str r3, [r2, #68] ; 0x44
+ 800075e: 4b0f ldr r3, [pc, #60] ; (800079c )
+ 8000760: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8000762: f403 4380 and.w r3, r3, #16384 ; 0x4000
+ 8000766: 607b str r3, [r7, #4]
+ 8000768: 687b ldr r3, [r7, #4]
+ __HAL_RCC_PWR_CLK_ENABLE();
+ 800076a: 2300 movs r3, #0
+ 800076c: 603b str r3, [r7, #0]
+ 800076e: 4b0b ldr r3, [pc, #44] ; (800079c )
+ 8000770: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8000772: 4a0a ldr r2, [pc, #40] ; (800079c )
+ 8000774: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 8000778: 6413 str r3, [r2, #64] ; 0x40
+ 800077a: 4b08 ldr r3, [pc, #32] ; (800079c )
+ 800077c: 6c1b ldr r3, [r3, #64] ; 0x40
+ 800077e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8000782: 603b str r3, [r7, #0]
+ 8000784: 683b ldr r3, [r7, #0]
+
+ /* System interrupt init*/
+ /* PendSV_IRQn interrupt configuration */
+ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
+ 8000786: 2200 movs r2, #0
+ 8000788: 210f movs r1, #15
+ 800078a: f06f 0001 mvn.w r0, #1
+ 800078e: f000 f99a bl 8000ac6
+
+ /* USER CODE BEGIN MspInit 1 */
+
+ /* USER CODE END MspInit 1 */
+}
+ 8000792: bf00 nop
+ 8000794: 3708 adds r7, #8
+ 8000796: 46bd mov sp, r7
+ 8000798: bd80 pop {r7, pc}
+ 800079a: bf00 nop
+ 800079c: 40023800 .word 0x40023800
+
+080007a0 :
+/******************************************************************************/
+/**
+ * @brief This function handles Non maskable interrupt.
+ */
+void NMI_Handler(void)
+{
+ 80007a0: b480 push {r7}
+ 80007a2: af00 add r7, sp, #0
+ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+ /* USER CODE END NonMaskableInt_IRQn 0 */
+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+ while (1)
+ 80007a4: e7fe b.n 80007a4
+
+080007a6 :
+
+/**
+ * @brief This function handles Hard fault interrupt.
+ */
+void HardFault_Handler(void)
+{
+ 80007a6: b480 push {r7}
+ 80007a8: af00 add r7, sp, #0
+ /* USER CODE BEGIN HardFault_IRQn 0 */
+
+ /* USER CODE END HardFault_IRQn 0 */
+ while (1)
+ 80007aa: e7fe b.n 80007aa
+
+080007ac :
+
+/**
+ * @brief This function handles Memory management fault.
+ */
+void MemManage_Handler(void)
+{
+ 80007ac: b480 push {r7}
+ 80007ae: af00 add r7, sp, #0
+ /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+ /* USER CODE END MemoryManagement_IRQn 0 */
+ while (1)
+ 80007b0: e7fe b.n 80007b0
+
+080007b2 :
+
+/**
+ * @brief This function handles Pre-fetch fault, memory access fault.
+ */
+void BusFault_Handler(void)
+{
+ 80007b2: b480 push {r7}
+ 80007b4: af00 add r7, sp, #0
+ /* USER CODE BEGIN BusFault_IRQn 0 */
+
+ /* USER CODE END BusFault_IRQn 0 */
+ while (1)
+ 80007b6: e7fe b.n 80007b6
+
+080007b8 :
+
+/**
+ * @brief This function handles Undefined instruction or illegal state.
+ */
+void UsageFault_Handler(void)
+{
+ 80007b8: b480 push {r7}
+ 80007ba: af00 add r7, sp, #0
+ /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+ /* USER CODE END UsageFault_IRQn 0 */
+ while (1)
+ 80007bc: e7fe b.n 80007bc
+
+080007be :
+
+/**
+ * @brief This function handles Debug monitor.
+ */
+void DebugMon_Handler(void)
+{
+ 80007be: b480 push {r7}
+ 80007c0: af00 add r7, sp, #0
+
+ /* USER CODE END DebugMonitor_IRQn 0 */
+ /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+ /* USER CODE END DebugMonitor_IRQn 1 */
+}
+ 80007c2: bf00 nop
+ 80007c4: 46bd mov sp, r7
+ 80007c6: f85d 7b04 ldr.w r7, [sp], #4
+ 80007ca: 4770 bx lr
+
+080007cc :
+
+void Error_Handler(void)
+{
+ 80007cc: b480 push {r7}
+ 80007ce: af00 add r7, sp, #0
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+ 80007d0: b672 cpsid i
+}
+ 80007d2: bf00 nop
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ 80007d4: e7fe b.n 80007d4
+
+080007d6 :
+
+/**
+ * @brief This function handles System tick timer.
+ */
+void SysTick_Handler(void)
+{
+ 80007d6: b580 push {r7, lr}
+ 80007d8: af00 add r7, sp, #0
+ /* USER CODE BEGIN SysTick_IRQn 0 */
+
+ /* USER CODE END SysTick_IRQn 0 */
+ HAL_IncTick();
+ 80007da: f000 f897 bl 800090c
+#if (INCLUDE_xTaskGetSchedulerState == 1 )
+ if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED)
+ 80007de: f001 feeb bl 80025b8
+ 80007e2: 4603 mov r3, r0
+ 80007e4: 2b01 cmp r3, #1
+ 80007e6: d001 beq.n 80007ec
+ {
+#endif /* INCLUDE_xTaskGetSchedulerState */
+ xPortSysTickHandler();
+ 80007e8: f002 f926 bl 8002a38
+ }
+#endif /* INCLUDE_xTaskGetSchedulerState */
+ /* USER CODE BEGIN SysTick_IRQn 1 */
+
+ /* USER CODE END SysTick_IRQn 1 */
+}
+ 80007ec: bf00 nop
+ 80007ee: bd80 pop {r7, pc}
+
+080007f0 :
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ 80007f0: b480 push {r7}
+ 80007f2: af00 add r7, sp, #0
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ 80007f4: 4b06 ldr r3, [pc, #24] ; (8000810 )
+ 80007f6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 80007fa: 4a05 ldr r2, [pc, #20] ; (8000810 )
+ 80007fc: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
+ 8000800: f8c2 3088 str.w r3, [r2, #136] ; 0x88
+
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+ 8000804: bf00 nop
+ 8000806: 46bd mov sp, r7
+ 8000808: f85d 7b04 ldr.w r7, [sp], #4
+ 800080c: 4770 bx lr
+ 800080e: bf00 nop
+ 8000810: e000ed00 .word 0xe000ed00
+
+08000814 :
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+ 8000814: f8df d034 ldr.w sp, [pc, #52] ; 800084c
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ 8000818: 480d ldr r0, [pc, #52] ; (8000850 )
+ ldr r1, =_edata
+ 800081a: 490e ldr r1, [pc, #56] ; (8000854 )
+ ldr r2, =_sidata
+ 800081c: 4a0e ldr r2, [pc, #56] ; (8000858 )
+ movs r3, #0
+ 800081e: 2300 movs r3, #0
+ b LoopCopyDataInit
+ 8000820: e002 b.n 8000828
+
+08000822 :
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ 8000822: 58d4 ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ 8000824: 50c4 str r4, [r0, r3]
+ adds r3, r3, #4
+ 8000826: 3304 adds r3, #4
+
+08000828 :
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ 8000828: 18c4 adds r4, r0, r3
+ cmp r4, r1
+ 800082a: 428c cmp r4, r1
+ bcc CopyDataInit
+ 800082c: d3f9 bcc.n 8000822
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ 800082e: 4a0b ldr r2, [pc, #44] ; (800085c )
+ ldr r4, =_ebss
+ 8000830: 4c0b ldr r4, [pc, #44] ; (8000860 )
+ movs r3, #0
+ 8000832: 2300 movs r3, #0
+ b LoopFillZerobss
+ 8000834: e001 b.n 800083a
+
+08000836 :
+
+FillZerobss:
+ str r3, [r2]
+ 8000836: 6013 str r3, [r2, #0]
+ adds r2, r2, #4
+ 8000838: 3204 adds r2, #4
+
+0800083a :
+
+LoopFillZerobss:
+ cmp r2, r4
+ 800083a: 42a2 cmp r2, r4
+ bcc FillZerobss
+ 800083c: d3fb bcc.n 8000836
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+ 800083e: f7ff ffd7 bl 80007f0
+/* Call static constructors */
+ bl __libc_init_array
+ 8000842: f002 fb33 bl 8002eac <__libc_init_array>
+/* Call the application's entry point.*/
+ bl main
+ 8000846: f7ff feed bl 8000624
+ bx lr
+ 800084a: 4770 bx lr
+ ldr sp, =_estack /* set stack pointer */
+ 800084c: 20020000 .word 0x20020000
+ ldr r0, =_sdata
+ 8000850: 20000000 .word 0x20000000
+ ldr r1, =_edata
+ 8000854: 20000010 .word 0x20000010
+ ldr r2, =_sidata
+ 8000858: 08002f94 .word 0x08002f94
+ ldr r2, =_sbss
+ 800085c: 20000010 .word 0x20000010
+ ldr r4, =_ebss
+ 8000860: 20003fe0 .word 0x20003fe0
+
+08000864 :
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ 8000864: e7fe b.n 8000864
+ ...
+
+08000868 :
+ * need to ensure that the SysTick time base is always set to 1 millisecond
+ * to have correct HAL operation.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_Init(void)
+{
+ 8000868: b580 push {r7, lr}
+ 800086a: af00 add r7, sp, #0
+ /* Configure Flash prefetch, Instruction cache, Data cache */
+#if (INSTRUCTION_CACHE_ENABLE != 0U)
+ __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+ 800086c: 4b0e ldr r3, [pc, #56] ; (80008a8 )
+ 800086e: 681b ldr r3, [r3, #0]
+ 8000870: 4a0d ldr r2, [pc, #52] ; (80008a8 )
+ 8000872: f443 7300 orr.w r3, r3, #512 ; 0x200
+ 8000876: 6013 str r3, [r2, #0]
+#endif /* INSTRUCTION_CACHE_ENABLE */
+
+#if (DATA_CACHE_ENABLE != 0U)
+ __HAL_FLASH_DATA_CACHE_ENABLE();
+ 8000878: 4b0b ldr r3, [pc, #44] ; (80008a8 )
+ 800087a: 681b ldr r3, [r3, #0]
+ 800087c: 4a0a ldr r2, [pc, #40] ; (80008a8 )
+ 800087e: f443 6380 orr.w r3, r3, #1024 ; 0x400
+ 8000882: 6013 str r3, [r2, #0]
+#endif /* DATA_CACHE_ENABLE */
+
+#if (PREFETCH_ENABLE != 0U)
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+ 8000884: 4b08 ldr r3, [pc, #32] ; (80008a8 )
+ 8000886: 681b ldr r3, [r3, #0]
+ 8000888: 4a07 ldr r2, [pc, #28] ; (80008a8 )
+ 800088a: f443 7380 orr.w r3, r3, #256 ; 0x100
+ 800088e: 6013 str r3, [r2, #0]
+#endif /* PREFETCH_ENABLE */
+
+ /* Set Interrupt Group Priority */
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+ 8000890: 2003 movs r0, #3
+ 8000892: f000 f90d bl 8000ab0
+
+ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+ HAL_InitTick(TICK_INT_PRIORITY);
+ 8000896: 200f movs r0, #15
+ 8000898: f000 f808 bl 80008ac
+
+ /* Init the low level hardware */
+ HAL_MspInit();
+ 800089c: f7ff ff54 bl 8000748
+
+ /* Return function status */
+ return HAL_OK;
+ 80008a0: 2300 movs r3, #0
+}
+ 80008a2: 4618 mov r0, r3
+ 80008a4: bd80 pop {r7, pc}
+ 80008a6: bf00 nop
+ 80008a8: 40023c00 .word 0x40023c00
+
+080008ac :
+ * implementation in user file.
+ * @param TickPriority Tick interrupt priority.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ 80008ac: b580 push {r7, lr}
+ 80008ae: b082 sub sp, #8
+ 80008b0: af00 add r7, sp, #0
+ 80008b2: 6078 str r0, [r7, #4]
+ /* Configure the SysTick to have interrupt in 1ms time basis*/
+ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
+ 80008b4: 4b12 ldr r3, [pc, #72] ; (8000900 )
+ 80008b6: 681a ldr r2, [r3, #0]
+ 80008b8: 4b12 ldr r3, [pc, #72] ; (8000904 )
+ 80008ba: 781b ldrb r3, [r3, #0]
+ 80008bc: 4619 mov r1, r3
+ 80008be: f44f 737a mov.w r3, #1000 ; 0x3e8
+ 80008c2: fbb3 f3f1 udiv r3, r3, r1
+ 80008c6: fbb2 f3f3 udiv r3, r2, r3
+ 80008ca: 4618 mov r0, r3
+ 80008cc: f000 f917 bl 8000afe
+ 80008d0: 4603 mov r3, r0
+ 80008d2: 2b00 cmp r3, #0
+ 80008d4: d001 beq.n 80008da
+ {
+ return HAL_ERROR;
+ 80008d6: 2301 movs r3, #1
+ 80008d8: e00e b.n 80008f8
+ }
+
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ 80008da: 687b ldr r3, [r7, #4]
+ 80008dc: 2b0f cmp r3, #15
+ 80008de: d80a bhi.n 80008f6
+ {
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ 80008e0: 2200 movs r2, #0
+ 80008e2: 6879 ldr r1, [r7, #4]
+ 80008e4: f04f 30ff mov.w r0, #4294967295
+ 80008e8: f000 f8ed bl 8000ac6
+ uwTickPrio = TickPriority;
+ 80008ec: 4a06 ldr r2, [pc, #24] ; (8000908 )
+ 80008ee: 687b ldr r3, [r7, #4]
+ 80008f0: 6013 str r3, [r2, #0]
+ {
+ return HAL_ERROR;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ 80008f2: 2300 movs r3, #0
+ 80008f4: e000 b.n 80008f8
+ return HAL_ERROR;
+ 80008f6: 2301 movs r3, #1
+}
+ 80008f8: 4618 mov r0, r3
+ 80008fa: 3708 adds r7, #8
+ 80008fc: 46bd mov sp, r7
+ 80008fe: bd80 pop {r7, pc}
+ 8000900: 20000000 .word 0x20000000
+ 8000904: 20000008 .word 0x20000008
+ 8000908: 20000004 .word 0x20000004
+
+0800090c :
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_IncTick(void)
+{
+ 800090c: b480 push {r7}
+ 800090e: af00 add r7, sp, #0
+ uwTick += uwTickFreq;
+ 8000910: 4b06 ldr r3, [pc, #24] ; (800092c )
+ 8000912: 781b ldrb r3, [r3, #0]
+ 8000914: 461a mov r2, r3
+ 8000916: 4b06 ldr r3, [pc, #24] ; (8000930 )
+ 8000918: 681b ldr r3, [r3, #0]
+ 800091a: 4413 add r3, r2
+ 800091c: 4a04 ldr r2, [pc, #16] ; (8000930 )
+ 800091e: 6013 str r3, [r2, #0]
+}
+ 8000920: bf00 nop
+ 8000922: 46bd mov sp, r7
+ 8000924: f85d 7b04 ldr.w r7, [sp], #4
+ 8000928: 4770 bx lr
+ 800092a: bf00 nop
+ 800092c: 20000008 .word 0x20000008
+ 8000930: 20000288 .word 0x20000288
+
+08000934 :
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval tick value
+ */
+__weak uint32_t HAL_GetTick(void)
+{
+ 8000934: b480 push {r7}
+ 8000936: af00 add r7, sp, #0
+ return uwTick;
+ 8000938: 4b03 ldr r3, [pc, #12] ; (8000948 )
+ 800093a: 681b ldr r3, [r3, #0]
+}
+ 800093c: 4618 mov r0, r3
+ 800093e: 46bd mov sp, r7
+ 8000940: f85d 7b04 ldr.w r7, [sp], #4
+ 8000944: 4770 bx lr
+ 8000946: bf00 nop
+ 8000948: 20000288 .word 0x20000288
+
+0800094c <__NVIC_SetPriorityGrouping>:
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ 800094c: b480 push {r7}
+ 800094e: b085 sub sp, #20
+ 8000950: af00 add r7, sp, #0
+ 8000952: 6078 str r0, [r7, #4]
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ 8000954: 687b ldr r3, [r7, #4]
+ 8000956: f003 0307 and.w r3, r3, #7
+ 800095a: 60fb str r3, [r7, #12]
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ 800095c: 4b0c ldr r3, [pc, #48] ; (8000990 <__NVIC_SetPriorityGrouping+0x44>)
+ 800095e: 68db ldr r3, [r3, #12]
+ 8000960: 60bb str r3, [r7, #8]
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ 8000962: 68ba ldr r2, [r7, #8]
+ 8000964: f64f 03ff movw r3, #63743 ; 0xf8ff
+ 8000968: 4013 ands r3, r2
+ 800096a: 60bb str r3, [r7, #8]
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ 800096c: 68fb ldr r3, [r7, #12]
+ 800096e: 021a lsls r2, r3, #8
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ 8000970: 68bb ldr r3, [r7, #8]
+ 8000972: 4313 orrs r3, r2
+ reg_value = (reg_value |
+ 8000974: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
+ 8000978: f443 3300 orr.w r3, r3, #131072 ; 0x20000
+ 800097c: 60bb str r3, [r7, #8]
+ SCB->AIRCR = reg_value;
+ 800097e: 4a04 ldr r2, [pc, #16] ; (8000990 <__NVIC_SetPriorityGrouping+0x44>)
+ 8000980: 68bb ldr r3, [r7, #8]
+ 8000982: 60d3 str r3, [r2, #12]
+}
+ 8000984: bf00 nop
+ 8000986: 3714 adds r7, #20
+ 8000988: 46bd mov sp, r7
+ 800098a: f85d 7b04 ldr.w r7, [sp], #4
+ 800098e: 4770 bx lr
+ 8000990: e000ed00 .word 0xe000ed00
+
+08000994 <__NVIC_GetPriorityGrouping>:
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ 8000994: b480 push {r7}
+ 8000996: af00 add r7, sp, #0
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+ 8000998: 4b04 ldr r3, [pc, #16] ; (80009ac <__NVIC_GetPriorityGrouping+0x18>)
+ 800099a: 68db ldr r3, [r3, #12]
+ 800099c: 0a1b lsrs r3, r3, #8
+ 800099e: f003 0307 and.w r3, r3, #7
+}
+ 80009a2: 4618 mov r0, r3
+ 80009a4: 46bd mov sp, r7
+ 80009a6: f85d 7b04 ldr.w r7, [sp], #4
+ 80009aa: 4770 bx lr
+ 80009ac: e000ed00 .word 0xe000ed00
+
+080009b0 <__NVIC_SetPriority>:
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ 80009b0: b480 push {r7}
+ 80009b2: b083 sub sp, #12
+ 80009b4: af00 add r7, sp, #0
+ 80009b6: 4603 mov r3, r0
+ 80009b8: 6039 str r1, [r7, #0]
+ 80009ba: 71fb strb r3, [r7, #7]
+ if ((int32_t)(IRQn) >= 0)
+ 80009bc: f997 3007 ldrsb.w r3, [r7, #7]
+ 80009c0: 2b00 cmp r3, #0
+ 80009c2: db0a blt.n 80009da <__NVIC_SetPriority+0x2a>
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ 80009c4: 683b ldr r3, [r7, #0]
+ 80009c6: b2da uxtb r2, r3
+ 80009c8: 490c ldr r1, [pc, #48] ; (80009fc <__NVIC_SetPriority+0x4c>)
+ 80009ca: f997 3007 ldrsb.w r3, [r7, #7]
+ 80009ce: 0112 lsls r2, r2, #4
+ 80009d0: b2d2 uxtb r2, r2
+ 80009d2: 440b add r3, r1
+ 80009d4: f883 2300 strb.w r2, [r3, #768] ; 0x300
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+ 80009d8: e00a b.n 80009f0 <__NVIC_SetPriority+0x40>
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ 80009da: 683b ldr r3, [r7, #0]
+ 80009dc: b2da uxtb r2, r3
+ 80009de: 4908 ldr r1, [pc, #32] ; (8000a00 <__NVIC_SetPriority+0x50>)
+ 80009e0: 79fb ldrb r3, [r7, #7]
+ 80009e2: f003 030f and.w r3, r3, #15
+ 80009e6: 3b04 subs r3, #4
+ 80009e8: 0112 lsls r2, r2, #4
+ 80009ea: b2d2 uxtb r2, r2
+ 80009ec: 440b add r3, r1
+ 80009ee: 761a strb r2, [r3, #24]
+}
+ 80009f0: bf00 nop
+ 80009f2: 370c adds r7, #12
+ 80009f4: 46bd mov sp, r7
+ 80009f6: f85d 7b04 ldr.w r7, [sp], #4
+ 80009fa: 4770 bx lr
+ 80009fc: e000e100 .word 0xe000e100
+ 8000a00: e000ed00 .word 0xe000ed00
+
+08000a04 :
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ 8000a04: b480 push {r7}
+ 8000a06: b089 sub sp, #36 ; 0x24
+ 8000a08: af00 add r7, sp, #0
+ 8000a0a: 60f8 str r0, [r7, #12]
+ 8000a0c: 60b9 str r1, [r7, #8]
+ 8000a0e: 607a str r2, [r7, #4]
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ 8000a10: 68fb ldr r3, [r7, #12]
+ 8000a12: f003 0307 and.w r3, r3, #7
+ 8000a16: 61fb str r3, [r7, #28]
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ 8000a18: 69fb ldr r3, [r7, #28]
+ 8000a1a: f1c3 0307 rsb r3, r3, #7
+ 8000a1e: 2b04 cmp r3, #4
+ 8000a20: bf28 it cs
+ 8000a22: 2304 movcs r3, #4
+ 8000a24: 61bb str r3, [r7, #24]
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+ 8000a26: 69fb ldr r3, [r7, #28]
+ 8000a28: 3304 adds r3, #4
+ 8000a2a: 2b06 cmp r3, #6
+ 8000a2c: d902 bls.n 8000a34
+ 8000a2e: 69fb ldr r3, [r7, #28]
+ 8000a30: 3b03 subs r3, #3
+ 8000a32: e000 b.n 8000a36
+ 8000a34: 2300 movs r3, #0
+ 8000a36: 617b str r3, [r7, #20]
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ 8000a38: f04f 32ff mov.w r2, #4294967295
+ 8000a3c: 69bb ldr r3, [r7, #24]
+ 8000a3e: fa02 f303 lsl.w r3, r2, r3
+ 8000a42: 43da mvns r2, r3
+ 8000a44: 68bb ldr r3, [r7, #8]
+ 8000a46: 401a ands r2, r3
+ 8000a48: 697b ldr r3, [r7, #20]
+ 8000a4a: 409a lsls r2, r3
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ 8000a4c: f04f 31ff mov.w r1, #4294967295
+ 8000a50: 697b ldr r3, [r7, #20]
+ 8000a52: fa01 f303 lsl.w r3, r1, r3
+ 8000a56: 43d9 mvns r1, r3
+ 8000a58: 687b ldr r3, [r7, #4]
+ 8000a5a: 400b ands r3, r1
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ 8000a5c: 4313 orrs r3, r2
+ );
+}
+ 8000a5e: 4618 mov r0, r3
+ 8000a60: 3724 adds r7, #36 ; 0x24
+ 8000a62: 46bd mov sp, r7
+ 8000a64: f85d 7b04 ldr.w r7, [sp], #4
+ 8000a68: 4770 bx lr
+ ...
+
+08000a6c :
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ 8000a6c: b580 push {r7, lr}
+ 8000a6e: b082 sub sp, #8
+ 8000a70: af00 add r7, sp, #0
+ 8000a72: 6078 str r0, [r7, #4]
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ 8000a74: 687b ldr r3, [r7, #4]
+ 8000a76: 3b01 subs r3, #1
+ 8000a78: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
+ 8000a7c: d301 bcc.n 8000a82
+ {
+ return (1UL); /* Reload value impossible */
+ 8000a7e: 2301 movs r3, #1
+ 8000a80: e00f b.n 8000aa2
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ 8000a82: 4a0a ldr r2, [pc, #40] ; (8000aac )
+ 8000a84: 687b ldr r3, [r7, #4]
+ 8000a86: 3b01 subs r3, #1
+ 8000a88: 6053 str r3, [r2, #4]
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ 8000a8a: 210f movs r1, #15
+ 8000a8c: f04f 30ff mov.w r0, #4294967295
+ 8000a90: f7ff ff8e bl 80009b0 <__NVIC_SetPriority>
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ 8000a94: 4b05 ldr r3, [pc, #20] ; (8000aac )
+ 8000a96: 2200 movs r2, #0
+ 8000a98: 609a str r2, [r3, #8]
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ 8000a9a: 4b04 ldr r3, [pc, #16] ; (8000aac )
+ 8000a9c: 2207 movs r2, #7
+ 8000a9e: 601a str r2, [r3, #0]
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+ 8000aa0: 2300 movs r3, #0
+}
+ 8000aa2: 4618 mov r0, r3
+ 8000aa4: 3708 adds r7, #8
+ 8000aa6: 46bd mov sp, r7
+ 8000aa8: bd80 pop {r7, pc}
+ 8000aaa: bf00 nop
+ 8000aac: e000e010 .word 0xe000e010
+
+08000ab0 :
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
+ * The pending IRQ priority will be managed only by the subpriority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ 8000ab0: b580 push {r7, lr}
+ 8000ab2: b082 sub sp, #8
+ 8000ab4: af00 add r7, sp, #0
+ 8000ab6: 6078 str r0, [r7, #4]
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+ NVIC_SetPriorityGrouping(PriorityGroup);
+ 8000ab8: 6878 ldr r0, [r7, #4]
+ 8000aba: f7ff ff47 bl 800094c <__NVIC_SetPriorityGrouping>
+}
+ 8000abe: bf00 nop
+ 8000ac0: 3708 adds r7, #8
+ 8000ac2: 46bd mov sp, r7
+ 8000ac4: bd80 pop {r7, pc}
+
+08000ac6 :
+ * This parameter can be a value between 0 and 15
+ * A lower priority value indicates a higher priority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ 8000ac6: b580 push {r7, lr}
+ 8000ac8: b086 sub sp, #24
+ 8000aca: af00 add r7, sp, #0
+ 8000acc: 4603 mov r3, r0
+ 8000ace: 60b9 str r1, [r7, #8]
+ 8000ad0: 607a str r2, [r7, #4]
+ 8000ad2: 73fb strb r3, [r7, #15]
+ uint32_t prioritygroup = 0x00U;
+ 8000ad4: 2300 movs r3, #0
+ 8000ad6: 617b str r3, [r7, #20]
+
+ /* Check the parameters */
+ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+ prioritygroup = NVIC_GetPriorityGrouping();
+ 8000ad8: f7ff ff5c bl 8000994 <__NVIC_GetPriorityGrouping>
+ 8000adc: 6178 str r0, [r7, #20]
+
+ NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+ 8000ade: 687a ldr r2, [r7, #4]
+ 8000ae0: 68b9 ldr r1, [r7, #8]
+ 8000ae2: 6978 ldr r0, [r7, #20]
+ 8000ae4: f7ff ff8e bl 8000a04
+ 8000ae8: 4602 mov r2, r0
+ 8000aea: f997 300f ldrsb.w r3, [r7, #15]
+ 8000aee: 4611 mov r1, r2
+ 8000af0: 4618 mov r0, r3
+ 8000af2: f7ff ff5d bl 80009b0 <__NVIC_SetPriority>
+}
+ 8000af6: bf00 nop
+ 8000af8: 3718 adds r7, #24
+ 8000afa: 46bd mov sp, r7
+ 8000afc: bd80 pop {r7, pc}
+
+08000afe :
+ * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
+ * @retval status: - 0 Function succeeded.
+ * - 1 Function failed.
+ */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ 8000afe: b580 push {r7, lr}
+ 8000b00: b082 sub sp, #8
+ 8000b02: af00 add r7, sp, #0
+ 8000b04: 6078 str r0, [r7, #4]
+ return SysTick_Config(TicksNumb);
+ 8000b06: 6878 ldr r0, [r7, #4]
+ 8000b08: f7ff ffb0 bl 8000a6c
+ 8000b0c: 4603 mov r3, r0
+}
+ 8000b0e: 4618 mov r0, r3
+ 8000b10: 3708 adds r7, #8
+ 8000b12: 46bd mov sp, r7
+ 8000b14: bd80 pop {r7, pc}
+ ...
+
+08000b18 :
+ * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+ * the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+ 8000b18: b480 push {r7}
+ 8000b1a: b089 sub sp, #36 ; 0x24
+ 8000b1c: af00 add r7, sp, #0
+ 8000b1e: 6078 str r0, [r7, #4]
+ 8000b20: 6039 str r1, [r7, #0]
+ uint32_t position;
+ uint32_t ioposition = 0x00U;
+ 8000b22: 2300 movs r3, #0
+ 8000b24: 617b str r3, [r7, #20]
+ uint32_t iocurrent = 0x00U;
+ 8000b26: 2300 movs r3, #0
+ 8000b28: 613b str r3, [r7, #16]
+ uint32_t temp = 0x00U;
+ 8000b2a: 2300 movs r3, #0
+ 8000b2c: 61bb str r3, [r7, #24]
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+ assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+
+ /* Configure the port pins */
+ for(position = 0U; position < GPIO_NUMBER; position++)
+ 8000b2e: 2300 movs r3, #0
+ 8000b30: 61fb str r3, [r7, #28]
+ 8000b32: e165 b.n 8000e00
+ {
+ /* Get the IO position */
+ ioposition = 0x01U << position;
+ 8000b34: 2201 movs r2, #1
+ 8000b36: 69fb ldr r3, [r7, #28]
+ 8000b38: fa02 f303 lsl.w r3, r2, r3
+ 8000b3c: 617b str r3, [r7, #20]
+ /* Get the current IO position */
+ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
+ 8000b3e: 683b ldr r3, [r7, #0]
+ 8000b40: 681b ldr r3, [r3, #0]
+ 8000b42: 697a ldr r2, [r7, #20]
+ 8000b44: 4013 ands r3, r2
+ 8000b46: 613b str r3, [r7, #16]
+
+ if(iocurrent == ioposition)
+ 8000b48: 693a ldr r2, [r7, #16]
+ 8000b4a: 697b ldr r3, [r7, #20]
+ 8000b4c: 429a cmp r2, r3
+ 8000b4e: f040 8154 bne.w 8000dfa
+ {
+ /*--------------------- GPIO Mode Configuration ------------------------*/
+ /* In case of Output or Alternate function mode selection */
+ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
+ 8000b52: 683b ldr r3, [r7, #0]
+ 8000b54: 685b ldr r3, [r3, #4]
+ 8000b56: f003 0303 and.w r3, r3, #3
+ 8000b5a: 2b01 cmp r3, #1
+ 8000b5c: d005 beq.n 8000b6a
+ (GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
+ 8000b5e: 683b ldr r3, [r7, #0]
+ 8000b60: 685b ldr r3, [r3, #4]
+ 8000b62: f003 0303 and.w r3, r3, #3
+ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
+ 8000b66: 2b02 cmp r3, #2
+ 8000b68: d130 bne.n 8000bcc
+ {
+ /* Check the Speed parameter */
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ /* Configure the IO Speed */
+ temp = GPIOx->OSPEEDR;
+ 8000b6a: 687b ldr r3, [r7, #4]
+ 8000b6c: 689b ldr r3, [r3, #8]
+ 8000b6e: 61bb str r3, [r7, #24]
+ temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
+ 8000b70: 69fb ldr r3, [r7, #28]
+ 8000b72: 005b lsls r3, r3, #1
+ 8000b74: 2203 movs r2, #3
+ 8000b76: fa02 f303 lsl.w r3, r2, r3
+ 8000b7a: 43db mvns r3, r3
+ 8000b7c: 69ba ldr r2, [r7, #24]
+ 8000b7e: 4013 ands r3, r2
+ 8000b80: 61bb str r3, [r7, #24]
+ temp |= (GPIO_Init->Speed << (position * 2U));
+ 8000b82: 683b ldr r3, [r7, #0]
+ 8000b84: 68da ldr r2, [r3, #12]
+ 8000b86: 69fb ldr r3, [r7, #28]
+ 8000b88: 005b lsls r3, r3, #1
+ 8000b8a: fa02 f303 lsl.w r3, r2, r3
+ 8000b8e: 69ba ldr r2, [r7, #24]
+ 8000b90: 4313 orrs r3, r2
+ 8000b92: 61bb str r3, [r7, #24]
+ GPIOx->OSPEEDR = temp;
+ 8000b94: 687b ldr r3, [r7, #4]
+ 8000b96: 69ba ldr r2, [r7, #24]
+ 8000b98: 609a str r2, [r3, #8]
+
+ /* Configure the IO Output Type */
+ temp = GPIOx->OTYPER;
+ 8000b9a: 687b ldr r3, [r7, #4]
+ 8000b9c: 685b ldr r3, [r3, #4]
+ 8000b9e: 61bb str r3, [r7, #24]
+ temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ 8000ba0: 2201 movs r2, #1
+ 8000ba2: 69fb ldr r3, [r7, #28]
+ 8000ba4: fa02 f303 lsl.w r3, r2, r3
+ 8000ba8: 43db mvns r3, r3
+ 8000baa: 69ba ldr r2, [r7, #24]
+ 8000bac: 4013 ands r3, r2
+ 8000bae: 61bb str r3, [r7, #24]
+ temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
+ 8000bb0: 683b ldr r3, [r7, #0]
+ 8000bb2: 685b ldr r3, [r3, #4]
+ 8000bb4: 091b lsrs r3, r3, #4
+ 8000bb6: f003 0201 and.w r2, r3, #1
+ 8000bba: 69fb ldr r3, [r7, #28]
+ 8000bbc: fa02 f303 lsl.w r3, r2, r3
+ 8000bc0: 69ba ldr r2, [r7, #24]
+ 8000bc2: 4313 orrs r3, r2
+ 8000bc4: 61bb str r3, [r7, #24]
+ GPIOx->OTYPER = temp;
+ 8000bc6: 687b ldr r3, [r7, #4]
+ 8000bc8: 69ba ldr r2, [r7, #24]
+ 8000bca: 605a str r2, [r3, #4]
+ }
+
+ if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
+ 8000bcc: 683b ldr r3, [r7, #0]
+ 8000bce: 685b ldr r3, [r3, #4]
+ 8000bd0: f003 0303 and.w r3, r3, #3
+ 8000bd4: 2b03 cmp r3, #3
+ 8000bd6: d017 beq.n 8000c08
+ {
+ /* Check the parameters */
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+ /* Activate the Pull-up or Pull down resistor for the current IO */
+ temp = GPIOx->PUPDR;
+ 8000bd8: 687b ldr r3, [r7, #4]
+ 8000bda: 68db ldr r3, [r3, #12]
+ 8000bdc: 61bb str r3, [r7, #24]
+ temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
+ 8000bde: 69fb ldr r3, [r7, #28]
+ 8000be0: 005b lsls r3, r3, #1
+ 8000be2: 2203 movs r2, #3
+ 8000be4: fa02 f303 lsl.w r3, r2, r3
+ 8000be8: 43db mvns r3, r3
+ 8000bea: 69ba ldr r2, [r7, #24]
+ 8000bec: 4013 ands r3, r2
+ 8000bee: 61bb str r3, [r7, #24]
+ temp |= ((GPIO_Init->Pull) << (position * 2U));
+ 8000bf0: 683b ldr r3, [r7, #0]
+ 8000bf2: 689a ldr r2, [r3, #8]
+ 8000bf4: 69fb ldr r3, [r7, #28]
+ 8000bf6: 005b lsls r3, r3, #1
+ 8000bf8: fa02 f303 lsl.w r3, r2, r3
+ 8000bfc: 69ba ldr r2, [r7, #24]
+ 8000bfe: 4313 orrs r3, r2
+ 8000c00: 61bb str r3, [r7, #24]
+ GPIOx->PUPDR = temp;
+ 8000c02: 687b ldr r3, [r7, #4]
+ 8000c04: 69ba ldr r2, [r7, #24]
+ 8000c06: 60da str r2, [r3, #12]
+ }
+
+ /* In case of Alternate function mode selection */
+ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
+ 8000c08: 683b ldr r3, [r7, #0]
+ 8000c0a: 685b ldr r3, [r3, #4]
+ 8000c0c: f003 0303 and.w r3, r3, #3
+ 8000c10: 2b02 cmp r3, #2
+ 8000c12: d123 bne.n 8000c5c
+ {
+ /* Check the Alternate function parameter */
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+ /* Configure Alternate function mapped with the current IO */
+ temp = GPIOx->AFR[position >> 3U];
+ 8000c14: 69fb ldr r3, [r7, #28]
+ 8000c16: 08da lsrs r2, r3, #3
+ 8000c18: 687b ldr r3, [r7, #4]
+ 8000c1a: 3208 adds r2, #8
+ 8000c1c: f853 3022 ldr.w r3, [r3, r2, lsl #2]
+ 8000c20: 61bb str r3, [r7, #24]
+ temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+ 8000c22: 69fb ldr r3, [r7, #28]
+ 8000c24: f003 0307 and.w r3, r3, #7
+ 8000c28: 009b lsls r3, r3, #2
+ 8000c2a: 220f movs r2, #15
+ 8000c2c: fa02 f303 lsl.w r3, r2, r3
+ 8000c30: 43db mvns r3, r3
+ 8000c32: 69ba ldr r2, [r7, #24]
+ 8000c34: 4013 ands r3, r2
+ 8000c36: 61bb str r3, [r7, #24]
+ temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
+ 8000c38: 683b ldr r3, [r7, #0]
+ 8000c3a: 691a ldr r2, [r3, #16]
+ 8000c3c: 69fb ldr r3, [r7, #28]
+ 8000c3e: f003 0307 and.w r3, r3, #7
+ 8000c42: 009b lsls r3, r3, #2
+ 8000c44: fa02 f303 lsl.w r3, r2, r3
+ 8000c48: 69ba ldr r2, [r7, #24]
+ 8000c4a: 4313 orrs r3, r2
+ 8000c4c: 61bb str r3, [r7, #24]
+ GPIOx->AFR[position >> 3U] = temp;
+ 8000c4e: 69fb ldr r3, [r7, #28]
+ 8000c50: 08da lsrs r2, r3, #3
+ 8000c52: 687b ldr r3, [r7, #4]
+ 8000c54: 3208 adds r2, #8
+ 8000c56: 69b9 ldr r1, [r7, #24]
+ 8000c58: f843 1022 str.w r1, [r3, r2, lsl #2]
+ }
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ temp = GPIOx->MODER;
+ 8000c5c: 687b ldr r3, [r7, #4]
+ 8000c5e: 681b ldr r3, [r3, #0]
+ 8000c60: 61bb str r3, [r7, #24]
+ temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
+ 8000c62: 69fb ldr r3, [r7, #28]
+ 8000c64: 005b lsls r3, r3, #1
+ 8000c66: 2203 movs r2, #3
+ 8000c68: fa02 f303 lsl.w r3, r2, r3
+ 8000c6c: 43db mvns r3, r3
+ 8000c6e: 69ba ldr r2, [r7, #24]
+ 8000c70: 4013 ands r3, r2
+ 8000c72: 61bb str r3, [r7, #24]
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 8000c74: 683b ldr r3, [r7, #0]
+ 8000c76: 685b ldr r3, [r3, #4]
+ 8000c78: f003 0203 and.w r2, r3, #3
+ 8000c7c: 69fb ldr r3, [r7, #28]
+ 8000c7e: 005b lsls r3, r3, #1
+ 8000c80: fa02 f303 lsl.w r3, r2, r3
+ 8000c84: 69ba ldr r2, [r7, #24]
+ 8000c86: 4313 orrs r3, r2
+ 8000c88: 61bb str r3, [r7, #24]
+ GPIOx->MODER = temp;
+ 8000c8a: 687b ldr r3, [r7, #4]
+ 8000c8c: 69ba ldr r2, [r7, #24]
+ 8000c8e: 601a str r2, [r3, #0]
+
+ /*--------------------- EXTI Mode Configuration ------------------------*/
+ /* Configure the External Interrupt or event for the current IO */
+ if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
+ 8000c90: 683b ldr r3, [r7, #0]
+ 8000c92: 685b ldr r3, [r3, #4]
+ 8000c94: f403 3340 and.w r3, r3, #196608 ; 0x30000
+ 8000c98: 2b00 cmp r3, #0
+ 8000c9a: f000 80ae beq.w 8000dfa
+ {
+ /* Enable SYSCFG Clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 8000c9e: 2300 movs r3, #0
+ 8000ca0: 60fb str r3, [r7, #12]
+ 8000ca2: 4b5d ldr r3, [pc, #372] ; (8000e18 )
+ 8000ca4: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8000ca6: 4a5c ldr r2, [pc, #368] ; (8000e18 )
+ 8000ca8: f443 4380 orr.w r3, r3, #16384 ; 0x4000
+ 8000cac: 6453 str r3, [r2, #68] ; 0x44
+ 8000cae: 4b5a ldr r3, [pc, #360] ; (8000e18 )
+ 8000cb0: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8000cb2: f403 4380 and.w r3, r3, #16384 ; 0x4000
+ 8000cb6: 60fb str r3, [r7, #12]
+ 8000cb8: 68fb ldr r3, [r7, #12]
+
+ temp = SYSCFG->EXTICR[position >> 2U];
+ 8000cba: 4a58 ldr r2, [pc, #352] ; (8000e1c )
+ 8000cbc: 69fb ldr r3, [r7, #28]
+ 8000cbe: 089b lsrs r3, r3, #2
+ 8000cc0: 3302 adds r3, #2
+ 8000cc2: f852 3023 ldr.w r3, [r2, r3, lsl #2]
+ 8000cc6: 61bb str r3, [r7, #24]
+ temp &= ~(0x0FU << (4U * (position & 0x03U)));
+ 8000cc8: 69fb ldr r3, [r7, #28]
+ 8000cca: f003 0303 and.w r3, r3, #3
+ 8000cce: 009b lsls r3, r3, #2
+ 8000cd0: 220f movs r2, #15
+ 8000cd2: fa02 f303 lsl.w r3, r2, r3
+ 8000cd6: 43db mvns r3, r3
+ 8000cd8: 69ba ldr r2, [r7, #24]
+ 8000cda: 4013 ands r3, r2
+ 8000cdc: 61bb str r3, [r7, #24]
+ temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
+ 8000cde: 687b ldr r3, [r7, #4]
+ 8000ce0: 4a4f ldr r2, [pc, #316] ; (8000e20 )
+ 8000ce2: 4293 cmp r3, r2
+ 8000ce4: d025 beq.n 8000d32
+ 8000ce6: 687b ldr r3, [r7, #4]
+ 8000ce8: 4a4e ldr r2, [pc, #312] ; (8000e24 )
+ 8000cea: 4293 cmp r3, r2
+ 8000cec: d01f beq.n 8000d2e
+ 8000cee: 687b ldr r3, [r7, #4]
+ 8000cf0: 4a4d ldr r2, [pc, #308] ; (8000e28 )
+ 8000cf2: 4293 cmp r3, r2
+ 8000cf4: d019 beq.n 8000d2a
+ 8000cf6: 687b ldr r3, [r7, #4]
+ 8000cf8: 4a4c ldr r2, [pc, #304] ; (8000e2c )
+ 8000cfa: 4293 cmp r3, r2
+ 8000cfc: d013 beq.n 8000d26
+ 8000cfe: 687b ldr r3, [r7, #4]
+ 8000d00: 4a4b ldr r2, [pc, #300] ; (8000e30 )
+ 8000d02: 4293 cmp r3, r2
+ 8000d04: d00d beq.n 8000d22
+ 8000d06: 687b ldr r3, [r7, #4]
+ 8000d08: 4a4a ldr r2, [pc, #296] ; (8000e34 )
+ 8000d0a: 4293 cmp r3, r2
+ 8000d0c: d007 beq.n 8000d1e
+ 8000d0e: 687b ldr r3, [r7, #4]
+ 8000d10: 4a49 ldr r2, [pc, #292] ; (8000e38 )
+ 8000d12: 4293 cmp r3, r2
+ 8000d14: d101 bne.n 8000d1a
+ 8000d16: 2306 movs r3, #6
+ 8000d18: e00c b.n 8000d34
+ 8000d1a: 2307 movs r3, #7
+ 8000d1c: e00a b.n 8000d34
+ 8000d1e: 2305 movs r3, #5
+ 8000d20: e008 b.n 8000d34
+ 8000d22: 2304 movs r3, #4
+ 8000d24: e006 b.n 8000d34
+ 8000d26: 2303 movs r3, #3
+ 8000d28: e004 b.n 8000d34
+ 8000d2a: 2302 movs r3, #2
+ 8000d2c: e002 b.n 8000d34
+ 8000d2e: 2301 movs r3, #1
+ 8000d30: e000 b.n 8000d34
+ 8000d32: 2300 movs r3, #0
+ 8000d34: 69fa ldr r2, [r7, #28]
+ 8000d36: f002 0203 and.w r2, r2, #3
+ 8000d3a: 0092 lsls r2, r2, #2
+ 8000d3c: 4093 lsls r3, r2
+ 8000d3e: 69ba ldr r2, [r7, #24]
+ 8000d40: 4313 orrs r3, r2
+ 8000d42: 61bb str r3, [r7, #24]
+ SYSCFG->EXTICR[position >> 2U] = temp;
+ 8000d44: 4935 ldr r1, [pc, #212] ; (8000e1c )
+ 8000d46: 69fb ldr r3, [r7, #28]
+ 8000d48: 089b lsrs r3, r3, #2
+ 8000d4a: 3302 adds r3, #2
+ 8000d4c: 69ba ldr r2, [r7, #24]
+ 8000d4e: f841 2023 str.w r2, [r1, r3, lsl #2]
+
+ /* Clear Rising Falling edge configuration */
+ temp = EXTI->RTSR;
+ 8000d52: 4b3a ldr r3, [pc, #232] ; (8000e3c )
+ 8000d54: 689b ldr r3, [r3, #8]
+ 8000d56: 61bb str r3, [r7, #24]
+ temp &= ~((uint32_t)iocurrent);
+ 8000d58: 693b ldr r3, [r7, #16]
+ 8000d5a: 43db mvns r3, r3
+ 8000d5c: 69ba ldr r2, [r7, #24]
+ 8000d5e: 4013 ands r3, r2
+ 8000d60: 61bb str r3, [r7, #24]
+ if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
+ 8000d62: 683b ldr r3, [r7, #0]
+ 8000d64: 685b ldr r3, [r3, #4]
+ 8000d66: f403 1380 and.w r3, r3, #1048576 ; 0x100000
+ 8000d6a: 2b00 cmp r3, #0
+ 8000d6c: d003 beq.n 8000d76
+ {
+ temp |= iocurrent;
+ 8000d6e: 69ba ldr r2, [r7, #24]
+ 8000d70: 693b ldr r3, [r7, #16]
+ 8000d72: 4313 orrs r3, r2
+ 8000d74: 61bb str r3, [r7, #24]
+ }
+ EXTI->RTSR = temp;
+ 8000d76: 4a31 ldr r2, [pc, #196] ; (8000e3c )
+ 8000d78: 69bb ldr r3, [r7, #24]
+ 8000d7a: 6093 str r3, [r2, #8]
+
+ temp = EXTI->FTSR;
+ 8000d7c: 4b2f ldr r3, [pc, #188] ; (8000e3c )
+ 8000d7e: 68db ldr r3, [r3, #12]
+ 8000d80: 61bb str r3, [r7, #24]
+ temp &= ~((uint32_t)iocurrent);
+ 8000d82: 693b ldr r3, [r7, #16]
+ 8000d84: 43db mvns r3, r3
+ 8000d86: 69ba ldr r2, [r7, #24]
+ 8000d88: 4013 ands r3, r2
+ 8000d8a: 61bb str r3, [r7, #24]
+ if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
+ 8000d8c: 683b ldr r3, [r7, #0]
+ 8000d8e: 685b ldr r3, [r3, #4]
+ 8000d90: f403 1300 and.w r3, r3, #2097152 ; 0x200000
+ 8000d94: 2b00 cmp r3, #0
+ 8000d96: d003 beq.n 8000da0
+ {
+ temp |= iocurrent;
+ 8000d98: 69ba ldr r2, [r7, #24]
+ 8000d9a: 693b ldr r3, [r7, #16]
+ 8000d9c: 4313 orrs r3, r2
+ 8000d9e: 61bb str r3, [r7, #24]
+ }
+ EXTI->FTSR = temp;
+ 8000da0: 4a26 ldr r2, [pc, #152] ; (8000e3c )
+ 8000da2: 69bb ldr r3, [r7, #24]
+ 8000da4: 60d3 str r3, [r2, #12]
+
+ temp = EXTI->EMR;
+ 8000da6: 4b25 ldr r3, [pc, #148] ; (8000e3c )
+ 8000da8: 685b ldr r3, [r3, #4]
+ 8000daa: 61bb str r3, [r7, #24]
+ temp &= ~((uint32_t)iocurrent);
+ 8000dac: 693b ldr r3, [r7, #16]
+ 8000dae: 43db mvns r3, r3
+ 8000db0: 69ba ldr r2, [r7, #24]
+ 8000db2: 4013 ands r3, r2
+ 8000db4: 61bb str r3, [r7, #24]
+ if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
+ 8000db6: 683b ldr r3, [r7, #0]
+ 8000db8: 685b ldr r3, [r3, #4]
+ 8000dba: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 8000dbe: 2b00 cmp r3, #0
+ 8000dc0: d003 beq.n 8000dca
+ {
+ temp |= iocurrent;
+ 8000dc2: 69ba ldr r2, [r7, #24]
+ 8000dc4: 693b ldr r3, [r7, #16]
+ 8000dc6: 4313 orrs r3, r2
+ 8000dc8: 61bb str r3, [r7, #24]
+ }
+ EXTI->EMR = temp;
+ 8000dca: 4a1c ldr r2, [pc, #112] ; (8000e3c )
+ 8000dcc: 69bb ldr r3, [r7, #24]
+ 8000dce: 6053 str r3, [r2, #4]
+
+ /* Clear EXTI line configuration */
+ temp = EXTI->IMR;
+ 8000dd0: 4b1a ldr r3, [pc, #104] ; (8000e3c )
+ 8000dd2: 681b ldr r3, [r3, #0]
+ 8000dd4: 61bb str r3, [r7, #24]
+ temp &= ~((uint32_t)iocurrent);
+ 8000dd6: 693b ldr r3, [r7, #16]
+ 8000dd8: 43db mvns r3, r3
+ 8000dda: 69ba ldr r2, [r7, #24]
+ 8000ddc: 4013 ands r3, r2
+ 8000dde: 61bb str r3, [r7, #24]
+ if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
+ 8000de0: 683b ldr r3, [r7, #0]
+ 8000de2: 685b ldr r3, [r3, #4]
+ 8000de4: f403 3380 and.w r3, r3, #65536 ; 0x10000
+ 8000de8: 2b00 cmp r3, #0
+ 8000dea: d003 beq.n 8000df4
+ {
+ temp |= iocurrent;
+ 8000dec: 69ba ldr r2, [r7, #24]
+ 8000dee: 693b ldr r3, [r7, #16]
+ 8000df0: 4313 orrs r3, r2
+ 8000df2: 61bb str r3, [r7, #24]
+ }
+ EXTI->IMR = temp;
+ 8000df4: 4a11 ldr r2, [pc, #68] ; (8000e3c )
+ 8000df6: 69bb ldr r3, [r7, #24]
+ 8000df8: 6013 str r3, [r2, #0]
+ for(position = 0U; position < GPIO_NUMBER; position++)
+ 8000dfa: 69fb ldr r3, [r7, #28]
+ 8000dfc: 3301 adds r3, #1
+ 8000dfe: 61fb str r3, [r7, #28]
+ 8000e00: 69fb ldr r3, [r7, #28]
+ 8000e02: 2b0f cmp r3, #15
+ 8000e04: f67f ae96 bls.w 8000b34
+ }
+ }
+ }
+}
+ 8000e08: bf00 nop
+ 8000e0a: bf00 nop
+ 8000e0c: 3724 adds r7, #36 ; 0x24
+ 8000e0e: 46bd mov sp, r7
+ 8000e10: f85d 7b04 ldr.w r7, [sp], #4
+ 8000e14: 4770 bx lr
+ 8000e16: bf00 nop
+ 8000e18: 40023800 .word 0x40023800
+ 8000e1c: 40013800 .word 0x40013800
+ 8000e20: 40020000 .word 0x40020000
+ 8000e24: 40020400 .word 0x40020400
+ 8000e28: 40020800 .word 0x40020800
+ 8000e2c: 40020c00 .word 0x40020c00
+ 8000e30: 40021000 .word 0x40021000
+ 8000e34: 40021400 .word 0x40021400
+ 8000e38: 40021800 .word 0x40021800
+ 8000e3c: 40013c00 .word 0x40013c00
+
+08000e40 :
+ * @arg GPIO_PIN_RESET: to clear the port pin
+ * @arg GPIO_PIN_SET: to set the port pin
+ * @retval None
+ */
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+ 8000e40: b480 push {r7}
+ 8000e42: b083 sub sp, #12
+ 8000e44: af00 add r7, sp, #0
+ 8000e46: 6078 str r0, [r7, #4]
+ 8000e48: 460b mov r3, r1
+ 8000e4a: 807b strh r3, [r7, #2]
+ 8000e4c: 4613 mov r3, r2
+ 8000e4e: 707b strb r3, [r7, #1]
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+ if(PinState != GPIO_PIN_RESET)
+ 8000e50: 787b ldrb r3, [r7, #1]
+ 8000e52: 2b00 cmp r3, #0
+ 8000e54: d003 beq.n 8000e5e
+ {
+ GPIOx->BSRR = GPIO_Pin;
+ 8000e56: 887a ldrh r2, [r7, #2]
+ 8000e58: 687b ldr r3, [r7, #4]
+ 8000e5a: 619a str r2, [r3, #24]
+ }
+ else
+ {
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
+ }
+}
+ 8000e5c: e003 b.n 8000e66
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
+ 8000e5e: 887b ldrh r3, [r7, #2]
+ 8000e60: 041a lsls r2, r3, #16
+ 8000e62: 687b ldr r3, [r7, #4]
+ 8000e64: 619a str r2, [r3, #24]
+}
+ 8000e66: bf00 nop
+ 8000e68: 370c adds r7, #12
+ 8000e6a: 46bd mov sp, r7
+ 8000e6c: f85d 7b04 ldr.w r7, [sp], #4
+ 8000e70: 4770 bx lr
+ ...
+
+08000e74 :
+ * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
+ * (for more details refer to section above "Initialization/de-initialization functions")
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
+{
+ 8000e74: b580 push {r7, lr}
+ 8000e76: b084 sub sp, #16
+ 8000e78: af00 add r7, sp, #0
+ 8000e7a: 6078 str r0, [r7, #4]
+ 8000e7c: 6039 str r1, [r7, #0]
+ uint32_t tickstart;
+
+ /* Check Null pointer */
+ if(RCC_ClkInitStruct == NULL)
+ 8000e7e: 687b ldr r3, [r7, #4]
+ 8000e80: 2b00 cmp r3, #0
+ 8000e82: d101 bne.n 8000e88
+ {
+ return HAL_ERROR;
+ 8000e84: 2301 movs r3, #1
+ 8000e86: e0cc b.n 8001022
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+ must be correctly programmed according to the frequency of the CPU clock
+ (HCLK) and the supply voltage of the device. */
+
+ /* Increasing the number of wait states because of higher CPU frequency */
+ if(FLatency > __HAL_FLASH_GET_LATENCY())
+ 8000e88: 4b68 ldr r3, [pc, #416] ; (800102c )
+ 8000e8a: 681b ldr r3, [r3, #0]
+ 8000e8c: f003 030f and.w r3, r3, #15
+ 8000e90: 683a ldr r2, [r7, #0]
+ 8000e92: 429a cmp r2, r3
+ 8000e94: d90c bls.n 8000eb0
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+ 8000e96: 4b65 ldr r3, [pc, #404] ; (800102c )
+ 8000e98: 683a ldr r2, [r7, #0]
+ 8000e9a: b2d2 uxtb r2, r2
+ 8000e9c: 701a strb r2, [r3, #0]
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)
+ 8000e9e: 4b63 ldr r3, [pc, #396] ; (800102c )
+ 8000ea0: 681b ldr r3, [r3, #0]
+ 8000ea2: f003 030f and.w r3, r3, #15
+ 8000ea6: 683a ldr r2, [r7, #0]
+ 8000ea8: 429a cmp r2, r3
+ 8000eaa: d001 beq.n 8000eb0
+ {
+ return HAL_ERROR;
+ 8000eac: 2301 movs r3, #1
+ 8000eae: e0b8 b.n 8001022
+ }
+ }
+
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ 8000eb0: 687b ldr r3, [r7, #4]
+ 8000eb2: 681b ldr r3, [r3, #0]
+ 8000eb4: f003 0302 and.w r3, r3, #2
+ 8000eb8: 2b00 cmp r3, #0
+ 8000eba: d020 beq.n 8000efe
+ {
+ /* Set the highest APBx dividers in order to ensure that we do not go through
+ a non-spec phase whatever we decrease or increase HCLK. */
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 8000ebc: 687b ldr r3, [r7, #4]
+ 8000ebe: 681b ldr r3, [r3, #0]
+ 8000ec0: f003 0304 and.w r3, r3, #4
+ 8000ec4: 2b00 cmp r3, #0
+ 8000ec6: d005 beq.n 8000ed4
+ {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
+ 8000ec8: 4b59 ldr r3, [pc, #356] ; (8001030 )
+ 8000eca: 689b ldr r3, [r3, #8]
+ 8000ecc: 4a58 ldr r2, [pc, #352] ; (8001030 )
+ 8000ece: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
+ 8000ed2: 6093 str r3, [r2, #8]
+ }
+
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ 8000ed4: 687b ldr r3, [r7, #4]
+ 8000ed6: 681b ldr r3, [r3, #0]
+ 8000ed8: f003 0308 and.w r3, r3, #8
+ 8000edc: 2b00 cmp r3, #0
+ 8000ede: d005 beq.n 8000eec
+ {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
+ 8000ee0: 4b53 ldr r3, [pc, #332] ; (8001030 )
+ 8000ee2: 689b ldr r3, [r3, #8]
+ 8000ee4: 4a52 ldr r2, [pc, #328] ; (8001030 )
+ 8000ee6: f443 4360 orr.w r3, r3, #57344 ; 0xe000
+ 8000eea: 6093 str r3, [r2, #8]
+ }
+
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ 8000eec: 4b50 ldr r3, [pc, #320] ; (8001030 )
+ 8000eee: 689b ldr r3, [r3, #8]
+ 8000ef0: f023 02f0 bic.w r2, r3, #240 ; 0xf0
+ 8000ef4: 687b ldr r3, [r7, #4]
+ 8000ef6: 689b ldr r3, [r3, #8]
+ 8000ef8: 494d ldr r1, [pc, #308] ; (8001030 )
+ 8000efa: 4313 orrs r3, r2
+ 8000efc: 608b str r3, [r1, #8]
+ }
+
+ /*------------------------- SYSCLK Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ 8000efe: 687b ldr r3, [r7, #4]
+ 8000f00: 681b ldr r3, [r3, #0]
+ 8000f02: f003 0301 and.w r3, r3, #1
+ 8000f06: 2b00 cmp r3, #0
+ 8000f08: d044 beq.n 8000f94
+ {
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+ /* HSE is selected as System Clock Source */
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ 8000f0a: 687b ldr r3, [r7, #4]
+ 8000f0c: 685b ldr r3, [r3, #4]
+ 8000f0e: 2b01 cmp r3, #1
+ 8000f10: d107 bne.n 8000f22
+ {
+ /* Check the HSE ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ 8000f12: 4b47 ldr r3, [pc, #284] ; (8001030 )
+ 8000f14: 681b ldr r3, [r3, #0]
+ 8000f16: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 8000f1a: 2b00 cmp r3, #0
+ 8000f1c: d119 bne.n 8000f52
+ {
+ return HAL_ERROR;
+ 8000f1e: 2301 movs r3, #1
+ 8000f20: e07f b.n 8001022
+ }
+ }
+ /* PLL is selected as System Clock Source */
+ else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
+ 8000f22: 687b ldr r3, [r7, #4]
+ 8000f24: 685b ldr r3, [r3, #4]
+ 8000f26: 2b02 cmp r3, #2
+ 8000f28: d003 beq.n 8000f32
+ (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
+ 8000f2a: 687b ldr r3, [r7, #4]
+ 8000f2c: 685b ldr r3, [r3, #4]
+ else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
+ 8000f2e: 2b03 cmp r3, #3
+ 8000f30: d107 bne.n 8000f42
+ {
+ /* Check the PLL ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ 8000f32: 4b3f ldr r3, [pc, #252] ; (8001030 )
+ 8000f34: 681b ldr r3, [r3, #0]
+ 8000f36: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 8000f3a: 2b00 cmp r3, #0
+ 8000f3c: d109 bne.n 8000f52
+ {
+ return HAL_ERROR;
+ 8000f3e: 2301 movs r3, #1
+ 8000f40: e06f b.n 8001022
+ }
+ /* HSI is selected as System Clock Source */
+ else
+ {
+ /* Check the HSI ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ 8000f42: 4b3b ldr r3, [pc, #236] ; (8001030 )
+ 8000f44: 681b ldr r3, [r3, #0]
+ 8000f46: f003 0302 and.w r3, r3, #2
+ 8000f4a: 2b00 cmp r3, #0
+ 8000f4c: d101 bne.n 8000f52
+ {
+ return HAL_ERROR;
+ 8000f4e: 2301 movs r3, #1
+ 8000f50: e067 b.n 8001022
+ }
+ }
+
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+ 8000f52: 4b37 ldr r3, [pc, #220] ; (8001030 )
+ 8000f54: 689b ldr r3, [r3, #8]
+ 8000f56: f023 0203 bic.w r2, r3, #3
+ 8000f5a: 687b ldr r3, [r7, #4]
+ 8000f5c: 685b ldr r3, [r3, #4]
+ 8000f5e: 4934 ldr r1, [pc, #208] ; (8001030 )
+ 8000f60: 4313 orrs r3, r2
+ 8000f62: 608b str r3, [r1, #8]
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+ 8000f64: f7ff fce6 bl 8000934
+ 8000f68: 60f8 str r0, [r7, #12]
+
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+ 8000f6a: e00a b.n 8000f82
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 8000f6c: f7ff fce2 bl 8000934
+ 8000f70: 4602 mov r2, r0
+ 8000f72: 68fb ldr r3, [r7, #12]
+ 8000f74: 1ad3 subs r3, r2, r3
+ 8000f76: f241 3288 movw r2, #5000 ; 0x1388
+ 8000f7a: 4293 cmp r3, r2
+ 8000f7c: d901 bls.n 8000f82
+ {
+ return HAL_TIMEOUT;
+ 8000f7e: 2303 movs r3, #3
+ 8000f80: e04f b.n 8001022
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+ 8000f82: 4b2b ldr r3, [pc, #172] ; (8001030 )
+ 8000f84: 689b ldr r3, [r3, #8]
+ 8000f86: f003 020c and.w r2, r3, #12
+ 8000f8a: 687b ldr r3, [r7, #4]
+ 8000f8c: 685b ldr r3, [r3, #4]
+ 8000f8e: 009b lsls r3, r3, #2
+ 8000f90: 429a cmp r2, r3
+ 8000f92: d1eb bne.n 8000f6c
+ }
+ }
+ }
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if(FLatency < __HAL_FLASH_GET_LATENCY())
+ 8000f94: 4b25 ldr r3, [pc, #148] ; (800102c )
+ 8000f96: 681b ldr r3, [r3, #0]
+ 8000f98: f003 030f and.w r3, r3, #15
+ 8000f9c: 683a ldr r2, [r7, #0]
+ 8000f9e: 429a cmp r2, r3
+ 8000fa0: d20c bcs.n 8000fbc
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+ 8000fa2: 4b22 ldr r3, [pc, #136] ; (800102c )
+ 8000fa4: 683a ldr r2, [r7, #0]
+ 8000fa6: b2d2 uxtb r2, r2
+ 8000fa8: 701a strb r2, [r3, #0]
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)
+ 8000faa: 4b20 ldr r3, [pc, #128] ; (800102c )
+ 8000fac: 681b ldr r3, [r3, #0]
+ 8000fae: f003 030f and.w r3, r3, #15
+ 8000fb2: 683a ldr r2, [r7, #0]
+ 8000fb4: 429a cmp r2, r3
+ 8000fb6: d001 beq.n 8000fbc
+ {
+ return HAL_ERROR;
+ 8000fb8: 2301 movs r3, #1
+ 8000fba: e032 b.n 8001022
+ }
+ }
+
+ /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 8000fbc: 687b ldr r3, [r7, #4]
+ 8000fbe: 681b ldr r3, [r3, #0]
+ 8000fc0: f003 0304 and.w r3, r3, #4
+ 8000fc4: 2b00 cmp r3, #0
+ 8000fc6: d008 beq.n 8000fda