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MiniMips.twr
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MiniMips.twr
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--------------------------------------------------------------------------------
Release 14.7 Trace (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml MiniMips.twx MiniMips.ncd -o MiniMips.twr MiniMips.pcf -ucf
MiniMips.ucf
Design file: MiniMips.ncd
Physical constraint file: MiniMips.pcf
Device,package,speed: xc6slx16,csg324,C,-3 (PRODUCTION 1.23 2013-10-13)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock clk_global
------------+------------+------------+------------+------------+------------------+--------+
|Max Setup to| Process |Max Hold to | Process | | Clock |
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
------------+------------+------------+------------+------------+------------------+--------+
reset_global| 5.903(R)| SLOW | -3.745(R)| FAST |clk_global_BUFGP | 0.000|
------------+------------+------------+------------+------------+------------------+--------+
Clock clk_global to Pad
--------------+-----------------+------------+-----------------+------------+------------------+--------+
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
--------------+-----------------+------------+-----------------+------------+------------------+--------+
display_n_o<0>| 9.534(R)| SLOW | 4.656(R)| FAST |clk_global_BUFGP | 0.000|
display_n_o<1>| 9.383(R)| SLOW | 4.544(R)| FAST |clk_global_BUFGP | 0.000|
display_n_o<2>| 9.552(R)| SLOW | 4.673(R)| FAST |clk_global_BUFGP | 0.000|
display_n_o<3>| 9.362(R)| SLOW | 4.548(R)| FAST |clk_global_BUFGP | 0.000|
display_n_o<4>| 9.253(R)| SLOW | 4.485(R)| FAST |clk_global_BUFGP | 0.000|
display_n_o<5>| 9.354(R)| SLOW | 4.462(R)| FAST |clk_global_BUFGP | 0.000|
display_n_o<6>| 9.151(R)| SLOW | 4.431(R)| FAST |clk_global_BUFGP | 0.000|
en_n_o<0> | 7.568(R)| SLOW | 3.900(R)| FAST |clk_global_BUFGP | 0.000|
en_n_o<1> | 7.803(R)| SLOW | 4.048(R)| FAST |clk_global_BUFGP | 0.000|
en_n_o<2> | 7.832(R)| SLOW | 4.018(R)| FAST |clk_global_BUFGP | 0.000|
en_n_o<3> | 8.046(R)| SLOW | 4.163(R)| FAST |clk_global_BUFGP | 0.000|
--------------+-----------------+------------+-----------------+------------+------------------+--------+
Clock to Setup on destination clock clk_global
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_global | 3.299| | | |
---------------+---------+---------+---------+---------+
Analysis completed Wed May 21 12:27:33 2014
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 168 MB