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Super 80 Reproduction.sch
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Super 80 Reproduction.sch
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EESchema Schematic File Version 2
LIBS:mals_library
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:Super 80 Reproduction-cache
EELAYER 27 0
EELAYER END
$Descr A3 16535 11693
encoding utf-8
Sheet 1 7
Title "Super 80 Reproduction"
Date "10 oct 2016"
Rev "0.1"
Comp "Malcolm Macleod"
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 1050 1950 1800 750
U 5492C51F
F0 "RAM" 50
F1 "RAM.sch" 50
$EndSheet
$Sheet
S 1050 3950 1800 750
U 559C64AB
F0 "S-100 Interface" 50
F1 "s100.sch" 50
$EndSheet
$Sheet
S 1050 2950 1800 750
U 559A6243
F0 "I/O" 50
F1 "io.sch" 50
$EndSheet
$Sheet
S 1050 4950 1800 750
U 55A96B0E
F0 "Video Timing" 50
F1 "video-timing.sch" 50
$EndSheet
$Sheet
S 1050 5950 1800 750
U 55B04158
F0 "Power" 50
F1 "power.sch" 50
$EndSheet
$Sheet
S 1050 950 1800 750
U 55BB5AC1
F0 "CPU & ROM" 50
F1 "CPU.sch" 50
$EndSheet
$EndSCHEMATC