lpc812.mmap

0x14000000 A PERIPHERAL MTB
0x14000000 B  REGISTER POSITION (rw): POSITION Register
0x14000000 C   FIELD 02w01 WRAP (rw): This bit is set to 1 automatically when the POINTER value wraps as determined by the MASTER.MASK field in the MASTER Trace Control Register.
0x14000000 C   FIELD 03w29 POINTER (rw): Trace packet location pointer. Because a packet consists of two words, the POINTER field is the location of the first word of a packet. This field contains bits [31:3] of the address, in the SRAM, where the next trace packet will be written. The field points to an unused location and is automatically incremented. A debug agent can calculate the system address, on the AHB-Lite bus, of the SRAM location pointed to by the POSITION register using the following equation: system address = BASE + ((P + (2AWIDTH - (BASE MOD 2AWIDTH))) MOD 2AWIDTH). Where P = POSITION AND 0xFFFF_FFF8. Where BASE is the BASE register value
0x14000004 B  REGISTER MASTER (rw): MASTER Register
0x14000004 C   FIELD 00w05 MASK (rw): This value determines the maximum size of the trace buffer in SRAM. It specifies the most-significant bit of the POSITION.POINTER field that can be updated by automatic increment. If the trace tries to advance past this power of two, the POSITION.WRAP bit is set to 1, the POSITION.POINTER[MASK:0] bits are set to zero, and the POSITION.POINTER[AWIDTH-4:MASK+1] bits remain unchanged. This field causes the trace packet information to be stored in a circular buffer of size 2(MASK+4) bytes, that can be positioned in memory at multiples of this size. Valid values of this field are zero to AWIDTH-4. Values greater than the maximum have the same effect as the maximum.
0x14000004 C   FIELD 05w01 TSTARTEN (rw): Trace start input enable. If this bit is 1 and the TSTART signal is HIGH, then the EN bit is set to 1. Tracing continues until a stop condition occurs.
0x14000004 C   FIELD 06w01 TSTOPEN (rw): Trace stop input enable. If this bit is 1 and the TSTOP signal is HIGH, then the EN bit is set to 0. If a trace packet is being written to memory, the write is completed before tracing is stopped.
0x14000004 C   FIELD 07w01 SFRWPRIV (rw): Special Function Register Write Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write accesses to the Special Function Registers are permitted. If this bit is 1, then only Privileged write accesses are permitted and User write accesses are ignored. The HPROT[1] signal determines if an access is User or Privileged.
0x14000004 C   FIELD 08w01 RAMPRIV (rw): SRAM Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write accesses to the SRAM are permitted. If this bit is 1, then only Privileged AHB-Lite read and write accesses to the SRAM are permitted and User accesses are RAZ/WI. The HPROT[1] signal determines if an access is User or Privileged.
0x14000004 C   FIELD 09w01 HALTREQ (rw): Halt request bit. This bit is connected to the halt request signal of the trace logic, EDBGRQ. When HALTREQ is set to 1, EDBGRQ is asserted if DBGEN is also HIGH. The HALTREQ bit can be automatically set to 1 using the FLOW.WATERMARK field.
0x14000004 C   FIELD 31w01 EN (rw): Main trace enable bit. When this bit is 1 trace data is written into the SRAM memory location addressed by POSITION.POINTER. The POSITION.POINTER value auto increments after the trace data packet is written. The EN bit can be automatically set to 0 using the FLOW.WATERMARK field and the FLOW.AUTOSTOP bit. The EN bit is automatically set to 1 if the TSTARTEN bit is 1 and the TSTART signal is HIGH. The EN bit is automatically set to 0 if TSTOPEN bit is 1 and the TSTOP signal is HIGH.
0x14000008 B  REGISTER FLOW (rw): FLOW Register
0x14000008 C   FIELD 00w01 AUTOSTOP (rw): If this bit is 1 and WATERMARK is equal to POSITION.POINTER, then the MASTER.EN bit is automatically set to 0. This stops tracing.
0x14000008 C   FIELD 01w01 AUTOHALT (rw): If this bit is 1 and WATERMARK is equal to POSITION.POINTER, then the MASTER.HALTREQ bit is automatically set to 1. If the DBGEN signal is HIGH, the MTB asserts this halt request to the Cortex-M0+ processor by asserting the EDBGRQ signal.
0x14000008 C   FIELD 03w29 WATERMARK (rw): WATERMARK value. This field contains an address in the same format as the POSITION.POINTER field. When the POSITION.POINTER matches the WATERMARK field value, actions defined by the AUTOHALT and AUTOSTOP bits are performed.
0x1400000C B  REGISTER BASE (ro): Indicates where the SRAM is located in the processor memory map. This register is provided to enable auto discovery of the MTB SRAM location, by a debug agent.
0x1400000C C   FIELD 00w32 BASE (ro): The value provided is the value of the SRAMBASEADDR[31:0] signal.
0x40000000 A PERIPHERAL WWDT
0x40000000 B  REGISTER MOD (rw): Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.
0x40000000 C   FIELD 00w01 WDEN (rw): Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently.
0x40000000 C   FIELD 01w01 WDRESET (rw): Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0.
0x40000000 C   FIELD 02w01 WDTOF (rw): Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1.
0x40000000 C   FIELD 03w01 WDINT (rw): Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0.
0x40000000 C   FIELD 04w01 WDPROTECT (rw): Watchdog update mode. This bit can be set once by software and is only cleared by a reset.
0x40000000 C   FIELD 05w01 LOCK (rw): Once this bit is set to one and a watchdog feed is performed, disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset.
0x40000004 B  REGISTER TC (rw): Watchdog timer constant register. This 24-bit register determines the time-out value.
0x40000004 C   FIELD 00w24 COUNT (rw): Watchdog time-out value.
0x40000008 B  REGISTER FEED (wo): Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC.
0x40000008 C   FIELD 00w08 FEED (wo): Feed value should be 0xAA followed by 0x55.
0x4000000C B  REGISTER TV (ro): Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer.
0x4000000C C   FIELD 00w24 COUNT (ro): Counter timer value.
0x40000014 B  REGISTER WARNINT (rw): Watchdog Warning Interrupt compare value.
0x40000014 C   FIELD 00w10 WARNINT (rw): Watchdog warning interrupt compare value.
0x40000018 B  REGISTER WINDOW (rw): Watchdog Window compare value.
0x40000018 C   FIELD 00w24 WINDOW (rw): Watchdog window value.
0x40004000 A PERIPHERAL MRT0
0x40004000 B  CLUSTER CHANNEL[0]: no description available
0x40004000 B  REGISTER INTVAL0 (rw): MRT Time interval value register. This value is loaded into the TIMER register.
0x40004000 C   FIELD 00w31 IVALUE (rw): Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
0x40004000 C   FIELD 31w01 LOAD (rw): Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
0x40004004 B  REGISTER TIMER0 (ro): MRT Timer register. This register reads the value of the down-counter.
0x40004004 C   FIELD 00w31 VALUE (ro): Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
0x40004008 B  REGISTER CTRL0 (rw): MRT Control register. This register controls the MRT modes.
0x40004008 C   FIELD 00w01 INTEN (rw): Enable the TIMERn interrupt.
0x40004008 C   FIELD 01w02 MODE (rw): Selects timer mode.
0x4000400C B  REGISTER STAT0 (rw): MRT Status register.
0x4000400C C   FIELD 00w01 INTFLAG (rw): Monitors the interrupt flag.
0x4000400C C   FIELD 01w01 RUN (rw): Indicates the state of TIMERn. This bit is read-only.
0x40004010 B  CLUSTER CHANNEL[1]: no description available
0x40004010 B  REGISTER INTVAL1 (rw): MRT Time interval value register. This value is loaded into the TIMER register.
0x40004010 C   FIELD 00w31 IVALUE (rw): Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
0x40004010 C   FIELD 31w01 LOAD (rw): Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
0x40004014 B  REGISTER TIMER1 (ro): MRT Timer register. This register reads the value of the down-counter.
0x40004014 C   FIELD 00w31 VALUE (ro): Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
0x40004018 B  REGISTER CTRL1 (rw): MRT Control register. This register controls the MRT modes.
0x40004018 C   FIELD 00w01 INTEN (rw): Enable the TIMERn interrupt.
0x40004018 C   FIELD 01w02 MODE (rw): Selects timer mode.
0x4000401C B  REGISTER STAT1 (rw): MRT Status register.
0x4000401C C   FIELD 00w01 INTFLAG (rw): Monitors the interrupt flag.
0x4000401C C   FIELD 01w01 RUN (rw): Indicates the state of TIMERn. This bit is read-only.
0x40004020 B  CLUSTER CHANNEL[2]: no description available
0x40004020 B  REGISTER INTVAL2 (rw): MRT Time interval value register. This value is loaded into the TIMER register.
0x40004020 C   FIELD 00w31 IVALUE (rw): Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
0x40004020 C   FIELD 31w01 LOAD (rw): Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
0x40004024 B  REGISTER TIMER2 (ro): MRT Timer register. This register reads the value of the down-counter.
0x40004024 C   FIELD 00w31 VALUE (ro): Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
0x40004028 B  REGISTER CTRL2 (rw): MRT Control register. This register controls the MRT modes.
0x40004028 C   FIELD 00w01 INTEN (rw): Enable the TIMERn interrupt.
0x40004028 C   FIELD 01w02 MODE (rw): Selects timer mode.
0x4000402C B  REGISTER STAT2 (rw): MRT Status register.
0x4000402C C   FIELD 00w01 INTFLAG (rw): Monitors the interrupt flag.
0x4000402C C   FIELD 01w01 RUN (rw): Indicates the state of TIMERn. This bit is read-only.
0x40004030 B  CLUSTER CHANNEL[3]: no description available
0x40004030 B  REGISTER INTVAL3 (rw): MRT Time interval value register. This value is loaded into the TIMER register.
0x40004030 C   FIELD 00w31 IVALUE (rw): Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
0x40004030 C   FIELD 31w01 LOAD (rw): Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
0x40004034 B  REGISTER TIMER3 (ro): MRT Timer register. This register reads the value of the down-counter.
0x40004034 C   FIELD 00w31 VALUE (ro): Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
0x40004038 B  REGISTER CTRL3 (rw): MRT Control register. This register controls the MRT modes.
0x40004038 C   FIELD 00w01 INTEN (rw): Enable the TIMERn interrupt.
0x40004038 C   FIELD 01w02 MODE (rw): Selects timer mode.
0x4000403C B  REGISTER STAT3 (rw): MRT Status register.
0x4000403C C   FIELD 00w01 INTFLAG (rw): Monitors the interrupt flag.
0x4000403C C   FIELD 01w01 RUN (rw): Indicates the state of TIMERn. This bit is read-only.
0x400040F0 B  REGISTER MODCFG (rw): Module Configuration register. This register provides information about this particular MRT instance.
0x400040F0 C   FIELD 00w04 NOC (ro): Identifies the number of channels in this MRT.(4 channels on this device.)
0x400040F0 C   FIELD 04w05 NOB (ro): Identifies the number of timer bits in this MRT. (31 bits wide on this device.)
0x400040F4 B  REGISTER IDLE_CH (ro): Idle channel register. This register returns the number of the first idle channel.
0x400040F4 C   FIELD 04w04 CHAN (ro): Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details.
0x400040F8 B  REGISTER IRQ_FLAG (rw): Global interrupt flag register
0x400040F8 C   FIELD 00w01 GFLAG0 (rw): Monitors the interrupt flag of TIMER0.
0x400040F8 C   FIELD 01w01 GFLAG1 (rw): Monitors the interrupt flag of TIMER1. See description of channel 0.
0x400040F8 C   FIELD 02w01 GFLAG2 (rw): Monitors the interrupt flag of TIMER2. See description of channel 0.
0x400040F8 C   FIELD 03w01 GFLAG3 (rw): Monitors the interrupt flag of TIMER3. See description of channel 0.
0x40008000 A PERIPHERAL WKT
0x40008000 B  REGISTER CTRL (rw): Self wake-up timer control register.
0x40008000 C   FIELD 00w01 CLKSEL (rw): Select the self wake-up timer clock source. Remark: This bit only has an effect if the SEL_EXTCLK bit is not set.
0x40008000 C   FIELD 01w01 ALARMFLAG (rw): Wake-up or alarm timer flag.
0x40008000 C   FIELD 02w01 CLEARCTR (rw): Clears the self wake-up timer.
0x4000800C B  REGISTER COUNT (rw): Counter register.
0x4000800C C   FIELD 00w32 VALUE (rw): A write to this register pre-loads start count value into the timer and starts the count-down sequence. A read reflects the current value of the timer.
0x4000C000 A PERIPHERAL SWM0
0x4000C000 B  REGISTER PINASSIGN0 (rw): Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS.
0x4000C000 B  REGISTER PINASSIGN_DATA0 (rw): Pin assign register
0x4000C000 C   FIELD 00w08 DATA0 (rw): T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C000 C   FIELD 00w08 U0_TXD_O (rw): U0_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C000 C   FIELD 08w08 DATA1 (rw): T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C000 C   FIELD 08w08 U0_RXD_I (rw): U0_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C000 C   FIELD 16w08 DATA2 (rw): T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C000 C   FIELD 16w08 U0_RTS_O (rw): U0_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C000 C   FIELD 24w08 DATA3 (rw): T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C000 C   FIELD 24w08 U0_CTS_I (rw): U0_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C004 B  REGISTER PINASSIGN1 (rw): Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, U1_RXD, U1_RTS.
0x4000C004 B  REGISTER PINASSIGN_DATA1 (rw): Pin assign register
0x4000C004 C   FIELD 00w08 DATA0 (rw): T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C004 C   FIELD 00w08 U0_SCLK_IO (rw): U0_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C004 C   FIELD 08w08 DATA1 (rw): T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C004 C   FIELD 08w08 U1_TXD_O (rw): U1_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C004 C   FIELD 16w08 DATA2 (rw): T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C004 C   FIELD 16w08 U1_RXD_I (rw): U1_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C004 C   FIELD 24w08 DATA3 (rw): T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C004 C   FIELD 24w08 U1_RTS_O (rw): U1_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C008 B  REGISTER PINASSIGN2 (rw): Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK, U2_TXD, U2_RXD.
0x4000C008 B  REGISTER PINASSIGN_DATA2 (rw): Pin assign register
0x4000C008 C   FIELD 00w08 DATA0 (rw): T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C008 C   FIELD 00w08 U1_CTS_I (rw): U1_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C008 C   FIELD 08w08 DATA1 (rw): T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C008 C   FIELD 08w08 U1_SCLK_IO (rw): U1_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C008 C   FIELD 16w08 DATA2 (rw): T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C008 C   FIELD 16w08 U2_TXD_O (rw): U2_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C008 C   FIELD 24w08 DATA3 (rw): T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C008 C   FIELD 24w08 U2_RXD_I (rw): U2_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C00C B  REGISTER PINASSIGN3 (rw): Pin assign register 3. Assign movable function U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK.
0x4000C00C B  REGISTER PINASSIGN_DATA3 (rw): Pin assign register
0x4000C00C C   FIELD 00w08 DATA0 (rw): T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C00C C   FIELD 00w08 U2_RTS_O (rw): U2_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C00C C   FIELD 08w08 DATA1 (rw): T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C00C C   FIELD 08w08 U2_CTS_I (rw): U2_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C00C C   FIELD 16w08 DATA2 (rw): T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C00C C   FIELD 16w08 U2_SCLK_IO (rw): U2_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C00C C   FIELD 24w08 DATA3 (rw): T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C00C C   FIELD 24w08 SPI0_SCK_IO (rw): SPI0_SCK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C010 B  REGISTER PINASSIGN4 (rw): Pin assign register 4. Assign movable functions SPI0_MOSI, SPI0_MISO,SPI0_SSEL, SPI1_SCK.
0x4000C010 B  REGISTER PINASSIGN_DATA4 (rw): Pin assign register
0x4000C010 C   FIELD 00w08 DATA0 (rw): T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C010 C   FIELD 00w08 SPI0_MOSI_IO (rw): SPI0_MOSI function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C010 C   FIELD 08w08 DATA1 (rw): T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C010 C   FIELD 08w08 SPI0_MISO_IO (rw): SPI0_MISIO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C010 C   FIELD 16w08 DATA2 (rw): T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C010 C   FIELD 16w08 SPI0_SSEL_IO (rw): SPI0_SSEL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C010 C   FIELD 24w08 DATA3 (rw): T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C010 C   FIELD 24w08 SPI1_SCK_IO (rw): SPI1_SCK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C014 B  REGISTER PINASSIGN5 (rw): Pin assign register 5. Assign movable functions SPI1_MOSI, SPI1_MISO,SPI1_SSEL, CTIN_0
0x4000C014 B  REGISTER PINASSIGN_DATA5 (rw): Pin assign register
0x4000C014 C   FIELD 00w08 DATA0 (rw): T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C014 C   FIELD 00w08 SPI1_MOSI_IO (rw): SPI1_MOSI function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C014 C   FIELD 08w08 DATA1 (rw): T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C014 C   FIELD 08w08 SPI1_MISO_IO (rw): SPI1_MISIO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C014 C   FIELD 16w08 DATA2 (rw): T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C014 C   FIELD 16w08 SPI1_SSEL_IO (rw): SPI1_SSEL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C014 C   FIELD 24w08 CTIN_0_I (rw): CTIN_0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C014 C   FIELD 24w08 DATA3 (rw): T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C018 B  REGISTER PINASSIGN6 (rw): Pin assign register 6. Assign movable functions CTIN_1, CTIN_2, CTIN_3,CTOUT_0.
0x4000C018 B  REGISTER PINASSIGN_DATA6 (rw): Pin assign register
0x4000C018 C   FIELD 00w08 CTIN_1_I (rw): CTIN_1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C018 C   FIELD 00w08 DATA0 (rw): T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C018 C   FIELD 08w08 CTIN_2_I (rw): CTIN_2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C018 C   FIELD 08w08 DATA1 (rw): T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C018 C   FIELD 16w08 CTIN_3_I (rw): CTIN_3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C018 C   FIELD 16w08 DATA2 (rw): T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C018 C   FIELD 24w08 CTOUT_0_O (rw): CTOUT_0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C018 C   FIELD 24w08 DATA3 (rw): T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C01C B  REGISTER PINASSIGN7 (rw): Pin assign register 7. Assign movable functions CTOUT_1, CTOUT_2, CTOUT_3,I2C_SDA.
0x4000C01C B  REGISTER PINASSIGN_DATA7 (rw): Pin assign register
0x4000C01C C   FIELD 00w08 CTOUT_1_O (rw): CTOUT_1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C01C C   FIELD 00w08 DATA0 (rw): T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C01C C   FIELD 08w08 CTOUT_2_O (rw): CTOUT_2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C01C C   FIELD 08w08 DATA1 (rw): T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C01C C   FIELD 16w08 CTOUT_3_O (rw): CTOUT_3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C01C C   FIELD 16w08 DATA2 (rw): T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C01C C   FIELD 24w08 DATA3 (rw): T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C01C C   FIELD 24w08 I2C_SDA_IO (rw): I2C_SDA function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C020 B  REGISTER PINASSIGN8 (rw): Pin assign register 8. Assign movable functions I2C_SCL, ACMP_O, CLKOUT,GPIO_INT_BMAT.
0x4000C020 B  REGISTER PINASSIGN_DATA8 (rw): Pin assign register
0x4000C020 C   FIELD 00w08 DATA0 (rw): T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C020 C   FIELD 00w08 I2C_SCL_IO (rw): I2C_SCL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C020 C   FIELD 08w08 ACMP_O_O (rw): ACMP_O_O function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C020 C   FIELD 08w08 DATA1 (rw): T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C020 C   FIELD 16w08 CLKOUT_O (rw): CLKOUT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C020 C   FIELD 16w08 DATA2 (rw): T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C020 C   FIELD 24w08 DATA3 (rw): T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0x4000C020 C   FIELD 24w08 GPIO_INT_BMAT_O (rw): GPIO_INT_BMAT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0x4000C1C0 B  REGISTER PINENABLE0 (rw): Pin enable register 0. Enables fixed-pin functions ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN, VDDCMP and so on.
0x4000C1C0 C   FIELD 00w01 ACMP_I1 (rw): Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin.
0x4000C1C0 C   FIELD 01w01 ACMP_I2 (rw): Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed-pin function is deselected and GPIO is assigned to this pin. Functions CLKIN and ACMP_I2 are connected to the same pin PIO0_1. To use ACMP_I2, disable the CLKIN function in bit 7 of this register and enable ACMP_I2.
0x4000C1C0 C   FIELD 02w01 SWCLK (rw): Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. This function is selected by default.
0x4000C1C0 C   FIELD 03w01 SWDIO (rw): Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. This function is selected by default.
0x4000C1C0 C   FIELD 04w01 XTALIN (rw): Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin.
0x4000C1C0 C   FIELD 05w01 XTALOUT (rw): Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin.
0x4000C1C0 C   FIELD 06w01 RESETN (rw): Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. This function is selected by default.
0x4000C1C0 C   FIELD 07w01 CLKIN (rw): Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed-pin function is deselected and GPIO is assigned to this pin. Functions CLKIN and ACMP_I2 are connected to the same pin PIO0_1. To use CLKIN, disable ACMP_I2 in bit 1 of this register and enable CLKIN.
0x4000C1C0 C   FIELD 08w01 VDDCMP (rw): Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin.
0x40020000 A PERIPHERAL PMU
0x40020000 B  REGISTER PCON (rw): Power control register
0x40020000 C   FIELD 00w03 PM (rw): Power mode
0x40020000 C   FIELD 03w01 NODPD (rw): A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked.
0x40020000 C   FIELD 08w01 SLEEPFLAG (rw): Sleep mode flag
0x40020000 C   FIELD 11w01 DPDFLAG (rw): Deep power-down flag
0x40020004 B  REGISTER GPREG[0] (rw): General purpose register N
0x40020004 C   FIELD 00w32 GPDATA (rw): Data retained during Deep power-down mode.
0x40020008 B  REGISTER GPREG[1] (rw): General purpose register N
0x40020008 C   FIELD 00w32 GPDATA (rw): Data retained during Deep power-down mode.
0x4002000C B  REGISTER GPREG[2] (rw): General purpose register N
0x4002000C C   FIELD 00w32 GPDATA (rw): Data retained during Deep power-down mode.
0x40020010 B  REGISTER GPREG[3] (rw): General purpose register N
0x40020010 C   FIELD 00w32 GPDATA (rw): Data retained during Deep power-down mode.
0x40020014 B  REGISTER DPDCTRL (rw): Deep power-down control register. Also includes bits for general purpose storage.
0x40020014 C   FIELD 00w01 WAKEUPHYS (rw): WAKEUP pin hysteresis enable
0x40020014 C   FIELD 01w01 WAKEPAD_DISABLE (rw): WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be used for other purposes. Remark: Never set this bit if you intend to use a pin to wake up the part from Deep power-down mode. You can only disable the wake-up pin if the self wake-up timer is enabled and configured. Remark: Setting this bit is not necessary if Deep power-down mode is not used.
0x40020014 C   FIELD 02w01 LPOSCEN (rw): Enable the low-power oscillator for use with the 10 kHz self wake-up timer clock. You must set this bit if the CLKSEL bit in the self wake-up timer CTRL bit is set. Do not enable the low-power oscillator if the self wake-up timer is clocked by the divided IRC or the external clock input.
0x40020014 C   FIELD 03w01 LPOSCDPDEN (rw): causes the low-power oscillator to remain running during Deep power-down mode provided that bit 2 in this register is set as well. You must set this bit for the self wake-up timer to be able to wake up the part from Deep power-down mode. Remark: Do not set this bit unless you use the self wake-up timer with the low-power oscillator clock source to wake up from Deep power-down mode.
0x40020014 C   FIELD 04w28 GPDATA (rw): Data retained during Deep power-down mode.
0x40024000 A PERIPHERAL ACOMP
0x40024000 B  REGISTER CTRL (rw): Comparator control register
0x40024000 C   FIELD 03w02 EDGESEL (rw): This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below):
0x40024000 C   FIELD 06w01 COMPSA (rw): Comparator output control
0x40024000 C   FIELD 08w03 COMP_VP_SEL (rw): Selects positive voltage input
0x40024000 C   FIELD 11w03 COMP_VM_SEL (rw): Selects negative voltage input
0x40024000 C   FIELD 20w01 EDGECLR (rw): Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request, toggle the EDGECLR bit by first writing a 1 and then a 0.
0x40024000 C   FIELD 21w01 COMPSTAT (rw): Comparator status. This bit reflects the state of the comparator output.
0x40024000 C   FIELD 23w01 COMPEDGE (rw): Comparator edge-detect status.
0x40024000 C   FIELD 25w02 HYS (rw): Controls the hysteresis of the comparator. When the comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output.
0x40024004 B  REGISTER LAD (rw): Voltage ladder register
0x40024004 C   FIELD 00w01 LADEN (rw): Voltage ladder enable
0x40024004 C   FIELD 01w05 LADSEL (rw): Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000 = VSS 00001 = 1 x Vref/31 00010 = 2 x Vref/31 ... 11111 = Vref
0x40024004 C   FIELD 06w01 LADREF (rw): Selects the reference voltage Vref for the voltage ladder.
0x40040000 A PERIPHERAL FLASH_CTRL
0x40040010 B  REGISTER FLASHCFG (rw): Flash configuration register
0x40040010 C   FIELD 00w02 FLASHTIM (rw): Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
0x40040020 B  REGISTER FMSSTART (rw): Flash signature start address register
0x40040020 C   FIELD 00w17 START (rw): Signature generation start address (corresponds to AHB byte address bits[18:2]).
0x40040024 B  REGISTER FMSSTOP (rw): Flash signaure stop address register
0x40040024 C   FIELD 00w17 STOPA (rw): Stop address for signature generation (the word specified by STOP is included in the address range). The address is in units of memory words, not bytes.
0x40040024 C   FIELD 31w01 STRTBIST (rw): When this bit is written to 1, signature generation starts. At the end of signature generation, this bit is automatically cleared.
0x4004002C B  REGISTER FMSW0 (ro): Flash signature generation result register returns the flash signature produced by the embedded signature generator..
0x4004002C C   FIELD 00w32 SIG (ro): 32-bit signature.
0x40044000 A PERIPHERAL IOCON
0x40044000 B  REGISTER PIO0_17 (rw): Digital I/O control for pins PIO0_17
0x40044000 C   FIELD 03w02 MODE (rw): Selects function mode (on-chip pull-up/pull-down resistor control).
0x40044000 C   FIELD 05w01 HYS (rw): Hysteresis.
0x40044000 C   FIELD 06w01 INV (rw): Invert input
0x40044000 C   FIELD 10w01 OD (rw): Open-drain mode.
0x40044000 C   FIELD 11w02 S_MODE (rw): Digital filter sample mode.
0x40044000 C   FIELD 13w03 CLK_DIV (rw): Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
0x40044004 B  REGISTER PIO0_13 (rw): Digital I/O control for pins PIO0_13
0x40044004 C   FIELD 03w02 MODE (rw): Selects function mode (on-chip pull-up/pull-down resistor control).
0x40044004 C   FIELD 05w01 HYS (rw): Hysteresis.
0x40044004 C   FIELD 06w01 INV (rw): Invert input
0x40044004 C   FIELD 10w01 OD (rw): Open-drain mode.
0x40044004 C   FIELD 11w02 S_MODE (rw): Digital filter sample mode.
0x40044004 C   FIELD 13w03 CLK_DIV (rw): Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
0x40044008 B  REGISTER PIO0_12 (rw): Digital I/O control for pins PIO0_12
0x40044008 C   FIELD 03w02 MODE (rw): Selects function mode (on-chip pull-up/pull-down resistor control).
0x40044008 C   FIELD 05w01 HYS (rw): Hysteresis.
0x40044008 C   FIELD 06w01 INV (rw): Invert input
0x40044008 C   FIELD 10w01 OD (rw): Open-drain mode.
0x40044008 C   FIELD 11w02 S_MODE (rw): Digital filter sample mode.
0x40044008 C   FIELD 13w03 CLK_DIV (rw): Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
0x4004400C B  REGISTER PIO0_5 (rw): Digital I/O control for pins PIO0_5
0x4004400C C   FIELD 03w02 MODE (rw): Selects function mode (on-chip pull-up/pull-down resistor control).
0x4004400C C   FIELD 05w01 HYS (rw): Hysteresis.
0x4004400C C   FIELD 06w01 INV (rw): Invert input
0x4004400C C   FIELD 10w01 OD (rw): Open-drain mode.
0x4004400C C   FIELD 11w02 S_MODE (rw): Digital filter sample mode.
0x4004400C C   FIELD 13w03 CLK_DIV (rw): Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
0x40044010 B  REGISTER PIO0_4 (rw): Digital I/O control for pins PIO0_4
0x40044010 C   FIELD 03w02 MODE (rw): Selects function mode (on-chip pull-up/pull-down resistor control).
0x40044010 C   FIELD 05w01 HYS (rw): Hysteresis.
0x40044010 C   FIELD 06w01 INV (rw): Invert input
0x40044010 C   FIELD 10w01 OD (rw): Open-drain mode.
0x40044010 C   FIELD 11w02 S_MODE (rw): Digital filter sample mode.
0x40044010 C   FIELD 13w03 CLK_DIV (rw): Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
0x40044014 B  REGISTER PIO0_3 (rw): Digital I/O control for pins PIO0_3
0x40044014 C   FIELD 03w02 MODE (rw): Selects function mode (on-chip pull-up/pull-down resistor control).
0x40044014 C   FIELD 05w01 HYS (rw): Hysteresis.
0x40044014 C   FIELD 06w01 INV (rw): Invert input
0x40044014 C   FIELD 10w01 OD (rw): Open-drain mode.
0x40044014 C   FIELD 11w02 S_MODE (rw): Digital filter sample mode.
0x40044014 C   FIELD 13w03 CLK_DIV (rw): Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
0x40044018 B  REGISTER PIO0_2 (rw): Digital I/O control for pins PIO0_2
0x40044018 C   FIELD 03w02 MODE (rw): Selects function mode (on-chip pull-up/pull-down resistor control).
0x40044018 C   FIELD 05w01 HYS (rw): Hysteresis.
0x40044018 C   FIELD 06w01 INV (rw): Invert input
0x40044018 C   FIELD 10w01 OD (rw): Open-drain mode.
0x40044018 C   FIELD 11w02 S_MODE (rw): Digital filter sample mode.
0x40044018 C   FIELD 13w03 CLK_DIV (rw): Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
0x4004401C B  REGISTER PIO0_11 (rw): Digital I/O control for pins PIO0_11
0x4004401C C   FIELD 06w01 INV (rw): Invert input
0x4004401C C   FIELD 08w02 I2CMODE (rw): Selects I2C mode.
0x4004401C C   FIELD 11w02 S_MODE (rw): Digital filter sample mode.
0x4004401C C   FIELD 13w03 CLK_DIV (rw): Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
0x40044020 B  REGISTER PIO0_10 (rw): Digital I/O control for pins PIO0_10
0x40044020 C   FIELD 06w01 INV (rw): Invert input
0x40044020 C   FIELD 08w02 I2CMODE (rw): Selects I2C mode.
0x40044020 C   FIELD 11w02 S_MODE (rw): Digital filter sample mode.
0x40044020 C   FIELD 13w03 CLK_DIV (rw): Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
0x40044024 B  REGISTER PIO0_16 (rw): Digital I/O control for pins PIO0_16
0x40044024 C   FIELD 03w02 MODE (rw): Selects function mode (on-chip pull-up/pull-down resistor control).
0x40044024 C   FIELD 05w01 HYS (rw): Hysteresis.
0x40044024 C   FIELD 06w01 INV (rw): Invert input
0x40044024 C   FIELD 10w01 OD (rw): Open-drain mode.
0x40044024 C   FIELD 11w02 S_MODE (rw): Digital filter sample mode.
0x40044024 C   FIELD 13w03 CLK_DIV (rw): Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
0x40044028 B  REGISTER PIO0_15 (rw): Digital I/O control for pins PIO0_15
0x40044028 C   FIELD 03w02 MODE (rw): Selects function mode (on-chip pull-up/pull-down resistor control).
0x40044028 C   FIELD 05w01 HYS (rw): Hysteresis.
0x40044028 C   FIELD 06w01 INV (rw): Invert input
0x40044028 C   FIELD 10w01 OD (rw): Open-drain mode.
0x40044028 C   FIELD 11w02 S_MODE (rw): Digital filter sample mode.
0x40044028 C   FIELD 13w03 CLK_DIV (rw): Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
0x4004402C B  REGISTER PIO0_1 (rw): Digital I/O control for pins PIO0_1
0x4004402C C   FIELD 03w02 MODE (rw): Selects function mode (on-chip pull-up/pull-down resistor control).
0x4004402C C   FIELD 05w01 HYS (rw): Hysteresis.
0x4004402C C   FIELD 06w01 INV (rw): Invert input
0x4004402C C   FIELD 10w01 OD (rw): Open-drain mode.
0x4004402C C   FIELD 11w02 S_MODE (rw): Digital filter sample mode.
0x4004402C C   FIELD 13w03 CLK_DIV (rw): Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
0x40044034 B  REGISTER PIO0_9 (rw): Digital I/O control for pins PIO0_9
0x40044034 C   FIELD 03w02 MODE (rw): Selects function mode (on-chip pull-up/pull-down resistor control).
0x40044034 C   FIELD 05w01 HYS (rw): Hysteresis.
0x40044034 C   FIELD 06w01 INV (rw): Invert input
0x40044034 C   FIELD 10w01 OD (rw): Open-drain mode.
0x40044034 C   FIELD 11w02 S_MODE (rw): Digital filter sample mode.
0x40044034 C   FIELD 13w03 CLK_DIV (rw): Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
0x40044038 B  REGISTER PIO0_8 (rw): Digital I/O control for pins PIO0_8
0x40044038 C   FIELD 03w02 MODE (rw): Selects function mode (on-chip pull-up/pull-down resistor control).
0x40044038 C   FIELD 05w01 HYS (rw): Hysteresis.
0x40044038 C   FIELD 06w01 INV (rw): Invert input
0x40044038 C   FIELD 10w01 OD (rw): Open-drain mode.
0x40044038 C   FIELD 11w02 S_MODE (rw): Digital filter sample mode.
0x40044038 C   FIELD 13w03 CLK_DIV (rw): Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
0x4004403C B  REGISTER PIO0_7 (rw): Digital I/O control for pins PIO0_7
0x4004403C C   FIELD 03w02 MODE (rw): Selects function mode (on-chip pull-up/pull-down resistor control).
0x4004403C C   FIELD 05w01 HYS (rw): Hysteresis.
0x4004403C C   FIELD 06w01 INV (rw): Invert input
0x4004403C C   FIELD 10w01 OD (rw): Open-drain mode.
0x4004403C C   FIELD 11w02 S_MODE (rw): Digital filter sample mode.
0x4004403C C   FIELD 13w03 CLK_DIV (rw): Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
0x40044040 B  REGISTER PIO0_6 (rw): Digital I/O control for pins PIO0_6
0x40044040 C   FIELD 03w02 MODE (rw): Selects function mode (on-chip pull-up/pull-down resistor control).
0x40044040 C   FIELD 05w01 HYS (rw): Hysteresis.
0x40044040 C   FIELD 06w01 INV (rw): Invert input
0x40044040 C   FIELD 10w01 OD (rw): Open-drain mode.
0x40044040 C   FIELD 11w02 S_MODE (rw): Digital filter sample mode.
0x40044040 C   FIELD 13w03 CLK_DIV (rw): Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
0x40044044 B  REGISTER PIO0_0 (rw): Digital I/O control for pins PIO0_0
0x40044044 C   FIELD 03w02 MODE (rw): Selects function mode (on-chip pull-up/pull-down resistor control).
0x40044044 C   FIELD 05w01 HYS (rw): Hysteresis.
0x40044044 C   FIELD 06w01 INV (rw): Invert input
0x40044044 C   FIELD 10w01 OD (rw): Open-drain mode.
0x40044044 C   FIELD 11w02 S_MODE (rw): Digital filter sample mode.
0x40044044 C   FIELD 13w03 CLK_DIV (rw): Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
0x40044048 B  REGISTER PIO0_14 (rw): Digital I/O control for pins PIO0_14
0x40044048 C   FIELD 03w02 MODE (rw): Selects function mode (on-chip pull-up/pull-down resistor control).
0x40044048 C   FIELD 05w01 HYS (rw): Hysteresis.
0x40044048 C   FIELD 06w01 INV (rw): Invert input
0x40044048 C   FIELD 10w01 OD (rw): Open-drain mode.
0x40044048 C   FIELD 11w02 S_MODE (rw): Digital filter sample mode.
0x40044048 C   FIELD 13w03 CLK_DIV (rw): Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
0x40048000 A PERIPHERAL SYSCON
0x40048000 B  REGISTER SYSMEMREMAP (rw): System Remap register
0x40048000 C   FIELD 00w02 MAP (rw): System memory remap. Value 0x3 is reserved.
0x40048004 B  REGISTER PRESETCTRL (rw): Peripheral reset control register
0x40048004 C   FIELD 00w01 SPI0_RST_N (rw): SPI0 reset control.
0x40048004 C   FIELD 01w01 SPI1_RST_N (rw): SPI1 reset control.
0x40048004 C   FIELD 02w01 UARTFRG_RST_N (rw): USART fractional baud rate generator(UARTFRG) reset control.
0x40048004 C   FIELD 03w01 UART0_RST_N (rw): USART0 reset control.
0x40048004 C   FIELD 04w01 UART1_RST_N (rw): USART1 reset control.
0x40048004 C   FIELD 05w01 UART2_RST_N (rw): USART2 reset control.
0x40048004 C   FIELD 06w01 I2C0_RST_N (rw): I2C0 reset control.
0x40048004 C   FIELD 07w01 MRT_RST_N (rw): Multi-rate timer (MRT) reset control.
0x40048004 C   FIELD 08w01 SCT_RST_N (rw): SCT reset control.
0x40048004 C   FIELD 09w01 WKT_RST_N (rw): Self-wake-up timer (WKT) reset control.
0x40048004 C   FIELD 10w01 GPIO_RST_N (rw): GPIO and GPIO pin interrupt reset control.
0x40048004 C   FIELD 11w01 FLASH_RST_N (rw): Flash controller reset control.
0x40048004 C   FIELD 12w01 ACMP_RST_N (rw): Analog comparator reset control.
0x40048008 B  REGISTER SYSPLLCTRL (rw): PLL control
0x40048008 C   FIELD 00w05 MSEL (rw): Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32
0x40048008 C   FIELD 05w02 PSEL (rw): Post divider ratio P. The division ratio is 2 x P.
0x4004800C B  REGISTER SYSPLLSTAT (ro): PLL status
0x4004800C C   FIELD 00w01 LOCK (ro): PLL0 lock indicator
0x40048020 B  REGISTER SYSOSCCTRL (rw): system oscillator control
0x40048020 C   FIELD 00w01 BYPASS (rw): Bypass system oscillator
0x40048020 C   FIELD 01w01 FREQRANGE (rw): oscillator low / high transconductance selection input (Active High) 1-20MHz '0' : 15-50MHz '1'
0x40048024 B  REGISTER WDTOSCCTRL (rw): Watchdog oscillator control
0x40048024 C   FIELD 00w05 DIVSEL (rw): Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64
0x40048024 C   FIELD 05w04 FREQSEL (rw): Frequency select. Selects the frequency of the oscillator. 0x00 = invalid setting when watchdog oscillator is running 0x1 = 0.6 MHz 0x2 = 1.05 MHz 0x3 = 1.4 MHz 0x4 = 1.75 MHz 0x5 = 2.1 MHz 0x6 = 2.4 MHz 0x7 = 2.7 MHz 0x8 = 3.0 MHz 0x9 = 3.25 MHz 0xA = 3.5 MHz 0xB = 3.75 MHz 0xC = 4.0 MHz 0xD = 4.2 MHz 0xE = 4.4 MHz 0xF = 4.6 MHz
0x40048030 B  REGISTER SYSRSTSTAT (rw): System reset status register
0x40048030 C   FIELD 00w01 POR (rw): POR reset status.
0x40048030 C   FIELD 01w01 EXTRST (rw): Status of the external RESET pin. External reset status.
0x40048030 C   FIELD 02w01 WDT (rw): Status of the Watchdog reset.
0x40048030 C   FIELD 03w01 BOD (rw): Status of the Brown-out detect reset.
0x40048030 C   FIELD 04w01 SYSRST (rw): Status of the software system reset.
0x40048040 B  REGISTER SYSPLLCLKSEL (rw): System PLL clock source select register
0x40048040 C   FIELD 00w02 SEL (rw): System PLL clock source
0x40048044 B  REGISTER SYSPLLCLKUEN (rw): System PLL clock source update enable register
0x40048044 C   FIELD 00w01 ENA (rw): Enable system PLL clock source update
0x40048070 B  REGISTER MAINCLKSEL (rw): Main clock source select
0x40048070 C   FIELD 00w02 SEL (rw): Clock source for main clock.
0x40048074 B  REGISTER MAINCLKUEN (rw): Main clock source update enable
0x40048074 C   FIELD 00w01 ENA (rw): Enable main clock source update.
0x40048078 B  REGISTER SYSAHBCLKDIV (rw): System clock divider
0x40048078 C   FIELD 00w08 DIV (rw): System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.
0x40048080 B  REGISTER SYSAHBCLKCTRL (rw): System clock control
0x40048080 C   FIELD 00w01 SYS (rw): Enables the clock for the AHB, the APB bridge, the Cortex-M0+ core clocks, SYSCON, and the PMU. This bit is read only and always reads as 1.
0x40048080 C   FIELD 01w01 ROM (rw): Enables clock for ROM.
0x40048080 C   FIELD 02w01 RAM0_1 (rw): Enables clock for SRAM0 and SRAM1.
0x40048080 C   FIELD 03w01 FLASHREG (rw): Enables clock for flash register interface.
0x40048080 C   FIELD 04w01 FLASH (rw): Enables clock for flash.
0x40048080 C   FIELD 05w01 I2C0 (rw): Enables clock for I2C0.
0x40048080 C   FIELD 06w01 GPIO (rw): Enables clock for GPIO port registers and GPIO pin interrupt registers.
0x40048080 C   FIELD 07w01 SWM (rw): Enables clock for switch matrix.
0x40048080 C   FIELD 08w01 SCT (rw): Enables clock for state configurable timer SCTimer/PWM.
0x40048080 C   FIELD 09w01 WKT (rw): Enables clock for self-wake-up timer.
0x40048080 C   FIELD 10w01 MRT (rw): Enables clock for multi-rate timer.
0x40048080 C   FIELD 11w01 SPI0 (rw): Enables clock for SPI0.
0x40048080 C   FIELD 12w01 SPI1 (rw): Enables clock for SPI1.
0x40048080 C   FIELD 13w01 CRC (rw): Enables clock for CRC.
0x40048080 C   FIELD 14w01 UART0 (rw): Enables clock for USART0.
0x40048080 C   FIELD 15w01 UART1 (rw): Enables clock for USART1.
0x40048080 C   FIELD 16w01 UART2 (rw): Enables clock for USART2.
0x40048080 C   FIELD 17w01 WWDT (rw): Enables clock for WWDT.
0x40048080 C   FIELD 18w01 IOCON (rw): Enables clock for IOCON block.
0x40048080 C   FIELD 19w01 ACMP (rw): Enables clock to analog comparator.
0x40048094 B  REGISTER UARTCLKDIV (rw): USART clock divider
0x40048094 C   FIELD 00w08 DIV (rw): USART fractional baud rate generator clock divider values. 0: Clock disabled. 1: Divide by 1. to 255: Divide by 255.
0x400480E0 B  REGISTER CLKOUTSEL (rw): CLKOUT clock source select
0x400480E0 C   FIELD 00w02 SEL (rw): CLKOUT clock source.
0x400480E4 B  REGISTER CLKOUTUEN (rw): CLKOUT clock source update enable
0x400480E4 C   FIELD 00w01 ENA (rw): Enable CLKOUT clock source update.
0x400480E8 B  REGISTER CLKOUTDIV (rw): clock out divider
0x400480E8 C   FIELD 00w08 DIV (rw): CLKOUT clock divider values. 0: Disable CLKOUT clock divider 1: Divide by 1 to 255: Divide by 255
0x400480F0 B  REGISTER UARTFRGDIV (rw): USART common fractional generator divider value
0x400480F0 C   FIELD 00w08 DIV (rw): Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator.
0x400480F4 B  REGISTER UARTFRGMULT (rw): USART common fractional generator divider value
0x400480F4 C   FIELD 00w08 MULT (rw): Numerator of the fractional divider. MULT is equal to the programmed value.
0x400480FC B  REGISTER EXTTRACECMD (rw): External trace buffer command register
0x400480FC C   FIELD 00w01 START (rw): Trace start command. Writing a one to this bit sets the TSTART signal to the MTB to HIGH and starts tracing if the TSTARTEN bit in the MTB master register is set to one as well.
0x400480FC C   FIELD 01w01 STOP (rw): Trace stop command. Writing a one to this bit sets the TSTOP signal in the MTB to HIGH and stops tracing if the TSTOPEN bit in the MTB master register is set to one as well.
0x40048100 B  REGISTER PIOPORCAP0 (rw): POR captured PIO status 0
0x40048100 C   FIELD 00w18 PIOSTAT (ro): State of PIO0_17 through PIO0_0 at power-on reset
0x40048134 B  REGISTER IOCONCLKDIV6 (rw): Peripheral clock 6 to the IOCON block for programmable glitch filter
0x40048134 C   FIELD 00w08 DIV (rw): IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
0x40048138 B  REGISTER IOCONCLKDIV5 (rw): Peripheral clock 6 to the IOCON block for programmable glitch filter
0x40048138 C   FIELD 00w08 DIV (rw): IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
0x4004813C B  REGISTER IOCONCLKDIV4 (rw): Peripheral clock 4 to the IOCON block for programmable glitch filter
0x4004813C C   FIELD 00w08 DIV (rw): IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
0x40048140 B  REGISTER IOCONCLKDIV3 (rw): Peripheral clock 3 to the IOCON block for programmable glitch filter
0x40048140 C   FIELD 00w08 DIV (rw): IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
0x40048144 B  REGISTER IOCONCLKDIV2 (rw): Peripheral clock 2 to the IOCON block for programmable glitch filter
0x40048144 C   FIELD 00w08 DIV (rw): IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
0x40048148 B  REGISTER IOCONCLKDIV1 (rw): Peripheral clock 1 to the IOCON block for programmable glitch filter
0x40048148 C   FIELD 00w08 DIV (rw): IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
0x4004814C B  REGISTER IOCONCLKDIV0 (rw): Peripheral clock 0 to the IOCON block for programmable glitch filter
0x4004814C C   FIELD 00w08 DIV (rw): IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
0x40048150 B  REGISTER BODCTRL (rw): BOD control register
0x40048150 C   FIELD 00w02 BODRSTLEV (rw): BOD reset level
0x40048150 C   FIELD 02w02 BODINTVAL (rw): BOD interrupt level
0x40048150 C   FIELD 04w01 BODRSTENA (rw): BOD reset enable
0x40048154 B  REGISTER SYSTCKCAL (rw): System tick timer calibration register
0x40048154 C   FIELD 00w26 CAL (rw): System tick timer calibration value.
0x40048170 B  REGISTER IRQLATENCY (rw): IRQ latency register
0x40048170 C   FIELD 00w08 LATENCY (rw): 8-bit latency value.
0x40048174 B  REGISTER NMISRC (rw): NMI source selection register
0x40048174 C   FIELD 00w05 IRQN (rw): The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1
0x40048174 C   FIELD 31w01 NMIEN (rw): Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0.
0x40048178 B  REGISTER PINTSEL[0] (rw): Pin interrupt select registers N
0x40048178 C   FIELD 00w06 INTPIN (rw): Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
0x4004817C B  REGISTER PINTSEL[1] (rw): Pin interrupt select registers N
0x4004817C C   FIELD 00w06 INTPIN (rw): Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
0x40048180 B  REGISTER PINTSEL[2] (rw): Pin interrupt select registers N
0x40048180 C   FIELD 00w06 INTPIN (rw): Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
0x40048184 B  REGISTER PINTSEL[3] (rw): Pin interrupt select registers N
0x40048184 C   FIELD 00w06 INTPIN (rw): Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
0x40048188 B  REGISTER PINTSEL[4] (rw): Pin interrupt select registers N
0x40048188 C   FIELD 00w06 INTPIN (rw): Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
0x4004818C B  REGISTER PINTSEL[5] (rw): Pin interrupt select registers N
0x4004818C C   FIELD 00w06 INTPIN (rw): Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
0x40048190 B  REGISTER PINTSEL[6] (rw): Pin interrupt select registers N
0x40048190 C   FIELD 00w06 INTPIN (rw): Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
0x40048194 B  REGISTER PINTSEL[7] (rw): Pin interrupt select registers N
0x40048194 C   FIELD 00w06 INTPIN (rw): Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
0x40048204 B  REGISTER STARTERP0 (rw): Start logic 0 pin wake-up enable register 0
0x40048204 C   FIELD 00w01 PINT0 (rw): GPIO pin interrupt 0 wake-up
0x40048204 C   FIELD 01w01 PINT1 (rw): GPIO pin interrupt 1 wake-up
0x40048204 C   FIELD 02w01 PINT2 (rw): GPIO pin interrupt 2 wake-up
0x40048204 C   FIELD 03w01 PINT3 (rw): GPIO pin interrupt 3 wake-up
0x40048204 C   FIELD 04w01 PINT4 (rw): GPIO pin interrupt 4 wake-up
0x40048204 C   FIELD 05w01 PINT5 (rw): GPIO pin interrupt 5 wake-up
0x40048204 C   FIELD 06w01 PINT6 (rw): GPIO pin interrupt 6 wake-up
0x40048204 C   FIELD 07w01 PINT7 (rw): GPIO pin interrupt 7 wake-up
0x40048214 B  REGISTER STARTERP1 (rw): Start logic 0 pin wake-up enable register 1
0x40048214 C   FIELD 00w01 SPI0 (rw): SPI0 interrupt wake-up
0x40048214 C   FIELD 01w01 SPI1 (rw): SPI1 interrupt wake-up
0x40048214 C   FIELD 03w01 USART0 (rw): USART0 interrupt wake-up. Configure USART in synchronous slave mode.
0x40048214 C   FIELD 04w01 USART1 (rw): USART1 interrupt wake-up. Configure USART in synchronous slave mode.
0x40048214 C   FIELD 05w01 USART2 (rw): USART2 interrupt wake-up. Configure USART in synchronous slave mode.
0x40048214 C   FIELD 08w01 I2C0 (rw): I2C0 interrupt wake-up.
0x40048214 C   FIELD 12w01 WWDT (rw): WWDT interrupt wake-up
0x40048214 C   FIELD 13w01 BOD (rw): BOD interrupt wake-up
0x40048214 C   FIELD 15w01 WKT (rw): Self-wake-up timer interrupt wake-up
0x40048230 B  REGISTER PDSLEEPCFG (rw): Deep-sleep configuration register
0x40048230 C   FIELD 03w01 BOD_PD (rw): BOD power-down control for Deep-sleep and Power-down mode
0x40048230 C   FIELD 06w01 WDTOSC_PD (rw): Watchdog oscillator power-down control for Deep-sleep and Power-down mode. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running.
0x40048234 B  REGISTER PDAWAKECFG (rw): Wake-up configuration register
0x40048234 C   FIELD 00w01 IRCOUT_PD (rw): IRC oscillator output wake-up configuration
0x40048234 C   FIELD 01w01 IRC_PD (rw): IRC oscillator power-down wake-up configuration
0x40048234 C   FIELD 02w01 FLASH_PD (rw): Flash wake-up configuration
0x40048234 C   FIELD 03w01 BOD_PD (rw): BOD wake-up configuration
0x40048234 C   FIELD 05w01 SYSOSC_PD (rw): Crystal oscillator wake-up configuration
0x40048234 C   FIELD 06w01 WDTOSC_PD (rw): Watchdog oscillator wake-up configuration. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running
0x40048234 C   FIELD 07w01 SYSPLL_PD (rw): System PLL wake-up configuration
0x40048234 C   FIELD 15w01 ACMP (rw): Analog comparator wake-up configuration
0x40048238 B  REGISTER PDRUNCFG (rw): Power configuration register
0x40048238 C   FIELD 00w01 IRCOUT_PD (rw): IRC oscillator output wake-up configuration
0x40048238 C   FIELD 01w01 IRC_PD (rw): IRC oscillator power-down wake-up configuration
0x40048238 C   FIELD 02w01 FLASH_PD (rw): Flash wake-up configuration
0x40048238 C   FIELD 03w01 BOD_PD (rw): BOD wake-up configuration
0x40048238 C   FIELD 05w01 SYSOSC_PD (rw): Crystal oscillator wake-up configuration
0x40048238 C   FIELD 06w01 WDTOSC_PD (rw): Watchdog oscillator wake-up configuration. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running
0x40048238 C   FIELD 07w01 SYSPLL_PD (rw): System PLL wake-up configuration
0x40048238 C   FIELD 15w01 ACMP (rw): Analog comparator wake-up configuration
0x400483F8 B  REGISTER DEVICE_ID (ro): Part ID register
0x400483F8 C   FIELD 00w32 DEVICEID (ro): Part ID
0x40050000 A PERIPHERAL I2C0
0x40050000 B  REGISTER CFG (rw): Configuration for shared functions.
0x40050000 C   FIELD 00w01 MSTEN (rw): Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset.
0x40050000 C   FIELD 01w01 SLVEN (rw): Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset.
0x40050000 C   FIELD 02w01 MONEN (rw): Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset.
0x40050000 C   FIELD 03w01 TIMEOUTEN (rw): I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
0x40050000 C   FIELD 04w01 MONCLKSTR (rw): Monitor function Clock Stretching.
0x40050004 B  REGISTER STAT (rw): Status register for Master, Slave, and Monitor functions.
0x40050004 C   FIELD 00w01 MSTPENDING (ro): Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt.
0x40050004 C   FIELD 01w03 MSTSTATE (ro): Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses.
0x40050004 C   FIELD 04w01 MSTARBLOSS (rw): Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
0x40050004 C   FIELD 06w01 MSTSTSTPERR (rw): Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
0x40050004 C   FIELD 08w01 SLVPENDING (ro): Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched.
0x40050004 C   FIELD 09w02 SLVSTATE (ro): Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes.
0x40050004 C   FIELD 11w01 SLVNOTSTR (ro): Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time.
0x40050004 C   FIELD 12w02 SLVIDX (ro): Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here.
0x40050004 C   FIELD 14w01 SLVSEL (ro): Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data.
0x40050004 C   FIELD 15w01 SLVDESEL (rw): Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit.
0x40050004 C   FIELD 16w01 MONRDY (ro): Monitor Ready. This flag is cleared when the MONRXDAT register is read.
0x40050004 C   FIELD 17w01 MONOV (rw): Monitor Overflow flag.
0x40050004 C   FIELD 18w01 MONACTIVE (ro): Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop.
0x40050004 C   FIELD 19w01 MONIDLE (rw): Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit.
0x40050004 C   FIELD 24w01 EVENTTIMEOUT (rw): Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle.
0x40050004 C   FIELD 25w01 SCLTIMEOUT (rw): SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.
0x40050008 B  REGISTER INTENSET (rw): Interrupt Enable Set and read register.
0x40050008 C   FIELD 00w01 MSTPENDINGEN (rw): Master Pending interrupt Enable.
0x40050008 C   FIELD 04w01 MSTARBLOSSEN (rw): Master Arbitration Loss interrupt Enable.
0x40050008 C   FIELD 06w01 MSTSTSTPERREN (rw): Master Start/Stop Error interrupt Enable.
0x40050008 C   FIELD 08w01 SLVPENDINGEN (rw): Slave Pending interrupt Enable.
0x40050008 C   FIELD 11w01 SLVNOTSTREN (rw): Slave Not Stretching interrupt Enable.
0x40050008 C   FIELD 15w01 SLVDESELEN (rw): Slave Deselect interrupt Enable.
0x40050008 C   FIELD 16w01 MONRDYEN (rw): Monitor data Ready interrupt Enable.
0x40050008 C   FIELD 17w01 MONOVEN (rw): Monitor Overrun interrupt Enable.
0x40050008 C   FIELD 19w01 MONIDLEEN (rw): Monitor Idle interrupt Enable.
0x40050008 C   FIELD 24w01 EVENTTIMEOUTEN (rw): Event time-out interrupt Enable.
0x40050008 C   FIELD 25w01 SCLTIMEOUTEN (rw): SCL time-out interrupt Enable.
0x4005000C B  REGISTER INTENCLR (wo): Interrupt Enable Clear register.
0x4005000C C   FIELD 00w01 MSTPENDINGCLR (wo): Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented.
0x4005000C C   FIELD 04w01 MSTARBLOSSCLR (wo): Master Arbitration Loss interrupt clear.
0x4005000C C   FIELD 06w01 MSTSTSTPERRCLR (wo): Master Start/Stop Error interrupt clear.
0x4005000C C   FIELD 08w01 SLVPENDINGCLR (wo): Slave Pending interrupt clear.
0x4005000C C   FIELD 11w01 SLVNOTSTRCLR (wo): Slave Not Stretching interrupt clear.
0x4005000C C   FIELD 15w01 SLVDESELCLR (wo): Slave Deselect interrupt clear.
0x4005000C C   FIELD 16w01 MONRDYCLR (wo): Monitor data Ready interrupt clear.
0x4005000C C   FIELD 17w01 MONOVCLR (wo): Monitor Overrun interrupt clear.
0x4005000C C   FIELD 19w01 MONIDLECLR (wo): Monitor Idle interrupt clear.
0x4005000C C   FIELD 24w01 EVENTTIMEOUTCLR (wo): Event time-out interrupt clear.
0x4005000C C   FIELD 25w01 SCLTIMEOUTCLR (wo): SCL time-out interrupt clear.
0x40050010 B  REGISTER TIMEOUT (rw): Time-out value register.
0x40050010 C   FIELD 00w04 TOMIN (rw): Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.
0x40050010 C   FIELD 04w12 TO (rw): Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock.
0x40050014 B  REGISTER CLKDIV (rw): Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.
0x40050014 C   FIELD 00w16 DIVVAL (rw): This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use.
0x40050018 B  REGISTER INTSTAT (ro): Interrupt Status register for Master, Slave, and Monitor functions.
0x40050018 C   FIELD 00w01 MSTPENDING (ro): Master Pending.
0x40050018 C   FIELD 04w01 MSTARBLOSS (ro): Master Arbitration Loss flag.
0x40050018 C   FIELD 06w01 MSTSTSTPERR (ro): Master Start/Stop Error flag.
0x40050018 C   FIELD 08w01 SLVPENDING (ro): Slave Pending.
0x40050018 C   FIELD 11w01 SLVNOTSTR (ro): Slave Not Stretching status.
0x40050018 C   FIELD 15w01 SLVDESEL (ro): Slave Deselected flag.
0x40050018 C   FIELD 16w01 MONRDY (ro): Monitor Ready.
0x40050018 C   FIELD 17w01 MONOV (ro): Monitor Overflow flag.
0x40050018 C   FIELD 19w01 MONIDLE (ro): Monitor Idle flag.
0x40050018 C   FIELD 24w01 EVENTTIMEOUT (ro): Event time-out Interrupt flag.
0x40050018 C   FIELD 25w01 SCLTIMEOUT (ro): SCL time-out Interrupt flag.
0x40050020 B  REGISTER MSTCTL (rw): Master control register.
0x40050020 C   FIELD 00w01 MSTCONTINUE (rw): Master Continue.
0x40050020 C   FIELD 01w01 MSTSTART (rw): Master Start control.
0x40050020 C   FIELD 02w01 MSTSTOP (rw): Master Stop control.
0x40050024 B  REGISTER MSTTIME (rw): Master timing configuration.
0x40050024 C   FIELD 00w03 MSTSCLLOW (rw): Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.
0x40050024 C   FIELD 04w03 MSTSCLHIGH (rw): Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.
0x40050028 B  REGISTER MSTDAT (rw): Combined Master receiver and transmitter data register.
0x40050028 C   FIELD 00w08 DATA (rw): Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function.
0x40050040 B  REGISTER SLVCTL (rw): Slave control register.
0x40050040 C   FIELD 00w01 SLVCONTINUE (rw): Slave Continue.
0x40050040 C   FIELD 01w01 SLVNACK (rw): Slave NACK.
0x40050044 B  REGISTER SLVDAT (rw): Combined Slave receiver and transmitter data register.
0x40050044 C   FIELD 00w08 DATA (rw): Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function.
0x40050048 B  REGISTER SLVADR[0] (rw): Slave address register.
0x40050048 C   FIELD 00w01 SADISABLE (rw): Slave Address n Disable.
0x40050048 C   FIELD 01w07 SLVADR (rw): Slave Address. Seven bit slave address that is compared to received addresses if enabled.
0x4005004C B  REGISTER SLVADR[1] (rw): Slave address register.
0x4005004C C   FIELD 00w01 SADISABLE (rw): Slave Address n Disable.
0x4005004C C   FIELD 01w07 SLVADR (rw): Slave Address. Seven bit slave address that is compared to received addresses if enabled.
0x40050050 B  REGISTER SLVADR[2] (rw): Slave address register.
0x40050050 C   FIELD 00w01 SADISABLE (rw): Slave Address n Disable.
0x40050050 C   FIELD 01w07 SLVADR (rw): Slave Address. Seven bit slave address that is compared to received addresses if enabled.
0x40050054 B  REGISTER SLVADR[3] (rw): Slave address register.
0x40050054 C   FIELD 00w01 SADISABLE (rw): Slave Address n Disable.
0x40050054 C   FIELD 01w07 SLVADR (rw): Slave Address. Seven bit slave address that is compared to received addresses if enabled.
0x40050058 B  REGISTER SLVQUAL0 (rw): Slave Qualification for address 0.
0x40050058 C   FIELD 00w01 QUALMODE0 (rw): Qualify mode for slave address 0.
0x40050058 C   FIELD 01w07 SLVQUAL0 (rw): Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).
0x40050080 B  REGISTER MONRXDAT (ro): Monitor receiver data register.
0x40050080 C   FIELD 00w08 MONRXDAT (ro): Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.
0x40050080 C   FIELD 08w01 MONSTART (ro): Monitor Received Start.
0x40050080 C   FIELD 09w01 MONRESTART (ro): Monitor Received Repeated Start.
0x40050080 C   FIELD 10w01 MONNACK (ro): Monitor Received NACK.
0x40058000 A PERIPHERAL SPI0
0x40058000 B  REGISTER CFG (rw): SPI Configuration register
0x40058000 C   FIELD 00w01 ENABLE (rw): SPI enable.
0x40058000 C   FIELD 02w01 MASTER (rw): Master mode select.
0x40058000 C   FIELD 03w01 LSBF (rw): LSB First mode enable.
0x40058000 C   FIELD 04w01 CPHA (rw): Clock Phase select.
0x40058000 C   FIELD 05w01 CPOL (rw): Clock Polarity select.
0x40058000 C   FIELD 07w01 LOOP (rw): Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing.
0x40058000 C   FIELD 08w01 SPOL0 (rw): SSEL0 Polarity select.
0x40058004 B  REGISTER DLY (rw): SPI Delay register
0x40058004 C   FIELD 00w04 PRE_DELAY (rw): Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
0x40058004 C   FIELD 04w04 POST_DELAY (rw): Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
0x40058004 C   FIELD 08w04 FRAME_DELAY (rw): If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
0x40058004 C   FIELD 12w04 TRANSFER_DELAY (rw): Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times.
0x40058008 B  REGISTER STAT (rw): SPI Status. Some status flags can be cleared by writing a 1 to that bit position
0x40058008 C   FIELD 00w01 RXRDY (ro): Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register.
0x40058008 C   FIELD 01w01 TXRDY (ro): Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register.
0x40058008 C   FIELD 02w01 RXOV (wo): Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set.
0x40058008 C   FIELD 03w01 TXUR (wo): Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be considered undefined if TXUR is set.
0x40058008 C   FIELD 04w01 SSA (wo): Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software.
0x40058008 C   FIELD 05w01 SSD (wo): Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software.
0x40058008 C   FIELD 06w01 STALLED (ro): Stalled status flag. This indicates whether the SPI is currently in a stall condition.
0x40058008 C   FIELD 07w01 ENDTRANSFER (rw): End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
0x40058008 C   FIELD 08w01 MSTIDLE (ro): Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data.
0x4005800C B  REGISTER INTENSET (rw): SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0x4005800C C   FIELD 00w01 RXRDYEN (rw): Determines whether an interrupt occurs when receiver data is available.
0x4005800C C   FIELD 01w01 TXRDYEN (rw): Determines whether an interrupt occurs when the transmitter holding register is available.
0x4005800C C   FIELD 02w01 RXOVEN (rw): Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur.
0x4005800C C   FIELD 03w01 TXUREN (rw): Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available.
0x4005800C C   FIELD 04w01 SSAEN (rw): Determines whether an interrupt occurs when the Slave Select is asserted.
0x4005800C C   FIELD 05w01 SSDEN (rw): Determines whether an interrupt occurs when the Slave Select is deasserted.
0x40058010 B  REGISTER INTENCLR (wo): SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
0x40058010 C   FIELD 00w01 RXRDYEN (wo): Writing 1 clears the corresponding bits in the INTENSET register.
0x40058010 C   FIELD 01w01 TXRDYEN (wo): Writing 1 clears the corresponding bits in the INTENSET register.
0x40058010 C   FIELD 02w01 RXOVEN (wo): Writing 1 clears the corresponding bits in the INTENSET register.
0x40058010 C   FIELD 03w01 TXUREN (wo): Writing 1 clears the corresponding bits in the INTENSET register.
0x40058010 C   FIELD 04w01 SSAEN (wo): Writing 1 clears the corresponding bits in the INTENSET register.
0x40058010 C   FIELD 05w01 SSDEN (wo): Writing 1 clears the corresponding bits in the INTENSET register.
0x40058014 B  REGISTER RXDAT (ro): SPI Receive Data
0x40058014 C   FIELD 00w16 RXDAT (ro): Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL.
0x40058014 C   FIELD 16w01 RXSSEL0_N (ro): Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
0x40058014 C   FIELD 20w01 SOT (ro): Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit.
0x40058018 B  REGISTER TXDATCTL (rw): SPI Transmit Data with Control
0x40058018 C   FIELD 00w16 TXDAT (rw): Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.
0x40058018 C   FIELD 16w01 TXSSEL0_N (rw): Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register.
0x40058018 C   FIELD 20w01 EOT (rw): End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.
0x40058018 C   FIELD 21w01 EOF (rw): End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.
0x40058018 C   FIELD 22w01 RXIGNORE (rw): Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA.
0x40058018 C   FIELD 24w04 LEN (rw): Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length.
0x4005801C B  REGISTER TXDAT (rw): SPI Transmit Data.
0x4005801C C   FIELD 00w16 DATA (rw): Transmit Data. This field provides from 4 to 16 bits of data to be transmitted.
0x40058020 B  REGISTER TXCTL (rw): SPI Transmit Control
0x40058020 C   FIELD 16w01 TXSSEL0_N (rw): Transmit Slave Select 0.
0x40058020 C   FIELD 20w01 EOT (rw): End of Transfer.
0x40058020 C   FIELD 21w01 EOF (rw): End of Frame.
0x40058020 C   FIELD 22w01 RXIGNORE (rw): Receive Ignore.
0x40058020 C   FIELD 24w04 LEN (rw): Data transfer Length.
0x40058024 B  REGISTER DIV (rw): SPI clock Divider
0x40058024 C   FIELD 00w16 DIVVAL (rw): Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536.
0x40058028 B  REGISTER INTSTAT (rw): SPI Interrupt Status
0x40058028 C   FIELD 00w01 RXRDY (ro): Receiver Ready flag.
0x40058028 C   FIELD 01w01 TXRDY (ro): Transmitter Ready flag.
0x40058028 C   FIELD 02w01 RXOV (ro): Receiver Overrun interrupt flag.
0x40058028 C   FIELD 03w01 TXUR (ro): Transmitter Underrun interrupt flag.
0x40058028 C   FIELD 04w01 SSA (ro): Slave Select Assert.
0x40058028 C   FIELD 05w01 SSD (ro): Slave Select Deassert.
0x4005C000 A PERIPHERAL SPI1
0x4005C000 B  REGISTER CFG (rw): SPI Configuration register
0x4005C000 C   FIELD 00w01 ENABLE (rw): SPI enable.
0x4005C000 C   FIELD 02w01 MASTER (rw): Master mode select.
0x4005C000 C   FIELD 03w01 LSBF (rw): LSB First mode enable.
0x4005C000 C   FIELD 04w01 CPHA (rw): Clock Phase select.
0x4005C000 C   FIELD 05w01 CPOL (rw): Clock Polarity select.
0x4005C000 C   FIELD 07w01 LOOP (rw): Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing.
0x4005C000 C   FIELD 08w01 SPOL0 (rw): SSEL0 Polarity select.
0x4005C004 B  REGISTER DLY (rw): SPI Delay register
0x4005C004 C   FIELD 00w04 PRE_DELAY (rw): Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
0x4005C004 C   FIELD 04w04 POST_DELAY (rw): Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
0x4005C004 C   FIELD 08w04 FRAME_DELAY (rw): If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
0x4005C004 C   FIELD 12w04 TRANSFER_DELAY (rw): Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times.
0x4005C008 B  REGISTER STAT (rw): SPI Status. Some status flags can be cleared by writing a 1 to that bit position
0x4005C008 C   FIELD 00w01 RXRDY (ro): Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register.
0x4005C008 C   FIELD 01w01 TXRDY (ro): Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register.
0x4005C008 C   FIELD 02w01 RXOV (wo): Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set.
0x4005C008 C   FIELD 03w01 TXUR (wo): Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be considered undefined if TXUR is set.
0x4005C008 C   FIELD 04w01 SSA (wo): Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software.
0x4005C008 C   FIELD 05w01 SSD (wo): Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software.
0x4005C008 C   FIELD 06w01 STALLED (ro): Stalled status flag. This indicates whether the SPI is currently in a stall condition.
0x4005C008 C   FIELD 07w01 ENDTRANSFER (rw): End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
0x4005C008 C   FIELD 08w01 MSTIDLE (ro): Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data.
0x4005C00C B  REGISTER INTENSET (rw): SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0x4005C00C C   FIELD 00w01 RXRDYEN (rw): Determines whether an interrupt occurs when receiver data is available.
0x4005C00C C   FIELD 01w01 TXRDYEN (rw): Determines whether an interrupt occurs when the transmitter holding register is available.
0x4005C00C C   FIELD 02w01 RXOVEN (rw): Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur.
0x4005C00C C   FIELD 03w01 TXUREN (rw): Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available.
0x4005C00C C   FIELD 04w01 SSAEN (rw): Determines whether an interrupt occurs when the Slave Select is asserted.
0x4005C00C C   FIELD 05w01 SSDEN (rw): Determines whether an interrupt occurs when the Slave Select is deasserted.
0x4005C010 B  REGISTER INTENCLR (wo): SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
0x4005C010 C   FIELD 00w01 RXRDYEN (wo): Writing 1 clears the corresponding bits in the INTENSET register.
0x4005C010 C   FIELD 01w01 TXRDYEN (wo): Writing 1 clears the corresponding bits in the INTENSET register.
0x4005C010 C   FIELD 02w01 RXOVEN (wo): Writing 1 clears the corresponding bits in the INTENSET register.
0x4005C010 C   FIELD 03w01 TXUREN (wo): Writing 1 clears the corresponding bits in the INTENSET register.
0x4005C010 C   FIELD 04w01 SSAEN (wo): Writing 1 clears the corresponding bits in the INTENSET register.
0x4005C010 C   FIELD 05w01 SSDEN (wo): Writing 1 clears the corresponding bits in the INTENSET register.
0x4005C014 B  REGISTER RXDAT (ro): SPI Receive Data
0x4005C014 C   FIELD 00w16 RXDAT (ro): Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL.
0x4005C014 C   FIELD 16w01 RXSSEL0_N (ro): Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
0x4005C014 C   FIELD 20w01 SOT (ro): Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit.
0x4005C018 B  REGISTER TXDATCTL (rw): SPI Transmit Data with Control
0x4005C018 C   FIELD 00w16 TXDAT (rw): Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.
0x4005C018 C   FIELD 16w01 TXSSEL0_N (rw): Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register.
0x4005C018 C   FIELD 20w01 EOT (rw): End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.
0x4005C018 C   FIELD 21w01 EOF (rw): End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.
0x4005C018 C   FIELD 22w01 RXIGNORE (rw): Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA.
0x4005C018 C   FIELD 24w04 LEN (rw): Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length.
0x4005C01C B  REGISTER TXDAT (rw): SPI Transmit Data.
0x4005C01C C   FIELD 00w16 DATA (rw): Transmit Data. This field provides from 4 to 16 bits of data to be transmitted.
0x4005C020 B  REGISTER TXCTL (rw): SPI Transmit Control
0x4005C020 C   FIELD 16w01 TXSSEL0_N (rw): Transmit Slave Select 0.
0x4005C020 C   FIELD 20w01 EOT (rw): End of Transfer.
0x4005C020 C   FIELD 21w01 EOF (rw): End of Frame.
0x4005C020 C   FIELD 22w01 RXIGNORE (rw): Receive Ignore.
0x4005C020 C   FIELD 24w04 LEN (rw): Data transfer Length.
0x4005C024 B  REGISTER DIV (rw): SPI clock Divider
0x4005C024 C   FIELD 00w16 DIVVAL (rw): Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536.
0x4005C028 B  REGISTER INTSTAT (rw): SPI Interrupt Status
0x4005C028 C   FIELD 00w01 RXRDY (ro): Receiver Ready flag.
0x4005C028 C   FIELD 01w01 TXRDY (ro): Transmitter Ready flag.
0x4005C028 C   FIELD 02w01 RXOV (ro): Receiver Overrun interrupt flag.
0x4005C028 C   FIELD 03w01 TXUR (ro): Transmitter Underrun interrupt flag.
0x4005C028 C   FIELD 04w01 SSA (ro): Slave Select Assert.
0x4005C028 C   FIELD 05w01 SSD (ro): Slave Select Deassert.
0x40064000 A PERIPHERAL USART0
0x40064000 B  REGISTER CFG (rw): USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
0x40064000 C   FIELD 00w01 ENABLE (rw): USART Enable.
0x40064000 C   FIELD 02w02 DATALEN (rw): Selects the data size for the USART.
0x40064000 C   FIELD 04w02 PARITYSEL (rw): Selects what type of parity is used by the USART.
0x40064000 C   FIELD 06w01 STOPLEN (rw): Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
0x40064000 C   FIELD 09w01 CTSEN (rw): CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.
0x40064000 C   FIELD 11w01 SYNCEN (rw): Selects synchronous or asynchronous operation.
0x40064000 C   FIELD 12w01 CLKPOL (rw): Selects the clock polarity and sampling edge of received data in synchronous mode.
0x40064000 C   FIELD 14w01 SYNCMST (rw): Synchronous mode Master select.
0x40064000 C   FIELD 15w01 LOOP (rw): Selects data loopback mode.
0x40064004 B  REGISTER CTL (rw): USART Control register. USART control settings that are more likely to change during operation.
0x40064004 C   FIELD 01w01 TXBRKEN (rw): Break Enable.
0x40064004 C   FIELD 02w01 ADDRDET (rw): Enable address detect mode.
0x40064004 C   FIELD 06w01 TXDIS (rw): Transmit Disable.
0x40064004 C   FIELD 08w01 CC (rw): Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
0x40064004 C   FIELD 09w01 CLRCCONRX (rw): Clear Continuous Clock.
0x40064008 B  REGISTER STAT (rw): USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
0x40064008 C   FIELD 00w01 RXRDY (ro): Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers.
0x40064008 C   FIELD 01w01 RXIDLE (ro): Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.
0x40064008 C   FIELD 02w01 TXRDY (ro): Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register.
0x40064008 C   FIELD 03w01 TXIDLE (ro): Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.
0x40064008 C   FIELD 04w01 CTS (ro): This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.
0x40064008 C   FIELD 05w01 DELTACTS (wo): This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
0x40064008 C   FIELD 06w01 TXDISSTAT (ro): Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1).
0x40064008 C   FIELD 08w01 OVERRUNINT (wo): Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost.
0x40064008 C   FIELD 10w01 RXBRK (ro): Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.
0x40064008 C   FIELD 11w01 DELTARXBRK (wo): This bit is set when a change in the state of receiver break detection occurs.Cleared by software.
0x40064008 C   FIELD 12w01 START (wo): This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.
0x40064008 C   FIELD 13w01 FRAMERRINT (wo): Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
0x40064008 C   FIELD 14w01 PARITYERRINT (wo): Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.
0x40064008 C   FIELD 15w01 RXNOISEINT (wo): Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.
0x4006400C B  REGISTER INTENSET (rw): Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0x4006400C C   FIELD 00w01 RXRDYEN (rw): When 1, enables an interrupt when there is a received character available to be read from the RXDAT register.
0x4006400C C   FIELD 02w01 TXRDYEN (rw): When 1, enables an interrupt when the TXDAT register is available to take another character to transmit.
0x4006400C C   FIELD 05w01 DELTACTSEN (rw): When 1, enables an interrupt when there is a change in the state of the CTS input.
0x4006400C C   FIELD 06w01 TXDISEN (rw): When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
0x4006400C C   FIELD 08w01 OVERRUNEN (rw): When 1, enables an interrupt when an overrun error occurred.
0x4006400C C   FIELD 11w01 DELTARXBRKEN (rw): When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).
0x4006400C C   FIELD 12w01 STARTEN (rw): When 1, enables an interrupt when a received start bit has been detected.
0x4006400C C   FIELD 13w01 FRAMERREN (rw): When 1, enables an interrupt when a framing error has been detected.
0x4006400C C   FIELD 14w01 PARITYERREN (rw): When 1, enables an interrupt when a parity error has been detected.
0x4006400C C   FIELD 15w01 RXNOISEEN (rw): When 1, enables an interrupt when noise is detected.
0x40064010 B  REGISTER INTENCLR (wo): Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
0x40064010 C   FIELD 00w01 RXRDYCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40064010 C   FIELD 02w01 TXRDYCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40064010 C   FIELD 05w01 DELTACTSCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40064010 C   FIELD 06w01 TXDISINTCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40064010 C   FIELD 08w01 OVERRUNCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40064010 C   FIELD 11w01 DELTARXBRKCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40064010 C   FIELD 12w01 STARTCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40064010 C   FIELD 13w01 FRAMERRCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40064010 C   FIELD 14w01 PARITYERRCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40064010 C   FIELD 15w01 RXNOISECLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40064014 B  REGISTER RXDAT (ro): Receiver Data register. Contains the last character received.
0x40064014 C   FIELD 00w09 RXDAT (ro): The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0x40064018 B  REGISTER RXDATSTAT (ro): Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.
0x40064018 C   FIELD 00w09 RXDAT (ro): The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0x40064018 C   FIELD 13w01 FRAMERR (ro): Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
0x40064018 C   FIELD 14w01 PARITYERR (ro): Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.
0x40064018 C   FIELD 15w01 RXNOISE (ro): Received Noise flag.
0x4006401C B  REGISTER TXDAT (rw): Transmit Data register. Data to be transmitted is written here.
0x4006401C C   FIELD 00w09 TXDAT (rw): Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0.
0x40064020 B  REGISTER BRG (rw): Baud Rate Generator register. 16-bit integer baud rate divisor value.
0x40064020 C   FIELD 00w16 BRGVAL (rw): This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function.
0x40064024 B  REGISTER INTSTAT (rw): Interrupt status register. Reflects interrupts that are currently enabled.
0x40064024 C   FIELD 00w01 RXRDY (ro): Receiver Ready flag.
0x40064024 C   FIELD 02w01 TXRDY (ro): Transmitter Ready flag.
0x40064024 C   FIELD 05w01 DELTACTS (ro): This bit is set when a change in the state of the CTS input is detected.
0x40064024 C   FIELD 06w01 TXDISINT (ro): Transmitter Disabled Interrupt flag.
0x40064024 C   FIELD 08w01 OVERRUNINT (ro): Overrun Error interrupt flag.
0x40064024 C   FIELD 11w01 DELTARXBRK (ro): This bit is set when a change in the state of receiver break detection occurs.
0x40064024 C   FIELD 12w01 START (ro): This bit is set when a start is detected on the receiver input.
0x40064024 C   FIELD 13w01 FRAMERRINT (ro): Framing Error interrupt flag.
0x40064024 C   FIELD 14w01 PARITYERRINT (ro): Parity Error interrupt flag.
0x40064024 C   FIELD 15w01 RXNOISEINT (ro): Received Noise interrupt flag.
0x40068000 A PERIPHERAL USART1
0x40068000 B  REGISTER CFG (rw): USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
0x40068000 C   FIELD 00w01 ENABLE (rw): USART Enable.
0x40068000 C   FIELD 02w02 DATALEN (rw): Selects the data size for the USART.
0x40068000 C   FIELD 04w02 PARITYSEL (rw): Selects what type of parity is used by the USART.
0x40068000 C   FIELD 06w01 STOPLEN (rw): Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
0x40068000 C   FIELD 09w01 CTSEN (rw): CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.
0x40068000 C   FIELD 11w01 SYNCEN (rw): Selects synchronous or asynchronous operation.
0x40068000 C   FIELD 12w01 CLKPOL (rw): Selects the clock polarity and sampling edge of received data in synchronous mode.
0x40068000 C   FIELD 14w01 SYNCMST (rw): Synchronous mode Master select.
0x40068000 C   FIELD 15w01 LOOP (rw): Selects data loopback mode.
0x40068004 B  REGISTER CTL (rw): USART Control register. USART control settings that are more likely to change during operation.
0x40068004 C   FIELD 01w01 TXBRKEN (rw): Break Enable.
0x40068004 C   FIELD 02w01 ADDRDET (rw): Enable address detect mode.
0x40068004 C   FIELD 06w01 TXDIS (rw): Transmit Disable.
0x40068004 C   FIELD 08w01 CC (rw): Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
0x40068004 C   FIELD 09w01 CLRCCONRX (rw): Clear Continuous Clock.
0x40068008 B  REGISTER STAT (rw): USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
0x40068008 C   FIELD 00w01 RXRDY (ro): Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers.
0x40068008 C   FIELD 01w01 RXIDLE (ro): Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.
0x40068008 C   FIELD 02w01 TXRDY (ro): Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register.
0x40068008 C   FIELD 03w01 TXIDLE (ro): Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.
0x40068008 C   FIELD 04w01 CTS (ro): This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.
0x40068008 C   FIELD 05w01 DELTACTS (wo): This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
0x40068008 C   FIELD 06w01 TXDISSTAT (ro): Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1).
0x40068008 C   FIELD 08w01 OVERRUNINT (wo): Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost.
0x40068008 C   FIELD 10w01 RXBRK (ro): Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.
0x40068008 C   FIELD 11w01 DELTARXBRK (wo): This bit is set when a change in the state of receiver break detection occurs.Cleared by software.
0x40068008 C   FIELD 12w01 START (wo): This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.
0x40068008 C   FIELD 13w01 FRAMERRINT (wo): Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
0x40068008 C   FIELD 14w01 PARITYERRINT (wo): Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.
0x40068008 C   FIELD 15w01 RXNOISEINT (wo): Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.
0x4006800C B  REGISTER INTENSET (rw): Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0x4006800C C   FIELD 00w01 RXRDYEN (rw): When 1, enables an interrupt when there is a received character available to be read from the RXDAT register.
0x4006800C C   FIELD 02w01 TXRDYEN (rw): When 1, enables an interrupt when the TXDAT register is available to take another character to transmit.
0x4006800C C   FIELD 05w01 DELTACTSEN (rw): When 1, enables an interrupt when there is a change in the state of the CTS input.
0x4006800C C   FIELD 06w01 TXDISEN (rw): When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
0x4006800C C   FIELD 08w01 OVERRUNEN (rw): When 1, enables an interrupt when an overrun error occurred.
0x4006800C C   FIELD 11w01 DELTARXBRKEN (rw): When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).
0x4006800C C   FIELD 12w01 STARTEN (rw): When 1, enables an interrupt when a received start bit has been detected.
0x4006800C C   FIELD 13w01 FRAMERREN (rw): When 1, enables an interrupt when a framing error has been detected.
0x4006800C C   FIELD 14w01 PARITYERREN (rw): When 1, enables an interrupt when a parity error has been detected.
0x4006800C C   FIELD 15w01 RXNOISEEN (rw): When 1, enables an interrupt when noise is detected.
0x40068010 B  REGISTER INTENCLR (wo): Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
0x40068010 C   FIELD 00w01 RXRDYCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40068010 C   FIELD 02w01 TXRDYCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40068010 C   FIELD 05w01 DELTACTSCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40068010 C   FIELD 06w01 TXDISINTCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40068010 C   FIELD 08w01 OVERRUNCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40068010 C   FIELD 11w01 DELTARXBRKCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40068010 C   FIELD 12w01 STARTCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40068010 C   FIELD 13w01 FRAMERRCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40068010 C   FIELD 14w01 PARITYERRCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40068010 C   FIELD 15w01 RXNOISECLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x40068014 B  REGISTER RXDAT (ro): Receiver Data register. Contains the last character received.
0x40068014 C   FIELD 00w09 RXDAT (ro): The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0x40068018 B  REGISTER RXDATSTAT (ro): Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.
0x40068018 C   FIELD 00w09 RXDAT (ro): The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0x40068018 C   FIELD 13w01 FRAMERR (ro): Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
0x40068018 C   FIELD 14w01 PARITYERR (ro): Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.
0x40068018 C   FIELD 15w01 RXNOISE (ro): Received Noise flag.
0x4006801C B  REGISTER TXDAT (rw): Transmit Data register. Data to be transmitted is written here.
0x4006801C C   FIELD 00w09 TXDAT (rw): Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0.
0x40068020 B  REGISTER BRG (rw): Baud Rate Generator register. 16-bit integer baud rate divisor value.
0x40068020 C   FIELD 00w16 BRGVAL (rw): This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function.
0x40068024 B  REGISTER INTSTAT (rw): Interrupt status register. Reflects interrupts that are currently enabled.
0x40068024 C   FIELD 00w01 RXRDY (ro): Receiver Ready flag.
0x40068024 C   FIELD 02w01 TXRDY (ro): Transmitter Ready flag.
0x40068024 C   FIELD 05w01 DELTACTS (ro): This bit is set when a change in the state of the CTS input is detected.
0x40068024 C   FIELD 06w01 TXDISINT (ro): Transmitter Disabled Interrupt flag.
0x40068024 C   FIELD 08w01 OVERRUNINT (ro): Overrun Error interrupt flag.
0x40068024 C   FIELD 11w01 DELTARXBRK (ro): This bit is set when a change in the state of receiver break detection occurs.
0x40068024 C   FIELD 12w01 START (ro): This bit is set when a start is detected on the receiver input.
0x40068024 C   FIELD 13w01 FRAMERRINT (ro): Framing Error interrupt flag.
0x40068024 C   FIELD 14w01 PARITYERRINT (ro): Parity Error interrupt flag.
0x40068024 C   FIELD 15w01 RXNOISEINT (ro): Received Noise interrupt flag.
0x4006C000 A PERIPHERAL USART2
0x4006C000 B  REGISTER CFG (rw): USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
0x4006C000 C   FIELD 00w01 ENABLE (rw): USART Enable.
0x4006C000 C   FIELD 02w02 DATALEN (rw): Selects the data size for the USART.
0x4006C000 C   FIELD 04w02 PARITYSEL (rw): Selects what type of parity is used by the USART.
0x4006C000 C   FIELD 06w01 STOPLEN (rw): Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
0x4006C000 C   FIELD 09w01 CTSEN (rw): CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.
0x4006C000 C   FIELD 11w01 SYNCEN (rw): Selects synchronous or asynchronous operation.
0x4006C000 C   FIELD 12w01 CLKPOL (rw): Selects the clock polarity and sampling edge of received data in synchronous mode.
0x4006C000 C   FIELD 14w01 SYNCMST (rw): Synchronous mode Master select.
0x4006C000 C   FIELD 15w01 LOOP (rw): Selects data loopback mode.
0x4006C004 B  REGISTER CTL (rw): USART Control register. USART control settings that are more likely to change during operation.
0x4006C004 C   FIELD 01w01 TXBRKEN (rw): Break Enable.
0x4006C004 C   FIELD 02w01 ADDRDET (rw): Enable address detect mode.
0x4006C004 C   FIELD 06w01 TXDIS (rw): Transmit Disable.
0x4006C004 C   FIELD 08w01 CC (rw): Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
0x4006C004 C   FIELD 09w01 CLRCCONRX (rw): Clear Continuous Clock.
0x4006C008 B  REGISTER STAT (rw): USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
0x4006C008 C   FIELD 00w01 RXRDY (ro): Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers.
0x4006C008 C   FIELD 01w01 RXIDLE (ro): Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.
0x4006C008 C   FIELD 02w01 TXRDY (ro): Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register.
0x4006C008 C   FIELD 03w01 TXIDLE (ro): Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.
0x4006C008 C   FIELD 04w01 CTS (ro): This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.
0x4006C008 C   FIELD 05w01 DELTACTS (wo): This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
0x4006C008 C   FIELD 06w01 TXDISSTAT (ro): Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1).
0x4006C008 C   FIELD 08w01 OVERRUNINT (wo): Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost.
0x4006C008 C   FIELD 10w01 RXBRK (ro): Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.
0x4006C008 C   FIELD 11w01 DELTARXBRK (wo): This bit is set when a change in the state of receiver break detection occurs.Cleared by software.
0x4006C008 C   FIELD 12w01 START (wo): This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.
0x4006C008 C   FIELD 13w01 FRAMERRINT (wo): Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
0x4006C008 C   FIELD 14w01 PARITYERRINT (wo): Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.
0x4006C008 C   FIELD 15w01 RXNOISEINT (wo): Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.
0x4006C00C B  REGISTER INTENSET (rw): Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0x4006C00C C   FIELD 00w01 RXRDYEN (rw): When 1, enables an interrupt when there is a received character available to be read from the RXDAT register.
0x4006C00C C   FIELD 02w01 TXRDYEN (rw): When 1, enables an interrupt when the TXDAT register is available to take another character to transmit.
0x4006C00C C   FIELD 05w01 DELTACTSEN (rw): When 1, enables an interrupt when there is a change in the state of the CTS input.
0x4006C00C C   FIELD 06w01 TXDISEN (rw): When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
0x4006C00C C   FIELD 08w01 OVERRUNEN (rw): When 1, enables an interrupt when an overrun error occurred.
0x4006C00C C   FIELD 11w01 DELTARXBRKEN (rw): When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).
0x4006C00C C   FIELD 12w01 STARTEN (rw): When 1, enables an interrupt when a received start bit has been detected.
0x4006C00C C   FIELD 13w01 FRAMERREN (rw): When 1, enables an interrupt when a framing error has been detected.
0x4006C00C C   FIELD 14w01 PARITYERREN (rw): When 1, enables an interrupt when a parity error has been detected.
0x4006C00C C   FIELD 15w01 RXNOISEEN (rw): When 1, enables an interrupt when noise is detected.
0x4006C010 B  REGISTER INTENCLR (wo): Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
0x4006C010 C   FIELD 00w01 RXRDYCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x4006C010 C   FIELD 02w01 TXRDYCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x4006C010 C   FIELD 05w01 DELTACTSCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x4006C010 C   FIELD 06w01 TXDISINTCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x4006C010 C   FIELD 08w01 OVERRUNCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x4006C010 C   FIELD 11w01 DELTARXBRKCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x4006C010 C   FIELD 12w01 STARTCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x4006C010 C   FIELD 13w01 FRAMERRCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x4006C010 C   FIELD 14w01 PARITYERRCLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x4006C010 C   FIELD 15w01 RXNOISECLR (wo): Writing 1 clears the corresponding bit in the INTENSET register.
0x4006C014 B  REGISTER RXDAT (ro): Receiver Data register. Contains the last character received.
0x4006C014 C   FIELD 00w09 RXDAT (ro): The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0x4006C018 B  REGISTER RXDATSTAT (ro): Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.
0x4006C018 C   FIELD 00w09 RXDAT (ro): The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0x4006C018 C   FIELD 13w01 FRAMERR (ro): Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
0x4006C018 C   FIELD 14w01 PARITYERR (ro): Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.
0x4006C018 C   FIELD 15w01 RXNOISE (ro): Received Noise flag.
0x4006C01C B  REGISTER TXDAT (rw): Transmit Data register. Data to be transmitted is written here.
0x4006C01C C   FIELD 00w09 TXDAT (rw): Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0.
0x4006C020 B  REGISTER BRG (rw): Baud Rate Generator register. 16-bit integer baud rate divisor value.
0x4006C020 C   FIELD 00w16 BRGVAL (rw): This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function.
0x4006C024 B  REGISTER INTSTAT (rw): Interrupt status register. Reflects interrupts that are currently enabled.
0x4006C024 C   FIELD 00w01 RXRDY (ro): Receiver Ready flag.
0x4006C024 C   FIELD 02w01 TXRDY (ro): Transmitter Ready flag.
0x4006C024 C   FIELD 05w01 DELTACTS (ro): This bit is set when a change in the state of the CTS input is detected.
0x4006C024 C   FIELD 06w01 TXDISINT (ro): Transmitter Disabled Interrupt flag.
0x4006C024 C   FIELD 08w01 OVERRUNINT (ro): Overrun Error interrupt flag.
0x4006C024 C   FIELD 11w01 DELTARXBRK (ro): This bit is set when a change in the state of receiver break detection occurs.
0x4006C024 C   FIELD 12w01 START (ro): This bit is set when a start is detected on the receiver input.
0x4006C024 C   FIELD 13w01 FRAMERRINT (ro): Framing Error interrupt flag.
0x4006C024 C   FIELD 14w01 PARITYERRINT (ro): Parity Error interrupt flag.
0x4006C024 C   FIELD 15w01 RXNOISEINT (ro): Received Noise interrupt flag.
0x50000000 A PERIPHERAL CRC
0x50000000 B  REGISTER MODE (rw): CRC mode register
0x50000000 C   FIELD 00w02 CRC_POLY (rw): CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
0x50000000 C   FIELD 02w01 BIT_RVS_WR (rw): Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
0x50000000 C   FIELD 03w01 CMPL_WR (rw): Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
0x50000000 C   FIELD 04w01 BIT_RVS_SUM (rw): CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
0x50000000 C   FIELD 05w01 CMPL_SUM (rw): CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
0x50000004 B  REGISTER SEED (rw): CRC seed register
0x50000004 C   FIELD 00w32 CRC_SEED (rw): A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses.
0x50000008 B  REGISTER SUM (ro): CRC checksum register
0x50000008 B  REGISTER WR_DATA (wo): CRC data register
0x50000008 C   FIELD 00w32 CRC_SUM (ro): The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
0x50000008 C   FIELD 00w32 CRC_WR_DATA (wo): Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions.
0x50004000 A PERIPHERAL SCT0
0x50004000 B  REGISTER CONFIG (rw): SCT configuration register
0x50004000 C   FIELD 00w01 UNIFY (rw): SCT operation
0x50004000 C   FIELD 01w02 CLKMODE (rw): SCT clock mode
0x50004000 C   FIELD 03w04 CKSEL (rw): SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register.
0x50004000 C   FIELD 07w01 NORELOAD_L (rw): A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
0x50004000 C   FIELD 08w01 NORELOAD_H (rw): A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.
0x50004000 C   FIELD 09w08 INSYNC (rw): Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field.
0x50004000 C   FIELD 17w01 AUTOLIMIT_L (rw): A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
0x50004000 C   FIELD 18w01 AUTOLIMIT_H (rw): A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.
0x50004004 B  REGISTER CTRL (rw): SCT control register
0x50004004 C   FIELD 00w01 DOWN_L (rw): This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.
0x50004004 C   FIELD 01w01 STOP_L (rw): When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes.
0x50004004 C   FIELD 02w01 HALT_L (rw): When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset.
0x50004004 C   FIELD 03w01 CLRCTR_L (rw): Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
0x50004004 C   FIELD 04w01 BIDIR_L (rw): L or unified counter direction select
0x50004004 C   FIELD 05w08 PRE_L (rw): Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
0x50004004 C   FIELD 16w01 DOWN_H (rw): This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.
0x50004004 C   FIELD 17w01 STOP_H (rw): When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.
0x50004004 C   FIELD 18w01 HALT_H (rw): When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset.
0x50004004 C   FIELD 19w01 CLRCTR_H (rw): Writing a 1 to this bit clears the H counter. This bit always reads as 0.
0x50004004 C   FIELD 20w01 BIDIR_H (rw): Direction select
0x50004004 C   FIELD 21w08 PRE_H (rw): Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
0x50004008 B  REGISTER LIMIT (rw): SCT limit event select register
0x50004008 C   FIELD 00w06 LIMMSK_L (rw): If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0x50004008 C   FIELD 16w06 LIMMSK_H (rw): If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
0x5000400C B  REGISTER HALT (rw): SCT halt event select register
0x5000400C C   FIELD 00w06 HALTMSK_L (rw): If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0x5000400C C   FIELD 16w06 HALTMSK_H (rw): If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
0x50004010 B  REGISTER STOP (rw): SCT stop event select register
0x50004010 C   FIELD 00w06 STOPMSK_L (rw): If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0x50004010 C   FIELD 16w06 STOPMSK_H (rw): If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
0x50004014 B  REGISTER START (rw): SCT start event select register
0x50004014 C   FIELD 00w06 STARTMSK_L (rw): If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0x50004014 C   FIELD 16w06 STARTMSK_H (rw): If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
0x50004040 B  REGISTER COUNT (rw): SCT counter register
0x50004040 C   FIELD 00w16 CTR_L (rw): When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter.
0x50004040 C   FIELD 16w16 CTR_H (rw): When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter.
0x50004044 B  REGISTER STATE (rw): SCT state register
0x50004044 C   FIELD 00w05 STATE_L (rw): State variable.
0x50004044 C   FIELD 16w05 STATE_H (rw): State variable.
0x50004048 B  REGISTER INPUT (rw): SCT input register
0x50004048 C   FIELD 00w01 AIN0 (ro): Input 0 state. Input 0 state on the last SCT clock edge.
0x50004048 C   FIELD 01w01 AIN1 (ro): Input 1 state. Input 1 state on the last SCT clock edge.
0x50004048 C   FIELD 02w01 AIN2 (ro): Input 2 state. Input 2 state on the last SCT clock edge.
0x50004048 C   FIELD 03w01 AIN3 (ro): Input 3 state. Input 3 state on the last SCT clock edge.
0x50004048 C   FIELD 16w01 SIN0 (ro): Input 0 state. Input 0 state following the synchronization specified by INSYNC.
0x50004048 C   FIELD 17w01 SIN1 (ro): Input 1 state. Input 1 state following the synchronization specified by INSYNC.
0x50004048 C   FIELD 18w01 SIN2 (ro): Input 2 state. Input 2 state following the synchronization specified by INSYNC.
0x50004048 C   FIELD 19w01 SIN3 (ro): Input 3 state. Input 3 state following the synchronization specified by INSYNC.
0x5000404C B  REGISTER REGMODE (rw): SCT match/capture mode register
0x5000404C C   FIELD 00w05 REGMOD_L (rw): Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match register. 1 = register operates as capture register.
0x5000404C C   FIELD 16w05 REGMOD_H (rw): Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers.
0x50004050 B  REGISTER OUTPUT (rw): SCT output register
0x50004050 C   FIELD 00w04 OUT (rw): Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT.
0x50004054 B  REGISTER OUTPUTDIRCTRL (rw): SCT output counter direction control register
0x50004054 C   FIELD 00w02 SETCLR0 (rw): Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.
0x50004054 C   FIELD 02w02 SETCLR1 (rw): Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.
0x50004054 C   FIELD 04w02 SETCLR2 (rw): Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.
0x50004054 C   FIELD 06w02 SETCLR3 (rw): Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.
0x50004058 B  REGISTER RES (rw): SCT conflict resolution register
0x50004058 C   FIELD 00w02 O0RES (rw): Effect of simultaneous set and clear on output 0.
0x50004058 C   FIELD 02w02 O1RES (rw): Effect of simultaneous set and clear on output 1.
0x50004058 C   FIELD 04w02 O2RES (rw): Effect of simultaneous set and clear on output 2.
0x50004058 C   FIELD 06w02 O3RES (rw): Effect of simultaneous set and clear on output 3.
0x500040F0 B  REGISTER EVEN (rw): SCT event interrupt enable register
0x500040F0 C   FIELD 00w06 IEN (rw): The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0x500040F4 B  REGISTER EVFLAG (rw): SCT event flag register
0x500040F4 C   FIELD 00w06 FLAG (rw): Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0x500040F8 B  REGISTER CONEN (rw): SCT conflict interrupt enable register
0x500040F8 C   FIELD 00w04 NCEN (rw): The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT.
0x500040FC B  REGISTER CONFLAG (rw): SCT conflict flag register
0x500040FC C   FIELD 00w04 NCFLAG (rw): Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT.
0x500040FC C   FIELD 30w01 BUSERRL (rw): The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful.
0x500040FC C   FIELD 31w01 BUSERRH (rw): The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted.
0x50004100 B  REGISTER CAP0 (rw): SCT capture register of capture channel
0x50004100 B  REGISTER MATCH0 (rw): SCT match value register of match channels
0x50004100 C   FIELD 00w16 CAPn_L (rw): When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0x50004100 C   FIELD 00w16 MATCHn_L (rw): When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0x50004100 C   FIELD 16w16 CAPn_H (rw): When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
0x50004100 C   FIELD 16w16 MATCHn_H (rw): When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
0x50004104 B  REGISTER CAP1 (rw): SCT capture register of capture channel
0x50004104 B  REGISTER MATCH1 (rw): SCT match value register of match channels
0x50004104 C   FIELD 00w16 CAPn_L (rw): When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0x50004104 C   FIELD 00w16 MATCHn_L (rw): When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0x50004104 C   FIELD 16w16 CAPn_H (rw): When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
0x50004104 C   FIELD 16w16 MATCHn_H (rw): When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
0x50004108 B  REGISTER CAP2 (rw): SCT capture register of capture channel
0x50004108 B  REGISTER MATCH2 (rw): SCT match value register of match channels
0x50004108 C   FIELD 00w16 CAPn_L (rw): When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0x50004108 C   FIELD 00w16 MATCHn_L (rw): When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0x50004108 C   FIELD 16w16 CAPn_H (rw): When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
0x50004108 C   FIELD 16w16 MATCHn_H (rw): When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
0x5000410C B  REGISTER CAP3 (rw): SCT capture register of capture channel
0x5000410C B  REGISTER MATCH3 (rw): SCT match value register of match channels
0x5000410C C   FIELD 00w16 CAPn_L (rw): When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0x5000410C C   FIELD 00w16 MATCHn_L (rw): When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0x5000410C C   FIELD 16w16 CAPn_H (rw): When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
0x5000410C C   FIELD 16w16 MATCHn_H (rw): When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
0x50004110 B  REGISTER CAP4 (rw): SCT capture register of capture channel
0x50004110 B  REGISTER MATCH4 (rw): SCT match value register of match channels
0x50004110 C   FIELD 00w16 CAPn_L (rw): When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0x50004110 C   FIELD 00w16 MATCHn_L (rw): When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0x50004110 C   FIELD 16w16 CAPn_H (rw): When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
0x50004110 C   FIELD 16w16 MATCHn_H (rw): When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
0x50004200 B  REGISTER CAPCTRL0 (rw): SCT capture control register
0x50004200 B  REGISTER MATCHREL0 (rw): SCT match reload value register
0x50004200 C   FIELD 00w16 CAPCONn_L (rw): If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0x50004200 C   FIELD 00w16 RELOADn_L (rw): When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0x50004200 C   FIELD 16w16 CAPCONn_H (rw): If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
0x50004200 C   FIELD 16w16 RELOADn_H (rw): When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
0x50004204 B  REGISTER CAPCTRL1 (rw): SCT capture control register
0x50004204 B  REGISTER MATCHREL1 (rw): SCT match reload value register
0x50004204 C   FIELD 00w16 CAPCONn_L (rw): If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0x50004204 C   FIELD 00w16 RELOADn_L (rw): When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0x50004204 C   FIELD 16w16 CAPCONn_H (rw): If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
0x50004204 C   FIELD 16w16 RELOADn_H (rw): When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
0x50004208 B  REGISTER CAPCTRL2 (rw): SCT capture control register
0x50004208 B  REGISTER MATCHREL2 (rw): SCT match reload value register
0x50004208 C   FIELD 00w16 CAPCONn_L (rw): If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0x50004208 C   FIELD 00w16 RELOADn_L (rw): When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0x50004208 C   FIELD 16w16 CAPCONn_H (rw): If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
0x50004208 C   FIELD 16w16 RELOADn_H (rw): When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
0x5000420C B  REGISTER CAPCTRL3 (rw): SCT capture control register
0x5000420C B  REGISTER MATCHREL3 (rw): SCT match reload value register
0x5000420C C   FIELD 00w16 CAPCONn_L (rw): If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0x5000420C C   FIELD 00w16 RELOADn_L (rw): When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0x5000420C C   FIELD 16w16 CAPCONn_H (rw): If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
0x5000420C C   FIELD 16w16 RELOADn_H (rw): When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
0x50004210 B  REGISTER CAPCTRL4 (rw): SCT capture control register
0x50004210 B  REGISTER MATCHREL4 (rw): SCT match reload value register
0x50004210 C   FIELD 00w16 CAPCONn_L (rw): If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0x50004210 C   FIELD 00w16 RELOADn_L (rw): When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0x50004210 C   FIELD 16w16 CAPCONn_H (rw): If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
0x50004210 C   FIELD 16w16 RELOADn_H (rw): When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
0x50004300 B  CLUSTER EV[0]: no description available
0x50004300 B  REGISTER EV_STATE0 (rw): SCT event state register 0
0x50004300 C   FIELD 00w01 STATEMSK0 (rw): If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
0x50004300 C   FIELD 01w01 STATEMSK1 (rw): If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
0x50004304 B  REGISTER EV_CTRL0 (rw): SCT event control register 0
0x50004304 C   FIELD 00w04 MATCHSEL (rw): Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0x50004304 C   FIELD 04w01 HEVENT (rw): Select L/H counter. Do not set this bit if UNIFY = 1.
0x50004304 C   FIELD 05w01 OUTSEL (rw): Input/output select
0x50004304 C   FIELD 06w04 IOSEL (rw): Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
0x50004304 C   FIELD 10w02 IOCOND (rw): Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
0x50004304 C   FIELD 12w02 COMBMODE (rw): Selects how the specified match and I/O condition are used and combined.
0x50004304 C   FIELD 14w01 STATELD (rw): This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
0x50004304 C   FIELD 15w05 STATEV (rw): This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
0x50004304 C   FIELD 20w01 MATCHMEM (rw): If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
0x50004304 C   FIELD 21w02 DIRECTION (rw): Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
0x50004308 B  CLUSTER EV[1]: no description available
0x50004308 B  REGISTER EV_STATE1 (rw): SCT event state register 0
0x50004308 C   FIELD 00w01 STATEMSK0 (rw): If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
0x50004308 C   FIELD 01w01 STATEMSK1 (rw): If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
0x5000430C B  REGISTER EV_CTRL1 (rw): SCT event control register 0
0x5000430C C   FIELD 00w04 MATCHSEL (rw): Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0x5000430C C   FIELD 04w01 HEVENT (rw): Select L/H counter. Do not set this bit if UNIFY = 1.
0x5000430C C   FIELD 05w01 OUTSEL (rw): Input/output select
0x5000430C C   FIELD 06w04 IOSEL (rw): Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
0x5000430C C   FIELD 10w02 IOCOND (rw): Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
0x5000430C C   FIELD 12w02 COMBMODE (rw): Selects how the specified match and I/O condition are used and combined.
0x5000430C C   FIELD 14w01 STATELD (rw): This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
0x5000430C C   FIELD 15w05 STATEV (rw): This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
0x5000430C C   FIELD 20w01 MATCHMEM (rw): If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
0x5000430C C   FIELD 21w02 DIRECTION (rw): Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
0x50004310 B  CLUSTER EV[2]: no description available
0x50004310 B  REGISTER EV_STATE2 (rw): SCT event state register 0
0x50004310 C   FIELD 00w01 STATEMSK0 (rw): If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
0x50004310 C   FIELD 01w01 STATEMSK1 (rw): If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
0x50004314 B  REGISTER EV_CTRL2 (rw): SCT event control register 0
0x50004314 C   FIELD 00w04 MATCHSEL (rw): Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0x50004314 C   FIELD 04w01 HEVENT (rw): Select L/H counter. Do not set this bit if UNIFY = 1.
0x50004314 C   FIELD 05w01 OUTSEL (rw): Input/output select
0x50004314 C   FIELD 06w04 IOSEL (rw): Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
0x50004314 C   FIELD 10w02 IOCOND (rw): Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
0x50004314 C   FIELD 12w02 COMBMODE (rw): Selects how the specified match and I/O condition are used and combined.
0x50004314 C   FIELD 14w01 STATELD (rw): This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
0x50004314 C   FIELD 15w05 STATEV (rw): This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
0x50004314 C   FIELD 20w01 MATCHMEM (rw): If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
0x50004314 C   FIELD 21w02 DIRECTION (rw): Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
0x50004318 B  CLUSTER EV[3]: no description available
0x50004318 B  REGISTER EV_STATE3 (rw): SCT event state register 0
0x50004318 C   FIELD 00w01 STATEMSK0 (rw): If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
0x50004318 C   FIELD 01w01 STATEMSK1 (rw): If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
0x5000431C B  REGISTER EV_CTRL3 (rw): SCT event control register 0
0x5000431C C   FIELD 00w04 MATCHSEL (rw): Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0x5000431C C   FIELD 04w01 HEVENT (rw): Select L/H counter. Do not set this bit if UNIFY = 1.
0x5000431C C   FIELD 05w01 OUTSEL (rw): Input/output select
0x5000431C C   FIELD 06w04 IOSEL (rw): Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
0x5000431C C   FIELD 10w02 IOCOND (rw): Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
0x5000431C C   FIELD 12w02 COMBMODE (rw): Selects how the specified match and I/O condition are used and combined.
0x5000431C C   FIELD 14w01 STATELD (rw): This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
0x5000431C C   FIELD 15w05 STATEV (rw): This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
0x5000431C C   FIELD 20w01 MATCHMEM (rw): If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
0x5000431C C   FIELD 21w02 DIRECTION (rw): Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
0x50004320 B  CLUSTER EV[4]: no description available
0x50004320 B  REGISTER EV_STATE4 (rw): SCT event state register 0
0x50004320 C   FIELD 00w01 STATEMSK0 (rw): If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
0x50004320 C   FIELD 01w01 STATEMSK1 (rw): If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
0x50004324 B  REGISTER EV_CTRL4 (rw): SCT event control register 0
0x50004324 C   FIELD 00w04 MATCHSEL (rw): Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0x50004324 C   FIELD 04w01 HEVENT (rw): Select L/H counter. Do not set this bit if UNIFY = 1.
0x50004324 C   FIELD 05w01 OUTSEL (rw): Input/output select
0x50004324 C   FIELD 06w04 IOSEL (rw): Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
0x50004324 C   FIELD 10w02 IOCOND (rw): Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
0x50004324 C   FIELD 12w02 COMBMODE (rw): Selects how the specified match and I/O condition are used and combined.
0x50004324 C   FIELD 14w01 STATELD (rw): This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
0x50004324 C   FIELD 15w05 STATEV (rw): This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
0x50004324 C   FIELD 20w01 MATCHMEM (rw): If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
0x50004324 C   FIELD 21w02 DIRECTION (rw): Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
0x50004328 B  CLUSTER EV[5]: no description available
0x50004328 B  REGISTER EV_STATE5 (rw): SCT event state register 0
0x50004328 C   FIELD 00w01 STATEMSK0 (rw): If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
0x50004328 C   FIELD 01w01 STATEMSK1 (rw): If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
0x5000432C B  REGISTER EV_CTRL5 (rw): SCT event control register 0
0x5000432C C   FIELD 00w04 MATCHSEL (rw): Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0x5000432C C   FIELD 04w01 HEVENT (rw): Select L/H counter. Do not set this bit if UNIFY = 1.
0x5000432C C   FIELD 05w01 OUTSEL (rw): Input/output select
0x5000432C C   FIELD 06w04 IOSEL (rw): Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
0x5000432C C   FIELD 10w02 IOCOND (rw): Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
0x5000432C C   FIELD 12w02 COMBMODE (rw): Selects how the specified match and I/O condition are used and combined.
0x5000432C C   FIELD 14w01 STATELD (rw): This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
0x5000432C C   FIELD 15w05 STATEV (rw): This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
0x5000432C C   FIELD 20w01 MATCHMEM (rw): If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
0x5000432C C   FIELD 21w02 DIRECTION (rw): Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
0x50004500 B  CLUSTER OUT[0]: no description available
0x50004500 B  REGISTER OUT_SET0 (rw): SCT output 0 set register
0x50004500 C   FIELD 00w06 SET (rw): A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
0x50004504 B  REGISTER OUT_CLR0 (rw): SCT output 0 clear register
0x50004504 C   FIELD 00w06 CLR (rw): A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
0x50004508 B  CLUSTER OUT[1]: no description available
0x50004508 B  REGISTER OUT_SET1 (rw): SCT output 0 set register
0x50004508 C   FIELD 00w06 SET (rw): A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
0x5000450C B  REGISTER OUT_CLR1 (rw): SCT output 0 clear register
0x5000450C C   FIELD 00w06 CLR (rw): A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
0x50004510 B  CLUSTER OUT[2]: no description available
0x50004510 B  REGISTER OUT_SET2 (rw): SCT output 0 set register
0x50004510 C   FIELD 00w06 SET (rw): A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
0x50004514 B  REGISTER OUT_CLR2 (rw): SCT output 0 clear register
0x50004514 C   FIELD 00w06 CLR (rw): A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
0x50004518 B  CLUSTER OUT[3]: no description available
0x50004518 B  REGISTER OUT_SET3 (rw): SCT output 0 set register
0x50004518 C   FIELD 00w06 SET (rw): A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
0x5000451C B  REGISTER OUT_CLR3 (rw): SCT output 0 clear register
0x5000451C C   FIELD 00w06 CLR (rw): A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
0xA0000000 A PERIPHERAL GPIO
0xA0000000 B  REGISTER B0_0 (rw): Byte pin registers for all port 0 and 1 GPIO pins
0xA0000000 C   FIELD 00w01 PBYTE (rw): Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0000001 B  REGISTER B0_1 (rw): Byte pin registers for all port 0 and 1 GPIO pins
0xA0000001 C   FIELD 00w01 PBYTE (rw): Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0000002 B  REGISTER B0_2 (rw): Byte pin registers for all port 0 and 1 GPIO pins
0xA0000002 C   FIELD 00w01 PBYTE (rw): Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0000003 B  REGISTER B0_3 (rw): Byte pin registers for all port 0 and 1 GPIO pins
0xA0000003 C   FIELD 00w01 PBYTE (rw): Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0000004 B  REGISTER B0_4 (rw): Byte pin registers for all port 0 and 1 GPIO pins
0xA0000004 C   FIELD 00w01 PBYTE (rw): Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0000005 B  REGISTER B0_5 (rw): Byte pin registers for all port 0 and 1 GPIO pins
0xA0000005 C   FIELD 00w01 PBYTE (rw): Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0000006 B  REGISTER B0_6 (rw): Byte pin registers for all port 0 and 1 GPIO pins
0xA0000006 C   FIELD 00w01 PBYTE (rw): Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0000007 B  REGISTER B0_7 (rw): Byte pin registers for all port 0 and 1 GPIO pins
0xA0000007 C   FIELD 00w01 PBYTE (rw): Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0000008 B  REGISTER B0_8 (rw): Byte pin registers for all port 0 and 1 GPIO pins
0xA0000008 C   FIELD 00w01 PBYTE (rw): Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0000009 B  REGISTER B0_9 (rw): Byte pin registers for all port 0 and 1 GPIO pins
0xA0000009 C   FIELD 00w01 PBYTE (rw): Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA000000A B  REGISTER B0_10 (rw): Byte pin registers for all port 0 and 1 GPIO pins
0xA000000A C   FIELD 00w01 PBYTE (rw): Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA000000B B  REGISTER B0_11 (rw): Byte pin registers for all port 0 and 1 GPIO pins
0xA000000B C   FIELD 00w01 PBYTE (rw): Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA000000C B  REGISTER B0_12 (rw): Byte pin registers for all port 0 and 1 GPIO pins
0xA000000C C   FIELD 00w01 PBYTE (rw): Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA000000D B  REGISTER B0_13 (rw): Byte pin registers for all port 0 and 1 GPIO pins
0xA000000D C   FIELD 00w01 PBYTE (rw): Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA000000E B  REGISTER B0_14 (rw): Byte pin registers for all port 0 and 1 GPIO pins
0xA000000E C   FIELD 00w01 PBYTE (rw): Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA000000F B  REGISTER B0_15 (rw): Byte pin registers for all port 0 and 1 GPIO pins
0xA000000F C   FIELD 00w01 PBYTE (rw): Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0000010 B  REGISTER B0_16 (rw): Byte pin registers for all port 0 and 1 GPIO pins
0xA0000010 C   FIELD 00w01 PBYTE (rw): Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0000011 B  REGISTER B0_17 (rw): Byte pin registers for all port 0 and 1 GPIO pins
0xA0000011 C   FIELD 00w01 PBYTE (rw): Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0001000 B  REGISTER W0_0 (rw): Word pin registers for all port 0 and 1 GPIO pins
0xA0001000 C   FIELD 00w32 PWORD (rw): Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0001004 B  REGISTER W0_1 (rw): Word pin registers for all port 0 and 1 GPIO pins
0xA0001004 C   FIELD 00w32 PWORD (rw): Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0001008 B  REGISTER W0_2 (rw): Word pin registers for all port 0 and 1 GPIO pins
0xA0001008 C   FIELD 00w32 PWORD (rw): Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA000100C B  REGISTER W0_3 (rw): Word pin registers for all port 0 and 1 GPIO pins
0xA000100C C   FIELD 00w32 PWORD (rw): Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0001010 B  REGISTER W0_4 (rw): Word pin registers for all port 0 and 1 GPIO pins
0xA0001010 C   FIELD 00w32 PWORD (rw): Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0001014 B  REGISTER W0_5 (rw): Word pin registers for all port 0 and 1 GPIO pins
0xA0001014 C   FIELD 00w32 PWORD (rw): Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0001018 B  REGISTER W0_6 (rw): Word pin registers for all port 0 and 1 GPIO pins
0xA0001018 C   FIELD 00w32 PWORD (rw): Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA000101C B  REGISTER W0_7 (rw): Word pin registers for all port 0 and 1 GPIO pins
0xA000101C C   FIELD 00w32 PWORD (rw): Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0001020 B  REGISTER W0_8 (rw): Word pin registers for all port 0 and 1 GPIO pins
0xA0001020 C   FIELD 00w32 PWORD (rw): Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0001024 B  REGISTER W0_9 (rw): Word pin registers for all port 0 and 1 GPIO pins
0xA0001024 C   FIELD 00w32 PWORD (rw): Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0001028 B  REGISTER W0_10 (rw): Word pin registers for all port 0 and 1 GPIO pins
0xA0001028 C   FIELD 00w32 PWORD (rw): Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA000102C B  REGISTER W0_11 (rw): Word pin registers for all port 0 and 1 GPIO pins
0xA000102C C   FIELD 00w32 PWORD (rw): Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0001030 B  REGISTER W0_12 (rw): Word pin registers for all port 0 and 1 GPIO pins
0xA0001030 C   FIELD 00w32 PWORD (rw): Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0001034 B  REGISTER W0_13 (rw): Word pin registers for all port 0 and 1 GPIO pins
0xA0001034 C   FIELD 00w32 PWORD (rw): Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0001038 B  REGISTER W0_14 (rw): Word pin registers for all port 0 and 1 GPIO pins
0xA0001038 C   FIELD 00w32 PWORD (rw): Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA000103C B  REGISTER W0_15 (rw): Word pin registers for all port 0 and 1 GPIO pins
0xA000103C C   FIELD 00w32 PWORD (rw): Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0001040 B  REGISTER W0_16 (rw): Word pin registers for all port 0 and 1 GPIO pins
0xA0001040 C   FIELD 00w32 PWORD (rw): Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0001044 B  REGISTER W0_17 (rw): Word pin registers for all port 0 and 1 GPIO pins
0xA0001044 C   FIELD 00w32 PWORD (rw): Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0xA0002000 B  REGISTER DIR0 (rw): Direction registers
0xA0002000 C   FIELD 00w18 DIRP (rw): Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output.
0xA0002080 B  REGISTER MASK0 (rw): Mask register
0xA0002080 C   FIELD 00w18 MASKP (rw): Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.
0xA0002100 B  REGISTER PIN0 (rw): Port pin register
0xA0002100 C   FIELD 00w18 PORT (rw): Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.
0xA0002180 B  REGISTER MPIN0 (rw): Masked port register
0xA0002180 C   FIELD 00w18 MPORTP (rw): Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.
0xA0002200 B  REGISTER SET0 (rw): Write: Set register for port Read: output bits for port
0xA0002200 C   FIELD 00w18 SETP (rw): Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.
0xA0002280 B  REGISTER CLR0 (wo): Clear port
0xA0002280 C   FIELD 00w18 CLRP (wo): Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit.
0xA0002300 B  REGISTER NOT0 (wo): Toggle port
0xA0002300 C   FIELD 00w18 NOTP (wo): Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit.
0xA0004000 A PERIPHERAL PINT
0xA0004000 B  REGISTER ISEL (rw): Pin Interrupt Mode register
0xA0004000 C   FIELD 00w08 PMODE (rw): Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive
0xA0004004 B  REGISTER IENR (rw): Pin interrupt level or rising edge interrupt enable register
0xA0004004 C   FIELD 00w08 ENRL (rw): Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.
0xA0004008 B  REGISTER SIENR (wo): Pin interrupt level or rising edge interrupt set register
0xA0004008 C   FIELD 00w08 SETENRL (wo): Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.
0xA000400C B  REGISTER CIENR (wo): Pin interrupt level (rising edge interrupt) clear register
0xA000400C C   FIELD 00w08 CENRL (wo): Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.
0xA0004010 B  REGISTER IENF (rw): Pin interrupt active level or falling edge interrupt enable register
0xA0004010 C   FIELD 00w08 ENAF (rw): Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.
0xA0004014 B  REGISTER SIENF (wo): Pin interrupt active level or falling edge interrupt set register
0xA0004014 C   FIELD 00w08 SETENAF (wo): Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.
0xA0004018 B  REGISTER CIENF (wo): Pin interrupt active level or falling edge interrupt clear register
0xA0004018 C   FIELD 00w08 CENAF (wo): Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.
0xA000401C B  REGISTER RISE (rw): Pin interrupt rising edge register
0xA000401C C   FIELD 00w08 RDET (rw): Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.
0xA0004020 B  REGISTER FALL (rw): Pin interrupt falling edge register
0xA0004020 C   FIELD 00w08 FDET (rw): Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.
0xA0004024 B  REGISTER IST (rw): Pin interrupt status register
0xA0004024 C   FIELD 00w08 PSTAT (rw): Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).
0xA0004028 B  REGISTER PMCTRL (rw): Pattern match interrupt control register
0xA0004028 C   FIELD 00w01 SEL_PMATCH (rw): Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.
0xA0004028 C   FIELD 01w01 ENA_RXEV (rw): Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true.
0xA0004028 C   FIELD 24w08 PMAT (rw): This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs.
0xA000402C B  REGISTER PMSRC (rw): Pattern match interrupt bit-slice source register
0xA000402C C   FIELD 08w03 SRC0 (rw): Selects the input source for bit slice 0
0xA000402C C   FIELD 11w03 SRC1 (rw): Selects the input source for bit slice 1
0xA000402C C   FIELD 14w03 SRC2 (rw): Selects the input source for bit slice 2
0xA000402C C   FIELD 17w03 SRC3 (rw): Selects the input source for bit slice 3
0xA000402C C   FIELD 20w03 SRC4 (rw): Selects the input source for bit slice 4
0xA000402C C   FIELD 23w03 SRC5 (rw): Selects the input source for bit slice 5
0xA000402C C   FIELD 26w03 SRC6 (rw): Selects the input source for bit slice 6
0xA000402C C   FIELD 29w03 SRC7 (rw): Selects the input source for bit slice 7
0xA0004030 B  REGISTER PMCFG (rw): Pattern match interrupt bit slice configuration register
0xA0004030 C   FIELD 00w01 PROD_ENDPTS0 (rw): Determines whether slice 0 is an endpoint.
0xA0004030 C   FIELD 01w01 PROD_ENDPTS1 (rw): Determines whether slice 1 is an endpoint.
0xA0004030 C   FIELD 02w01 PROD_ENDPTS2 (rw): Determines whether slice 2 is an endpoint.
0xA0004030 C   FIELD 03w01 PROD_ENDPTS3 (rw): Determines whether slice 3 is an endpoint.
0xA0004030 C   FIELD 04w01 PROD_ENDPTS4 (rw): Determines whether slice 4 is an endpoint.
0xA0004030 C   FIELD 05w01 PROD_ENDPTS5 (rw): Determines whether slice 5 is an endpoint.
0xA0004030 C   FIELD 06w01 PROD_ENDPTS6 (rw): Determines whether slice 6 is an endpoint.
0xA0004030 C   FIELD 08w03 CFG0 (rw): Specifies the match contribution condition for bit slice 0.
0xA0004030 C   FIELD 11w03 CFG1 (rw): Specifies the match contribution condition for bit slice 1.
0xA0004030 C   FIELD 14w03 CFG2 (rw): Specifies the match contribution condition for bit slice 2.
0xA0004030 C   FIELD 17w03 CFG3 (rw): Specifies the match contribution condition for bit slice 3.
0xA0004030 C   FIELD 20w03 CFG4 (rw): Specifies the match contribution condition for bit slice 4.
0xA0004030 C   FIELD 23w03 CFG5 (rw): Specifies the match contribution condition for bit slice 5.
0xA0004030 C   FIELD 26w03 CFG6 (rw): Specifies the match contribution condition for bit slice 6.
0xA0004030 C   FIELD 29w03 CFG7 (rw): Specifies the match contribution condition for bit slice 7.
INTERRUPT 000: SPI0 (SPI0): 
INTERRUPT 001: SPI1 (SPI1): 
INTERRUPT 003: USART0 (USART0): 
INTERRUPT 004: USART1 (USART1): 
INTERRUPT 005: USART2 (USART2): 
INTERRUPT 008: I2C0 (I2C0): 
INTERRUPT 009: SCT0 (SCT0): 
INTERRUPT 012: WDT (WWDT): 
INTERRUPT 015: WKT (WKT): 
INTERRUPT 024: PIN_INT0 (PINT): 
INTERRUPT 025: PIN_INT1 (PINT): 
INTERRUPT 026: PIN_INT2 (PINT): 
INTERRUPT 027: PIN_INT3 (PINT): 
INTERRUPT 028: PIN_INT4 (PINT): 
INTERRUPT 029: PIN_INT5 (PINT): 
INTERRUPT 030: PIN_INT6 (PINT): 
INTERRUPT 031: PIN_INT7 (PINT):