SID_PLAYER_cmsis_svd.xml

<?xml version="1.0" encoding="ISO-8859-1" ?>
<device>
  <name>SID_PLAYER</name>
  <version>1.0</version>
  <description>CMSIS description for SID_PLAYER.  Created by Microsemi SmartDesign on Sat Aug 21 21:45:04 2021</description>
  <addressUnitBits>8</addressUnitBits>
  <width>32</width>
  <peripherals>
    <peripheral>
      <name>DDR_0_SPACE_3</name>
      <baseAddress>0xD0000000</baseAddress>
    </peripheral>
    <peripheral>
      <name>DDR_0_SPACE_2</name>
      <baseAddress>0xC0000000</baseAddress>
    </peripheral>
    <peripheral>
      <name>DDR_0_SPACE_1</name>
      <baseAddress>0xB0000000</baseAddress>
    </peripheral>
    <peripheral>
      <name>DDR_0_SPACE_0</name>
      <baseAddress>0xA0000000</baseAddress>
    </peripheral>
    <peripheral>
      <name>AHB2ENVM1_REGISTERS</name>
      <baseAddress>0x600C0000</baseAddress>
    </peripheral>
    <peripheral>
      <name>AHB2ENVM0_REGISTERS</name>
      <baseAddress>0x60080000</baseAddress>
    </peripheral>
    <peripheral>
      <name>ENTIRE_ENVM</name>
      <baseAddress>0x60000000</baseAddress>
    </peripheral>
    <peripheral>
      <name>ENVM-PROGRAM</name>
      <baseAddress>0x60000000</baseAddress>
    </peripheral>
    <peripheral>
      <name>CORESDR_AHB_C1_0</name>
      <baseAddress>0x50000000%0x30000000</baseAddress>
    </peripheral>
    <peripheral>
      <name>SID_BRIDGE_0</name>
      <baseAddress>0x51000000%0x31000000</baseAddress>
    </peripheral>
    <peripheral>
      <name>CACHE_BACKDOOR</name>
      <baseAddress>0x40400000</baseAddress>
    </peripheral>
    <peripheral>
      <name>SYSREG</name>
      <baseAddress>0x40038000</baseAddress>
      <memoryMap>
        <name>RegisterMap</name>
        <addressBlock>
          <baseAddress>0x0</baseAddress>
          <range format="long">0x1000</range>
          <width format="long" id="width">32</width>
          <register>
            <name>ESRAM_CR</name>
            <addressOffset>0x0</addressOffset>
            <absoluteAddress>0x40038000</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>SW_CC_ERSAM1FWREMAP</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SW_CC_ESRAMFWREMAP</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>ESRAM_MAX_LAT</name>
            <addressOffset>0x4</addressOffset>
            <absoluteAddress>0x40038004</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>SW_MAX_LAT_ESRAM1</name>
              <bitNumber>5:3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SW_MAX_LAT_ESRAM0</name>
              <bitNumber>2:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>DDR_CR</name>
            <addressOffset>0x8</addressOffset>
            <absoluteAddress>0x40038008</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>SW_CC_DDRFWREMAP</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>ENVM_CR</name>
            <addressOffset>0xC</addressOffset>
            <absoluteAddress>0x4003800C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>ENVM_SENSE_ON</name>
              <bitNumber>16</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ENVM_PERSIST</name>
              <bitNumber>15</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>NV_DPD1</name>
              <bitNumber>14</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>NV_DPD0</name>
              <bitNumber>13</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>NV_FREQRNG</name>
              <bitNumber>7:5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SW_ENVMREMAPSIZE</name>
              <bitNumber>4:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>ENVM_REMAP_BASE_CR</name>
            <addressOffset>0x10</addressOffset>
            <absoluteAddress>0x40038010</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>SW_ENVMREMAPBASE</name>
              <bitNumber>18:1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SW_ENVMREMAPENABLE</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>ENVM_REMAP_FAB_CR</name>
            <addressOffset>0x14</addressOffset>
            <absoluteAddress>0x40038014</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>SW_ENVMFABREMAPBASE</name>
              <bitNumber>18:1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SW_ENVMFABREMAPENABLE</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>CC_CR</name>
            <addressOffset>0x18</addressOffset>
            <absoluteAddress>0x40038018</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CC_CACHE_LOCK</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CC_SBUS_WR_MODE</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CC_CACHE_ENB</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>CC_REGION_CR</name>
            <addressOffset>0x1C</addressOffset>
            <absoluteAddress>0x4003801C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CC_CACHE_REGION</name>
              <bitNumber>3:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>CC_LOCK_BASE_ADDR_CR</name>
            <addressOffset>0x20</addressOffset>
            <absoluteAddress>0x40038020</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CC_LOCK_BASEADD</name>
              <bitNumber>18:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>CC_FLUSH_INDX_CR</name>
            <addressOffset>0x24</addressOffset>
            <absoluteAddress>0x40038024</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CC_FLUSH_INDEX</name>
              <bitNumber>5:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>DDRB_BUF_TIMER_CR</name>
            <addressOffset>0x28</addressOffset>
            <absoluteAddress>0x40038028</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>DDRB_TIMER</name>
              <bitNumber>9:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>DDRB_NB_ADDR_CR</name>
            <addressOffset>0x2C</addressOffset>
            <absoluteAddress>0x4003802C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>DDRB_NB_ADDR</name>
              <bitNumber>15:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>DDRB_NB_SIZE_CR</name>
            <addressOffset>0x30</addressOffset>
            <absoluteAddress>0x40038030</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>DDRB_NB_SZ</name>
              <bitNumber>3:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>DDRB_CR</name>
            <addressOffset>0x34</addressOffset>
            <absoluteAddress>0x40038034</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>DDR_IDC_MAP</name>
              <bitNumber>23:20</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDR_SW_MAP</name>
              <bitNumber>19:16</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDR_HPD_MAP</name>
              <bitNumber>15:12</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDR_DS_MAP</name>
              <bitNumber>11:8</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDR_BUF_SZ</name>
              <bitNumber>7</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_IDC_EN</name>
              <bitNumber>6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_SW_REN</name>
              <bitNumber>5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_SW_WEN</name>
              <bitNumber>4</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_HPD_REN</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_HPD_WEN</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_DS_REN</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_DS_WEN</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>EDAC_CR</name>
            <addressOffset>0x38</addressOffset>
            <absoluteAddress>0x40038038</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CAN_EDAC_EN</name>
              <bitNumber>6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>USB_EDAC_EN</name>
              <bitNumber>5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MAC_EDAC_RX_EN</name>
              <bitNumber>4</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MAC_EDAC_TX_EN</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM1_EDAC_EN</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM0_EDAC_EN</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MASTER_WEIGHT0_CR</name>
            <addressOffset>0x3C</addressOffset>
            <absoluteAddress>0x4003803C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>SW_WEIGHT_PDMA</name>
              <bitNumber>29:25</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SW_WEIGHT_FAB_1</name>
              <bitNumber>24:20</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SW_WEIGHT_FAB_0</name>
              <bitNumber>19:15</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SW_WEIGHT_GIGE</name>
              <bitNumber>14:10</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SW_WEIGHT_S</name>
              <bitNumber>9:5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SW_WEIGHT_IC</name>
              <bitNumber>4:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MASTER_WEIGHT1_CR</name>
            <addressOffset>0x40</addressOffset>
            <absoluteAddress>0x40038040</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>SW_WEIGHT_G</name>
              <bitNumber>14:10</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SW_WEIGHT_USB</name>
              <bitNumber>9:5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SW_WEIGHT_HPMDA</name>
              <bitNumber>4:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>SOFT_IRQ_CR</name>
            <addressOffset>0x44</addressOffset>
            <absoluteAddress>0x40038044</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>SOFTINTERRUPT</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>SOFT_RESET_CR</name>
            <addressOffset>0x48</addressOffset>
            <absoluteAddress>0x40038048</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>MDDR_DDRFIC_SOFTRESET</name>
              <bitNumber>26</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MDDR_CTLR_SOFTRESET</name>
              <bitNumber>25</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MSS_GPOUT_31_24_SOFTRESET</name>
              <bitNumber>24</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MSS_GPOUT_23_16_SOFTRESET</name>
              <bitNumber>23</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MSS_GPOUT_15_8_SOFTRESET</name>
              <bitNumber>22</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MSS_GPOUT_7_0_SOFTRESET</name>
              <bitNumber>21</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MSS_GPIO_SOFTRESET</name>
              <bitNumber>20</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FIC_1_SOFTRESET</name>
              <bitNumber>19</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FIC_0_SOFTRESET</name>
              <bitNumber>18</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>HPDMA_SOFTRESET</name>
              <bitNumber>17</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FPGA_SOFTRESET</name>
              <bitNumber>16</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>COMBLK_SOFTRESET</name>
              <bitNumber>15</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>USB_SOFTRESET</name>
              <bitNumber>14</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CAN_SOFTRESET</name>
              <bitNumber>13</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>I2C1_SOFTRESET</name>
              <bitNumber>12</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>I2C0_SOFTRESET</name>
              <bitNumber>11</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SPI1_SOFTRESET</name>
              <bitNumber>10</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SPI0_SOFTRESET</name>
              <bitNumber>9</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MMUART1_SOFTRESET</name>
              <bitNumber>8</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MMUART0_SOFTRESET</name>
              <bitNumber>7</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>TIMER_SOFTRESET</name>
              <bitNumber>6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>PDMA_SOFTRESET</name>
              <bitNumber>5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MAC_SOFTRESET</name>
              <bitNumber>4</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM1_SOFTRESET</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM0_SOFTRESET</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ENVM1_SOFTRESET</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ENVM0_SOFTRESET</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>M3_CR</name>
            <addressOffset>0x4C</addressOffset>
            <absoluteAddress>0x4003804C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>M3_MPU_DISABLE</name>
              <bitNumber>28</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>STCLK_DIVISOR</name>
              <bitNumber>27:26</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>STCALIB</name>
              <bitNumber>25:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>FAB_IF_CR</name>
            <addressOffset>0x50</addressOffset>
            <absoluteAddress>0x40038050</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>SW_FIC_REG_SEL</name>
              <bitNumber>9:4</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FAB1_AHB_MODE</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FAB0_AHB_MODE</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FAB1_AHB_BYPASS</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FAB0_AHB_BYPASS</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>LOOPBACK_CR</name>
            <addressOffset>0x54</addressOffset>
            <absoluteAddress>0x40038054</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>MSS_GPIOLOOPBACK</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MSS_I2CLOOPBACK</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MSS_SPILOOPBACK</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MSS_MMUARTLOOPBACK</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>GPIO_SYSRESET_SEL_CR</name>
            <addressOffset>0x58</addressOffset>
            <absoluteAddress>0x40038058</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>MSS_GPIO_31_24_SYSRESET_SEL</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MSS_GPIO_23_16_SYSRESET_SEL</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MSS_GPIO_15_8_SYSRESET_SEL</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MSS_GPIO_7_0_SYSRESET_SEL</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>GPIN_SRC_SEL_CR</name>
            <addressOffset>0x5C</addressOffset>
            <absoluteAddress>0x4003805C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>MSS_GPINSOURCE</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MDDR_CR</name>
            <addressOffset>0x60</addressOffset>
            <absoluteAddress>0x40038060</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>PHY_SELF_REF_EN</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>F_AXI_AHB_MODE</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SDR_MODE</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MDDR_CONFIG_LOCAL</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>USB_IO_INPUT_SEL_CR</name>
            <addressOffset>0x64</addressOffset>
            <absoluteAddress>0x40038064</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>USB_IO_INPUT_SEL</name>
              <bitNumber>1:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>PERIPH_CLK_MUX_SEL_CR</name>
            <addressOffset>0x68</addressOffset>
            <absoluteAddress>0x40038068</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>TRACECLK_DIV2_SEL</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SPI1_SCK_FAB_SEL</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SPI0_SCK_FAB_SEL</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>WDOG_CR</name>
            <addressOffset>0x6C</addressOffset>
            <absoluteAddress>0x4003806C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>WDOGMODE</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>WDOGENABLE</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MDDR_IO_CALIB_CR</name>
            <addressOffset>0x70</addressOffset>
            <absoluteAddress>0x40038070</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CALIB_LOCK</name>
              <bitNumber>14</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CALIB_START</name>
              <bitNumber>13</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CALIB_TRIM</name>
              <bitNumber>12</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>NCODE</name>
              <bitNumber>11:6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>PCODE</name>
              <bitNumber>5:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>RESERVED</name>
            <addressOffset>0x74</addressOffset>
            <absoluteAddress>0x40038074</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
          </register>
          <register>
            <name>EDAC_IRQ_ENABLE_CR</name>
            <addressOffset>0x78</addressOffset>
            <absoluteAddress>0x40038078</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>MDDR_ECC_INT_EN</name>
              <bitNumber>14</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CAN_EDAC_2E_EN</name>
              <bitNumber>13</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CAN_EDAC_1E_EN</name>
              <bitNumber>12</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>USB_EDAC_2E_EN</name>
              <bitNumber>11</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>USB_EDAC_1E_EN</name>
              <bitNumber>10</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MAC_EDAC_RX_2E_EN</name>
              <bitNumber>9</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MAC_EDAC_RX_1E_EN</name>
              <bitNumber>8</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MAC_EDAC_TX_2E_EN</name>
              <bitNumber>7</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MAC_EDAC_TX_1E_EN</name>
              <bitNumber>6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM1_EDAC_2E_EN</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM1_EDAC_1E_EN</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM0_EDAC_2E_EN</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM0_EDAC_1E_EN</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>USB_CR</name>
            <addressOffset>0x7C</addressOffset>
            <absoluteAddress>0x4003807C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>USB_DDR_SELECT</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>USB_UTMI_SEL</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>ESRAM_PIPELINE_CR</name>
            <addressOffset>0x80</addressOffset>
            <absoluteAddress>0x40038080</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>ESRAM_PIPELINE_ENABLE</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MSS_IRQ_ENABLE_CR</name>
            <addressOffset>0x84</addressOffset>
            <absoluteAddress>0x40038084</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>DDRB_INTERRUPT_EN</name>
              <bitNumber>19:10</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CC_INTERRUPT_EN</name>
              <bitNumber>9:7</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SW_INTERRUPT_EN</name>
              <bitNumber>6:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>RTC_WAKEUP_CR</name>
            <addressOffset>0x88</addressOffset>
            <absoluteAddress>0x40038088</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>RTC_WAKEUP_C_EN</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>RTC_WAKEUP_FAB_EN</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>RTC_WAKEUP_M3_EN</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MAC_CR</name>
            <addressOffset>0x8C</addressOffset>
            <absoluteAddress>0x4003808C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>RGMII_TXC_DELAY_SEL</name>
              <bitNumber>8:5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ETH_PHY_MODE</name>
              <bitNumber>3:2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ETH_LINE_SPEED</name>
              <bitNumber>1:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MSSDDR_PLL_STATUS_LOW_CR</name>
            <addressOffset>0x90</addressOffset>
            <absoluteAddress>0x40038090</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>FACC_PLL_LOCKCNT</name>
              <bitNumber>29:26</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FACC_PLL_LOCKWIN</name>
              <bitNumber>25:23</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FACC_PLL_RANGE</name>
              <bitNumber>22:19</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FACC_PLL_DIVQ</name>
              <bitNumber>19:16</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FACC_PLL_DIVF</name>
              <bitNumber>15:6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FACC_PLL_DIVR</name>
              <bitNumber>5:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MSSDDR_PLL_STATUS_HIGH_CR</name>
            <addressOffset>0x94</addressOffset>
            <absoluteAddress>0x40038094</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>FACC_PLL_SSMF</name>
              <bitNumber>12:8</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FACC_PLL_SSMD</name>
              <bitNumber>7:6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FACC_PLL_SSE</name>
              <bitNumber>5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FACC_PLL_PD</name>
              <bitNumber>4</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FACC_PLL_FSE</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FACC_PLL_MODE_3V3</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FACC_PLL_MODE_1V2</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FACC_PLL_BYPASS</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MSSDDR_FACC1_CR</name>
            <addressOffset>0x98</addressOffset>
            <absoluteAddress>0x40038098</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>FACC_FAB_REF_SEL</name>
              <bitNumber>27</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CONTROLLER_PLLT_INT</name>
              <bitNumber>26</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>PERSIST_CC</name>
              <bitNumber>25</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>BASE_DIVISOR</name>
              <bitNumber>24:22</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDR_FIC_DIVISOR</name>
              <bitNumber>21:19</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FIC_1_DIVISOR</name>
              <bitNumber>18:16</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FIC_0_DIVISOR</name>
              <bitNumber>15:13</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FACC_GLMUX_SEL</name>
              <bitNumber>12</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>M3_CLK_DIVISOR</name>
              <bitNumber>11:9</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDR_CLK_EN</name>
              <bitNumber>8</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>APB1_DIVISOR</name>
              <bitNumber>7:5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>APB0_DIVISOR</name>
              <bitNumber>4:2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DIVISOR_A</name>
              <bitNumber>1:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MSSDDR_FACC2_CR</name>
            <addressOffset>0x9C</addressOffset>
            <absoluteAddress>0x4003809C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>MSS_XTAL_RTC_EN</name>
              <bitNumber>13</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MSS_XTAL_EN</name>
              <bitNumber>12</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MSS_CLK_ENVM_EN</name>
              <bitNumber>11</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MSS_1MHZ_EN</name>
              <bitNumber>10</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MSS_25_50MHZ_EN</name>
              <bitNumber>9</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FACC_STANDBY_SEL</name>
              <bitNumber>8:6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FACC_PRE_SRC_SEL</name>
              <bitNumber>5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FACC_SRC_SEL</name>
              <bitNumber>4:2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>RTC_CLK_SEL</name>
              <bitNumber>1:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>PLL_LOCK_EN_CR</name>
            <addressOffset>0xA0</addressOffset>
            <absoluteAddress>0x400380A0</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>FAB_PLL_LOCK_LOST_EN</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FAB_PLL_LOCK_EN</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MPLL_LOCK_LOST_EN</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MPLL_LOCK_EN</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MSSDDR_CLK_CALIB_CR</name>
            <addressOffset>0xA4</addressOffset>
            <absoluteAddress>0x400380A4</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>FAB_CALIB_START</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>PLL_DELAY_LINE_SEL_CR</name>
            <addressOffset>0xA8</addressOffset>
            <absoluteAddress>0x400380A8</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>PLL_REF_DEL_SEL</name>
              <bitNumber>1:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MAC_STAT_CLRONRD_CR</name>
            <addressOffset>0xAC</addressOffset>
            <absoluteAddress>0x400380AC</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>MAC_STAT_CLRONRD</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>RESET_SOURCE_CR</name>
            <addressOffset>0xB0</addressOffset>
            <absoluteAddress>0x400380B0</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>USER_M3_RESET_DETECT</name>
              <bitNumber>7</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>USER_RESET_DETECT</name>
              <bitNumber>6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>WDOG_RESET_DETECT</name>
              <bitNumber>5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>LOCKUP_RESET_DETECT</name>
              <bitNumber>4</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SOFT_RESET_DETECT</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CONTROLLER_M3_RESET_DETECT</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CONTROLLER_RESET_DETECT</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>P0_RESET_DETECT</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>CC_DC_ERR_ADDR_SR</name>
            <addressOffset>0xB4</addressOffset>
            <absoluteAddress>0x400380B4</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CC_DC_ERR_ADDR</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>CC_IC_ERR_ADDR_SR</name>
            <addressOffset>0xB8</addressOffset>
            <absoluteAddress>0x400380B8</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CC_IC_ERR_ADDR</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>CC_SB_ERR_ADDR_SR</name>
            <addressOffset>0xBC</addressOffset>
            <absoluteAddress>0x400380BC</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CC_SB_ERR_ADDR</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>RESERVED</name>
            <addressOffset>0xC0</addressOffset>
            <absoluteAddress>0x400380C0</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
          </register>
          <register>
            <name>CC_IC_MISS_CNTR_SR</name>
            <addressOffset>0xC4</addressOffset>
            <absoluteAddress>0x400380C4</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CC_IC_MISS_CNT</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>CC_IC_HIT_CNTR_SR</name>
            <addressOffset>0xC8</addressOffset>
            <absoluteAddress>0x400380C8</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CC_IC_HIT_CNT</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>CC_DC_MISS_CNTR_SR</name>
            <addressOffset>0xCC</addressOffset>
            <absoluteAddress>0x400380CC</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CC_DC_MISS_CNT</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>CC_DC_HIT_CNTR_SR</name>
            <addressOffset>0xD0</addressOffset>
            <absoluteAddress>0x400380D0</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CC_DC_HIT_CNT</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>CC_IC_TRANS_CNTR_SR</name>
            <addressOffset>0xD4</addressOffset>
            <absoluteAddress>0x400380D4</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CC_IC_TRANS_CNT</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>CC_DC_TRANS_CNTR_SR</name>
            <addressOffset>0xD8</addressOffset>
            <absoluteAddress>0x400380D8</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CC_DC_TRANS_CNT</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>DDRB_DS_ERR_ADR_SR</name>
            <addressOffset>0xDC</addressOffset>
            <absoluteAddress>0x400380DC</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>DDRB_DS_ERR_ADD</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>DDRB_HPD_ERR_ADR_SR</name>
            <addressOffset>0xE0</addressOffset>
            <absoluteAddress>0x400380E0</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>DDRB_HPD_ERR_ADD</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>DDRB_SW_ERR_ADDR_SR</name>
            <addressOffset>0xE4</addressOffset>
            <absoluteAddress>0x400380E4</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>DDRB_SW_ERR_ADD</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>DDRB_BUF_EMPTY_SR</name>
            <addressOffset>0xE8</addressOffset>
            <absoluteAddress>0x400380E8</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>DDRB_IDC_RBEMPTY</name>
              <bitNumber>6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_HPD_RBEMPTY</name>
              <bitNumber>5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_HPD_WBEMPTY</name>
              <bitNumber>4</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_SW_RBEMPTY</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_SW_EBEMPTY</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_DS_RBEMPTY</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_DS_WBEMPTY</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>DDRB_DSBL_DN_SR</name>
            <addressOffset>0xEC</addressOffset>
            <absoluteAddress>0x400380EC</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>DDRB_IDC_DSBL_DN</name>
              <bitNumber>6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_HPD_RDSBL_DN</name>
              <bitNumber>5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_HPD_WDSBL_DN</name>
              <bitNumber>4</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_SW_RDSBL_DN</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_SW_WDSBL_DN</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_DS_RDSBL_DN</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_DS_WDSBL_DN</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>ESRAM0_EDAC_CNT</name>
            <addressOffset>0xF0</addressOffset>
            <absoluteAddress>0x400380F0</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>ESRAM0_EDAC_CNT_2E</name>
              <bitNumber>31:16</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM0_EDAC_CNT_1E</name>
              <bitNumber>15:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>ERAM1_EDDAC_CNT</name>
            <addressOffset>0xF4</addressOffset>
            <absoluteAddress>0x400380F4</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>ESRAM1_EDAC_CNT_2E</name>
              <bitNumber>31:16</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM1_EDAC_CNT_1E</name>
              <bitNumber>15:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>CC_EDAC_CNT</name>
            <addressOffset>0xF8</addressOffset>
            <absoluteAddress>0x400380F8</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CC_EDAC_CNT_2E</name>
              <bitNumber>31:16</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CC_EDAC_CNT_1E</name>
              <bitNumber>15:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MAC_EDAC_TX_CNT</name>
            <addressOffset>0xFC</addressOffset>
            <absoluteAddress>0x400380FC</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>MAC_EDAC_TX_CNT_2E</name>
              <bitNumber>31:16</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MAC_EDAC_TX_CNT_1E</name>
              <bitNumber>15:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MAC_EDAC_RX_CNT</name>
            <addressOffset>0x100</addressOffset>
            <absoluteAddress>0x40038100</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>MAC_EDAC_RX_CNT_2E</name>
              <bitNumber>31:16</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MAC_EDAC_RX_CNT_1E</name>
              <bitNumber>15:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>USB_EDAC_CNT</name>
            <addressOffset>0x104</addressOffset>
            <absoluteAddress>0x40038104</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>USB_EDAC_CNT_2E</name>
              <bitNumber>31:16</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>USB_EDAC_CNT_1E</name>
              <bitNumber>15:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>CAN_EDAC_CNT</name>
            <addressOffset>0x108</addressOffset>
            <absoluteAddress>0x40038108</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CAN_EDAC_CNT_2E</name>
              <bitNumber>31:16</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CAN_EDAC_CNT_1E</name>
              <bitNumber>15:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>ESRAM0_EDAC_ADR</name>
            <addressOffset>0x10C</addressOffset>
            <absoluteAddress>0x4003810C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>ESRAM0_EDAC_2E_AD</name>
              <bitNumber>25:13</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM0_EDAC_1E_AD</name>
              <bitNumber>12:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>ERSAM1_EDAC_ADR</name>
            <addressOffset>0x110</addressOffset>
            <absoluteAddress>0x40038110</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>ESRAM1_EDAC_2E_AD</name>
              <bitNumber>25:13</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM1_EDAC_1E_AD</name>
              <bitNumber>12:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MAC_EDAC_RX_ADR</name>
            <addressOffset>0x114</addressOffset>
            <absoluteAddress>0x40038114</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>MAC_EDAC_RX_2E_AD</name>
              <bitNumber>25:13</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MAC_EDAC_RX_1E_AD</name>
              <bitNumber>12:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MAC_EDAC_TX_ADR</name>
            <addressOffset>0x118</addressOffset>
            <absoluteAddress>0x40038118</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>MAC_EDAC_TX_2E_AD</name>
              <bitNumber>25:13</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MAC_EDAC_TX_1E_AD</name>
              <bitNumber>12:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>CAN_EDAC_ADR</name>
            <addressOffset>0x11C</addressOffset>
            <absoluteAddress>0x4003811C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CAN_EDAC_2E_AD</name>
              <bitNumber>25:13</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CAN_EDAC_1E_AD</name>
              <bitNumber>12:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>USB_EDAC_ADR</name>
            <addressOffset>0x120</addressOffset>
            <absoluteAddress>0x40038120</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>USB_EDAC_2E_AD</name>
              <bitNumber>25:13</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>USB_EDAC_1E_AD</name>
              <bitNumber>12:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MM0_1_2_SECURITY</name>
            <addressOffset>0x124</addressOffset>
            <absoluteAddress>0x40038124</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>MM0_1_2_MS6_ALLOWED_W</name>
              <bitNumber>9</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM0_1_2_MS6_ALLOWED_R</name>
              <bitNumber>8</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM0_1_2_MS3_ALLOWED_W</name>
              <bitNumber>7</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM0_1_2_MS3_ALLOWED_R</name>
              <bitNumber>6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM0_1_2_MS2_ALLOWED_W</name>
              <bitNumber>5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM0_1_2_MS2_ALLOWED_R</name>
              <bitNumber>4</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM0_1_2_MS1_ALLOWED_W</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM0_1_2_MS1_ALLOWED_R</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM0_1_2_MS0_ALLOWED_W</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM0_1_2_MS0_ALLOWED_R</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MM4_5_DDR_FIC_SECURITY/MM_4_5_FIC64_SECURITY</name>
            <addressOffset>0x128</addressOffset>
            <absoluteAddress>0x40038128</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>MM4_5_DDR_FIC_MS6_ALLOWED_W</name>
              <bitNumber>9</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM4_5_DDR_FIC_MS6_ALLOWED_R</name>
              <bitNumber>8</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM4_5_DDR_FIC_MS3_ALLOWED_W</name>
              <bitNumber>7</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM4_5_DDR_FIC_MS3_ALLOWED_R</name>
              <bitNumber>6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM4_5_DDR_FIC_MS2_ALLOWED_W</name>
              <bitNumber>5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM4_5_DDR_FIC_MS2_ALLOWED_R</name>
              <bitNumber>4</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM4_5_DDR_FIC_MS1_ALLOWED_W</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM4_5_DDR_FIC_MS1_ALLOWED_R</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM4_5_DDR_FIC_MS0_ALLOWED_W</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM4_5_DDR_FIC_MS0_ALLOWED_R</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MM3_6_7_8_SECURITY</name>
            <addressOffset>0x12C</addressOffset>
            <absoluteAddress>0x4003812C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>MM3_6_7_8_MS6_ALLOWED_W</name>
              <bitNumber>9</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM3_6_7_8_MS6_ALLOWED_R</name>
              <bitNumber>8</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM3_6_7_8_MS3_ALLOWED_W</name>
              <bitNumber>7</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM3_6_7_8_MS3_ALLOWED_R</name>
              <bitNumber>6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM3_6_7_8_MS2_ALLOWED_W</name>
              <bitNumber>5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM3_6_7_8_MS2_ALLOWED_R</name>
              <bitNumber>4</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM3_6_7_8_MS1_ALLOWED_W</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM3_6_7_8_MS1_ALLOWED_R</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM3_6_7_8_MS0_ALLOWED_W</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM3_6_7_8_MS0_ALLOWED_R</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MM9_SECURITY</name>
            <addressOffset>0x130</addressOffset>
            <absoluteAddress>0x40038130</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>MM9_MS6_ALLOWED_W</name>
              <bitNumber>9</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM9_MS6_ALLOWED_R</name>
              <bitNumber>8</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM9_MS3_ALLOWED_W</name>
              <bitNumber>7</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM9_MS3_ALLOWED_R</name>
              <bitNumber>6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM9_MS2_ALLOWED_W</name>
              <bitNumber>5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM9_MS2_ALLOWED_R</name>
              <bitNumber>4</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM9_MS1_ALLOWED_W</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM9_MS1_ALLOWED_R</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM9_MS0_ALLOWED_W</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MM9_MS0_ALLOWED_R</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>M3_SR</name>
            <addressOffset>0x134</addressOffset>
            <absoluteAddress>0x40038134</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CURRPRI</name>
              <bitNumber>7:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>ETM_COUNT_LOW</name>
            <addressOffset>0x138</addressOffset>
            <absoluteAddress>0x40038138</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>ETMCOUNT_31_0</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>ETM_COUNT_HIGH</name>
            <addressOffset>0x13C</addressOffset>
            <absoluteAddress>0x4003813C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>ETMINTSTAT</name>
              <bitNumber>27:25</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ETMINTNUM</name>
              <bitNumber>24:16</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ETMCOUNT_47_32</name>
              <bitNumber>15:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>DEVICE_SR</name>
            <addressOffset>0x140</addressOffset>
            <absoluteAddress>0x40038140</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>M3_DEBUG_ENABLE</name>
              <bitNumber>6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>M3_DISABLE</name>
              <bitNumber>5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FLASH_VALID_SYNC</name>
              <bitNumber>4</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>WATCHDOG_FREEZE_SYNC</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FF_IN_PROGRESS_SYNC</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>VIRGIN_PART</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CORE_UP_SYNC</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>ENVM_PROTECT_USER</name>
            <addressOffset>0x144</addressOffset>
            <absoluteAddress>0x40038144</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>NVM1_UPPER_WRITE_ALLOWED</name>
              <bitNumber>15</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>NVM1_UPPER_OTHERS_ACCESS</name>
              <bitNumber>14</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>NVM1_UPPER_FABRIC_ACCESS</name>
              <bitNumber>13</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>NVM1_UPPER_M3ACCESS</name>
              <bitNumber>12</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>NVM1_LOWER_WRITE_ALLOWED</name>
              <bitNumber>11</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>NVM1_LOWER_OTHERS_ACCESS</name>
              <bitNumber>10</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>NVM1_LOWER_FABRIC_ACCESS</name>
              <bitNumber>9</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>NVM1_LOWER_M3ACCESS</name>
              <bitNumber>8</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>NVM0_UPPER_WRITE_ALLOWED</name>
              <bitNumber>7</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>NVM0_UPPER_OTHERS_ACCESS</name>
              <bitNumber>6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>NVM0_UPPER_FABRIC_ACCESS</name>
              <bitNumber>5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>NVM0_UPPER_M3ACCESS</name>
              <bitNumber>4</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>NVM0_LOWER_WRITE_ALLOWED</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>NVM0_LOWER_OTHERS_ACCESS</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>NVM0_LOWER_FABRIC_ACCESS</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>NVM0_LOWER_M3ACCESS</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>ENVM_STATUS</name>
            <addressOffset>0x148</addressOffset>
            <absoluteAddress>0x40038148</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CODE_SHADOW_EN</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>DEVICE_VERSION</name>
            <addressOffset>0x14C</addressOffset>
            <absoluteAddress>0x4003814C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>IDV</name>
              <bitNumber>19:16</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>IDP</name>
              <bitNumber>15:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MSSDDR_PLL_STATUS</name>
            <addressOffset>0x150</addressOffset>
            <absoluteAddress>0x40038150</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>RCOSC_DIV2</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MPLL_LOCK</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FAB_PLL_LOCK</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>USB_SR</name>
            <addressOffset>0x154</addressOffset>
            <absoluteAddress>0x40038154</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>LPI_CARKIT_EN</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>POWERDN</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>ENVM_SR</name>
            <addressOffset>0x158</addressOffset>
            <absoluteAddress>0x40038158</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>ENVM_BUSY</name>
              <bitNumber>1:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>RESERVED</name>
            <addressOffset>0x15C</addressOffset>
            <absoluteAddress>0x4003815C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
          </register>
          <register>
            <name>DDRB_STATUS</name>
            <addressOffset>0x160</addressOffset>
            <absoluteAddress>0x40038160</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>DDRB_DEBUG_STATUS</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MDDR_IO_CALIB_STATUS</name>
            <addressOffset>0x164</addressOffset>
            <absoluteAddress>0x40038164</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CALIB_PCOMP</name>
              <bitNumber>14</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CALIB_NCOMP</name>
              <bitNumber>13</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CALIB_PCODE</name>
              <bitNumber>12:6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CALIB_NCODE</name>
              <bitNumber>5:1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CALIB_STATUS</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MSSDDR_CLK_CALIB_STATUS</name>
            <addressOffset>0x168</addressOffset>
            <absoluteAddress>0x40038168</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>FAB_CALIB_FAIL</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>WDOGLOAD</name>
            <addressOffset>0x16C</addressOffset>
            <absoluteAddress>0x4003816C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>WDOGLOAD</name>
              <bitNumber>25:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>WDOGMVRP</name>
            <addressOffset>0x170</addressOffset>
            <absoluteAddress>0x40038170</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>WDOGMVRP</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>USERCONFIG0</name>
            <addressOffset>0x174</addressOffset>
            <absoluteAddress>0x40038174</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CONFIG_REG0</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>USERCONFIG1</name>
            <addressOffset>0x178</addressOffset>
            <absoluteAddress>0x40038178</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CONFIG_REG1</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>USERCONFIG2</name>
            <addressOffset>0x17C</addressOffset>
            <absoluteAddress>0x4003817C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CONFIG_REG2</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>USERCONFIG3</name>
            <addressOffset>0x180</addressOffset>
            <absoluteAddress>0x40038180</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CONFIG_REG4</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>FAB_PROT_SIZE</name>
            <addressOffset>0x184</addressOffset>
            <absoluteAddress>0x40038184</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>SW_PROTREGIONSIZE</name>
              <bitNumber>5:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>FAB_PROT_BASE</name>
            <addressOffset>0x188</addressOffset>
            <absoluteAddress>0x40038188</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>SW_PROTREGIONBASE</name>
              <bitNumber>31:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MSS_GPIO_DEF</name>
            <addressOffset>0x18C</addressOffset>
            <absoluteAddress>0x4003818C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>MSS_GPIO_31_24_DEF</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MSS_GPIO_23_16_DEF</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MSS_GPIO_15_8_DEF</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MSS_GPIO_7_0_DEF</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>EDAC_SR</name>
            <addressOffset>0x190</addressOffset>
            <absoluteAddress>0x40038190</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CAN_EDAC_2E</name>
              <bitNumber>13</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CAN_EDAC_1E</name>
              <bitNumber>12</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>USB_EDAC_2E</name>
              <bitNumber>11</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>USB_EDAC_1E</name>
              <bitNumber>10</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MAC_EDAC_RX_2E</name>
              <bitNumber>9</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MAC_EDAC_RX_1E</name>
              <bitNumber>8</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MAC_EDAC_TX_2E</name>
              <bitNumber>7</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MAC_EDAC_TX_1E</name>
              <bitNumber>6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM1_EDAC_2E</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM1_EDAC_1E</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM0_EDAC_2E</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM0_EDAC_1E</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MSS_INTERNAL_SR</name>
            <addressOffset>0x194</addressOffset>
            <absoluteAddress>0x40038194</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>DDR_FIC_INT</name>
              <bitNumber>6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MDDR_ECC_INT</name>
              <bitNumber>5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MDDR_IO_CALIB_INT</name>
              <bitNumber>4</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FAB_PLL_LOCKLOST_INT</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>FAB_PLL_LOCK_INT</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MPLL_LOCKLOST_INT</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MPLL_LOCK_INT</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MSS_EXTERNAL_SR</name>
            <addressOffset>0x198</addressOffset>
            <absoluteAddress>0x40038198</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CC_HRESP_ERR</name>
              <bitNumber>18</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_LOCK_MID</name>
              <bitNumber>17</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_LCKOUT</name>
              <bitNumber>16</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_HPD_WR_ERR</name>
              <bitNumber>15</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_SW_WR_ERR</name>
              <bitNumber>14</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_DS_WR_ERR</name>
              <bitNumber>13</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_RDWR_ERR_REG</name>
              <bitNumber>12:7</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>SW_ERRORSTATUS</name>
              <bitNumber>6:0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>WDOGTIMEOUTEVENT</name>
            <addressOffset>0x19C</addressOffset>
            <absoluteAddress>0x4003819C</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>WDOGTIMEOUTEVENT</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>CLR_MSS_COUNTERS</name>
            <addressOffset>0x1A0</addressOffset>
            <absoluteAddress>0x400381A0</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CC_DC_TRANS_CNTCLR</name>
              <bitNumber>5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CC_IC_TRANS_CNTCLR</name>
              <bitNumber>4</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CC_DC_HIT_CNTCLR</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CC_DC_MISS_CNTCLR</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CC_IC_HIT_CNTCLR</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CC_IC_MISS_CNTCLR</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>CLR_EDAC_COUNTERS</name>
            <addressOffset>0x1A4</addressOffset>
            <absoluteAddress>0x400381A4</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>CAN_EDAC_CNTCLR_2E</name>
              <bitNumber>13</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CAN_EDAC_CNTCLR_1E</name>
              <bitNumber>12</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>USB_EDAC_CNTCLR_2E</name>
              <bitNumber>11</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>USB_EDAC_CNTCLR_1E</name>
              <bitNumber>10</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MAC_EDAC_RX_CNTCLR_2E</name>
              <bitNumber>9</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MAC_EDAC_RX_CNTCLR_1E</name>
              <bitNumber>8</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MAC_EDAC_TX_CNTCLR_2E</name>
              <bitNumber>7</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>MAC_EDAC_TX_CNTCLR_1E</name>
              <bitNumber>6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM1_EDAC_CNTCLR_2E</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM1_EDAC_CNTCLR_1E</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM0_EDAC_CNTCLR_2E</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>ESRAM0_EDAC_CNTCLR_1E</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>FLUSH_CR</name>
            <addressOffset>0x1A8</addressOffset>
            <absoluteAddress>0x400381A8</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>DDRB_INVALID_IDC</name>
              <bitNumber>8</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_INVALID_HPD</name>
              <bitNumber>7</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_INVALID_SW</name>
              <bitNumber>6</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_INVALID_DS</name>
              <bitNumber>5</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_FLSHSW</name>
              <bitNumber>4</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_FLSHHPD</name>
              <bitNumber>3</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>DDRB_FLSHDS</name>
              <bitNumber>2</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CC_FLUSH_CHLINE</name>
              <bitNumber>1</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
            <field>
              <name>CC_FLUSH_CACHE</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
          <register>
            <name>MAC_STAT_CLR_CR</name>
            <addressOffset>0x1AC</addressOffset>
            <absoluteAddress>0x400381AC</absoluteAddress>
            <size>32</size>
            <access>R/W</access>
            <resetValue>0x0</resetValue>
            <field>
              <name>MAC_STAT_CLR</name>
              <bitNumber>0</bitNumber>
              <access>R/W</access>
              <description>
              </description>
            </field>
          </register>
        </addressBlock>
      </memoryMap>
    </peripheral>
    <peripheral>
      <name>MSSFIC2TOFABRIC</name>
      <baseAddress>0x40020000</baseAddress>
    </peripheral>
    <peripheral>
      <name>RTC</name>
      <baseAddress>0x40017000</baseAddress>
    </peripheral>
    <peripheral>
      <name>COMBLK</name>
      <baseAddress>0x40016000</baseAddress>
    </peripheral>
    <peripheral>
      <name>HDMA</name>
      <baseAddress>0x40014000</baseAddress>
    </peripheral>
    <peripheral>
      <name>GPIO</name>
      <baseAddress>0x40013000</baseAddress>
    </peripheral>
    <peripheral>
      <name>H2FINTERRUPT</name>
      <baseAddress>0x40006000</baseAddress>
    </peripheral>
    <peripheral>
      <name>TIMER</name>
      <baseAddress>0x40004000</baseAddress>
    </peripheral>
    <peripheral>
      <name>MMUART_0</name>
      <baseAddress>0x40000000</baseAddress>
    </peripheral>
    <peripheral>
      <name>RECYCLED_ESRAM1</name>
      <baseAddress>0x20012000</baseAddress>
    </peripheral>
    <peripheral>
      <name>RECYCLED_ESRAM0</name>
      <baseAddress>0x20010000</baseAddress>
    </peripheral>
    <peripheral>
      <name>ESRAM1</name>
      <baseAddress>0x20008000</baseAddress>
    </peripheral>
    <peripheral>
      <name>ESRAM0</name>
      <baseAddress>0x20000000</baseAddress>
    </peripheral>
  </peripherals>
</device>