0081-RISCV-Define-getSetCCResultType-for-setting-vector-s.patch

From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <asb@lowrisc.org>
Subject: [RISCV] Define getSetCCResultType for setting vector setCC type

To avoid trigger "No default SetCC type for vectors!" Assertion

Differential Revision: https://reviews.llvm.org/D42675
Patch by Shiva Chen.
---
 lib/Target/RISCV/RISCVISelLowering.cpp      |  7 ++++++
 lib/Target/RISCV/RISCVISelLowering.h        |  3 +++
 test/CodeGen/RISCV/get-setcc-result-type.ll | 35 +++++++++++++++++++++++++++++
 3 files changed, 45 insertions(+)
 create mode 100644 test/CodeGen/RISCV/get-setcc-result-type.ll

diff --git a/lib/Target/RISCV/RISCVISelLowering.cpp b/lib/Target/RISCV/RISCVISelLowering.cpp
index bac74ee62c5..c48e76cf32b 100644
--- a/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -229,6 +229,13 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(
   Known.One &= Known2.One;
 }
 
+EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
+                                            EVT VT) const {
+  if (!VT.isVector())
+    return getPointerTy(DL);
+  return VT.changeVectorElementTypeToInteger();
+}
+
 // Changes the condition code and swaps operands if necessary, so the SetCC
 // operation matches one of the comparisons supported directly in the RISC-V
 // ISA.
diff --git a/lib/Target/RISCV/RISCVISelLowering.h b/lib/Target/RISCV/RISCVISelLowering.h
index 807cb9c0b8d..f15853c76eb 100644
--- a/lib/Target/RISCV/RISCVISelLowering.h
+++ b/lib/Target/RISCV/RISCVISelLowering.h
@@ -79,6 +79,9 @@ public:
   Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
                                  AtomicOrdering Ord) const override;
 
+  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
+                         EVT VT) const override;
+
 private:
   void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
                         const SmallVectorImpl<ISD::InputArg> &Ins,
diff --git a/test/CodeGen/RISCV/get-setcc-result-type.ll b/test/CodeGen/RISCV/get-setcc-result-type.ll
new file mode 100644
index 00000000000..003f3b367cf
--- /dev/null
+++ b/test/CodeGen/RISCV/get-setcc-result-type.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32I %s
+
+define void @getSetCCResultType(<4 x i32>* %p, <4 x i32>* %q) {
+; RV32I-LABEL: getSetCCResultType:
+; RV32I:       # %bb.0: # %entry
+; RV32I-NEXT:    lw a1, 12(a0)
+; RV32I-NEXT:    xor a1, a1, zero
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    sw a1, 12(a0)
+; RV32I-NEXT:    lw a1, 8(a0)
+; RV32I-NEXT:    xor a1, a1, zero
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    sw a1, 8(a0)
+; RV32I-NEXT:    lw a1, 4(a0)
+; RV32I-NEXT:    xor a1, a1, zero
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    sw a1, 4(a0)
+; RV32I-NEXT:    lw a1, 0(a0)
+; RV32I-NEXT:    xor a1, a1, zero
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    sw a1, 0(a0)
+; RV32I-NEXT:    ret
+entry:
+  %0 = load <4 x i32>, <4 x i32>* %p, align 16
+  %cmp = icmp eq <4 x i32> %0, zeroinitializer
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  store <4 x i32> %sext, <4 x i32>* %p, align 16
+  ret void
+}
-- 
2.16.2