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0066-RISCV-Implement-RISCVRegisterInfo-enableMultipleCopy.patch
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0066-RISCV-Implement-RISCVRegisterInfo-enableMultipleCopy.patch
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <[email protected]>
Subject: [RISCV] Implement RISCVRegisterInfo::enableMultipleCopyHints()
https://reviews.llvm.org/D38128 and r319754 introduced an opt-in register
allocator tweak with the stated intention of enabling it by default once
backends have all opted in. It doesn't seem to hurt us at least, so let's opt
in.
---
lib/Target/RISCV/RISCVRegisterInfo.h | 2 +
test/CodeGen/RISCV/double-select-fcmp.ll | 2 +-
test/CodeGen/RISCV/vararg.ll | 100 +++++++++++++++----------------
3 files changed, 53 insertions(+), 51 deletions(-)
diff --git a/lib/Target/RISCV/RISCVRegisterInfo.h b/lib/Target/RISCV/RISCVRegisterInfo.h
index a81dea09401..6ae0cfd8c0f 100644
--- a/lib/Target/RISCV/RISCVRegisterInfo.h
+++ b/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -51,6 +51,8 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
bool trackLivenessAfterRegAlloc(const MachineFunction &) const override {
return true;
}
+
+ bool enableMultipleCopyHints() const override { return true; }
};
}
diff --git a/test/CodeGen/RISCV/double-select-fcmp.ll b/test/CodeGen/RISCV/double-select-fcmp.ll
index abb9ee5c8be..3a5ec81b44e 100644
--- a/test/CodeGen/RISCV/double-select-fcmp.ll
+++ b/test/CodeGen/RISCV/double-select-fcmp.ll
@@ -5,8 +5,8 @@
define double @select_fcmp_false(double %a, double %b) nounwind {
; RV32IFD-LABEL: select_fcmp_false:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: addi a0, a2, 0
; RV32IFD-NEXT: addi a1, a3, 0
+; RV32IFD-NEXT: addi a0, a2, 0
; RV32IFD-NEXT: jalr zero, ra, 0
%1 = fcmp false double %a, %b
%2 = select i1 %1, double %a, double %b
diff --git a/test/CodeGen/RISCV/vararg.ll b/test/CodeGen/RISCV/vararg.ll
index 2564d91361e..e9b7b07ff0c 100644
--- a/test/CodeGen/RISCV/vararg.ll
+++ b/test/CodeGen/RISCV/vararg.ll
@@ -383,24 +383,24 @@ define double @va3(i32 %a, double %b, ...) nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -32
; RV32I-FPELIM-NEXT: sw ra, 4(sp)
+; RV32I-FPELIM-NEXT: addi t0, a2, 0
+; RV32I-FPELIM-NEXT: addi a0, a1, 0
; RV32I-FPELIM-NEXT: sw a7, 28(sp)
; RV32I-FPELIM-NEXT: sw a6, 24(sp)
; RV32I-FPELIM-NEXT: sw a5, 20(sp)
; RV32I-FPELIM-NEXT: sw a4, 16(sp)
; RV32I-FPELIM-NEXT: sw a3, 12(sp)
-; RV32I-FPELIM-NEXT: addi a0, sp, 27
-; RV32I-FPELIM-NEXT: sw a0, 0(sp)
-; RV32I-FPELIM-NEXT: lui a0, %hi(__adddf3)
-; RV32I-FPELIM-NEXT: addi a5, a0, %lo(__adddf3)
-; RV32I-FPELIM-NEXT: addi a0, sp, 19
-; RV32I-FPELIM-NEXT: andi a0, a0, -8
-; RV32I-FPELIM-NEXT: lw a4, 0(a0)
-; RV32I-FPELIM-NEXT: ori a0, a0, 4
-; RV32I-FPELIM-NEXT: lw a3, 0(a0)
-; RV32I-FPELIM-NEXT: addi a0, a1, 0
-; RV32I-FPELIM-NEXT: addi a1, a2, 0
-; RV32I-FPELIM-NEXT: addi a2, a4, 0
-; RV32I-FPELIM-NEXT: jalr ra, a5, 0
+; RV32I-FPELIM-NEXT: addi a1, sp, 27
+; RV32I-FPELIM-NEXT: sw a1, 0(sp)
+; RV32I-FPELIM-NEXT: lui a1, %hi(__adddf3)
+; RV32I-FPELIM-NEXT: addi a4, a1, %lo(__adddf3)
+; RV32I-FPELIM-NEXT: addi a1, sp, 19
+; RV32I-FPELIM-NEXT: andi a1, a1, -8
+; RV32I-FPELIM-NEXT: lw a2, 0(a1)
+; RV32I-FPELIM-NEXT: ori a1, a1, 4
+; RV32I-FPELIM-NEXT: lw a3, 0(a1)
+; RV32I-FPELIM-NEXT: addi a1, t0, 0
+; RV32I-FPELIM-NEXT: jalr ra, a4, 0
; RV32I-FPELIM-NEXT: lw ra, 4(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 32
; RV32I-FPELIM-NEXT: jalr zero, ra, 0
@@ -411,24 +411,24 @@ define double @va3(i32 %a, double %b, ...) nounwind {
; RV32I-WITHFP-NEXT: sw ra, 20(sp)
; RV32I-WITHFP-NEXT: sw s0, 16(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 24
+; RV32I-WITHFP-NEXT: addi t0, a2, 0
+; RV32I-WITHFP-NEXT: addi a0, a1, 0
; RV32I-WITHFP-NEXT: sw a7, 20(s0)
; RV32I-WITHFP-NEXT: sw a6, 16(s0)
; RV32I-WITHFP-NEXT: sw a5, 12(s0)
; RV32I-WITHFP-NEXT: sw a4, 8(s0)
; RV32I-WITHFP-NEXT: sw a3, 4(s0)
-; RV32I-WITHFP-NEXT: addi a0, s0, 19
-; RV32I-WITHFP-NEXT: sw a0, -12(s0)
-; RV32I-WITHFP-NEXT: lui a0, %hi(__adddf3)
-; RV32I-WITHFP-NEXT: addi a5, a0, %lo(__adddf3)
-; RV32I-WITHFP-NEXT: addi a0, s0, 11
-; RV32I-WITHFP-NEXT: andi a0, a0, -8
-; RV32I-WITHFP-NEXT: lw a4, 0(a0)
-; RV32I-WITHFP-NEXT: ori a0, a0, 4
-; RV32I-WITHFP-NEXT: lw a3, 0(a0)
-; RV32I-WITHFP-NEXT: addi a0, a1, 0
-; RV32I-WITHFP-NEXT: addi a1, a2, 0
-; RV32I-WITHFP-NEXT: addi a2, a4, 0
-; RV32I-WITHFP-NEXT: jalr ra, a5, 0
+; RV32I-WITHFP-NEXT: addi a1, s0, 19
+; RV32I-WITHFP-NEXT: sw a1, -12(s0)
+; RV32I-WITHFP-NEXT: lui a1, %hi(__adddf3)
+; RV32I-WITHFP-NEXT: addi a4, a1, %lo(__adddf3)
+; RV32I-WITHFP-NEXT: addi a1, s0, 11
+; RV32I-WITHFP-NEXT: andi a1, a1, -8
+; RV32I-WITHFP-NEXT: lw a2, 0(a1)
+; RV32I-WITHFP-NEXT: ori a1, a1, 4
+; RV32I-WITHFP-NEXT: lw a3, 0(a1)
+; RV32I-WITHFP-NEXT: addi a1, t0, 0
+; RV32I-WITHFP-NEXT: jalr ra, a4, 0
; RV32I-WITHFP-NEXT: lw s0, 16(sp)
; RV32I-WITHFP-NEXT: lw ra, 20(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 48
@@ -455,25 +455,25 @@ define double @va3_va_arg(i32 %a, double %b, ...) nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -32
; RV32I-FPELIM-NEXT: sw ra, 4(sp)
+; RV32I-FPELIM-NEXT: addi t0, a2, 0
+; RV32I-FPELIM-NEXT: addi a0, a1, 0
; RV32I-FPELIM-NEXT: sw a7, 28(sp)
; RV32I-FPELIM-NEXT: sw a6, 24(sp)
; RV32I-FPELIM-NEXT: sw a5, 20(sp)
; RV32I-FPELIM-NEXT: sw a4, 16(sp)
; RV32I-FPELIM-NEXT: sw a3, 12(sp)
-; RV32I-FPELIM-NEXT: addi a0, sp, 19
-; RV32I-FPELIM-NEXT: andi a0, a0, -8
-; RV32I-FPELIM-NEXT: ori a3, a0, 4
+; RV32I-FPELIM-NEXT: addi a1, sp, 19
+; RV32I-FPELIM-NEXT: andi a1, a1, -8
+; RV32I-FPELIM-NEXT: ori a3, a1, 4
; RV32I-FPELIM-NEXT: sw a3, 0(sp)
-; RV32I-FPELIM-NEXT: lw a4, 0(a0)
-; RV32I-FPELIM-NEXT: addi a0, a3, 4
-; RV32I-FPELIM-NEXT: sw a0, 0(sp)
-; RV32I-FPELIM-NEXT: lui a0, %hi(__adddf3)
-; RV32I-FPELIM-NEXT: addi a5, a0, %lo(__adddf3)
+; RV32I-FPELIM-NEXT: lw a2, 0(a1)
+; RV32I-FPELIM-NEXT: addi a1, a3, 4
+; RV32I-FPELIM-NEXT: sw a1, 0(sp)
+; RV32I-FPELIM-NEXT: lui a1, %hi(__adddf3)
+; RV32I-FPELIM-NEXT: addi a4, a1, %lo(__adddf3)
; RV32I-FPELIM-NEXT: lw a3, 0(a3)
-; RV32I-FPELIM-NEXT: addi a0, a1, 0
-; RV32I-FPELIM-NEXT: addi a1, a2, 0
-; RV32I-FPELIM-NEXT: addi a2, a4, 0
-; RV32I-FPELIM-NEXT: jalr ra, a5, 0
+; RV32I-FPELIM-NEXT: addi a1, t0, 0
+; RV32I-FPELIM-NEXT: jalr ra, a4, 0
; RV32I-FPELIM-NEXT: lw ra, 4(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 32
; RV32I-FPELIM-NEXT: jalr zero, ra, 0
@@ -484,25 +484,25 @@ define double @va3_va_arg(i32 %a, double %b, ...) nounwind {
; RV32I-WITHFP-NEXT: sw ra, 20(sp)
; RV32I-WITHFP-NEXT: sw s0, 16(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 24
+; RV32I-WITHFP-NEXT: addi t0, a2, 0
+; RV32I-WITHFP-NEXT: addi a0, a1, 0
; RV32I-WITHFP-NEXT: sw a7, 20(s0)
; RV32I-WITHFP-NEXT: sw a6, 16(s0)
; RV32I-WITHFP-NEXT: sw a5, 12(s0)
; RV32I-WITHFP-NEXT: sw a4, 8(s0)
; RV32I-WITHFP-NEXT: sw a3, 4(s0)
-; RV32I-WITHFP-NEXT: addi a0, s0, 11
-; RV32I-WITHFP-NEXT: andi a0, a0, -8
-; RV32I-WITHFP-NEXT: ori a3, a0, 4
+; RV32I-WITHFP-NEXT: addi a1, s0, 11
+; RV32I-WITHFP-NEXT: andi a1, a1, -8
+; RV32I-WITHFP-NEXT: ori a3, a1, 4
; RV32I-WITHFP-NEXT: sw a3, -12(s0)
-; RV32I-WITHFP-NEXT: lw a4, 0(a0)
-; RV32I-WITHFP-NEXT: addi a0, a3, 4
-; RV32I-WITHFP-NEXT: sw a0, -12(s0)
-; RV32I-WITHFP-NEXT: lui a0, %hi(__adddf3)
-; RV32I-WITHFP-NEXT: addi a5, a0, %lo(__adddf3)
+; RV32I-WITHFP-NEXT: lw a2, 0(a1)
+; RV32I-WITHFP-NEXT: addi a1, a3, 4
+; RV32I-WITHFP-NEXT: sw a1, -12(s0)
+; RV32I-WITHFP-NEXT: lui a1, %hi(__adddf3)
+; RV32I-WITHFP-NEXT: addi a4, a1, %lo(__adddf3)
; RV32I-WITHFP-NEXT: lw a3, 0(a3)
-; RV32I-WITHFP-NEXT: addi a0, a1, 0
-; RV32I-WITHFP-NEXT: addi a1, a2, 0
-; RV32I-WITHFP-NEXT: addi a2, a4, 0
-; RV32I-WITHFP-NEXT: jalr ra, a5, 0
+; RV32I-WITHFP-NEXT: addi a1, t0, 0
+; RV32I-WITHFP-NEXT: jalr ra, a4, 0
; RV32I-WITHFP-NEXT: lw s0, 16(sp)
; RV32I-WITHFP-NEXT: lw ra, 20(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 48
--
2.16.2