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0042-RISCV-Implement-frame-pointer-elimination.patch
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0042-RISCV-Implement-frame-pointer-elimination.patch
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <[email protected]>
Subject: [RISCV] Implement frame pointer elimination
---
lib/Target/RISCV/RISCVFrameLowering.cpp | 41 +-
lib/Target/RISCV/RISCVRegisterInfo.cpp | 6 +-
test/CodeGen/RISCV/addc-adde-sube-subc.ll | 14 -
test/CodeGen/RISCV/alu32.ll | 133 ---
test/CodeGen/RISCV/analyze-branch.ll | 6 -
test/CodeGen/RISCV/bare-select.ll | 7 -
test/CodeGen/RISCV/blockaddress.ll | 3 -
test/CodeGen/RISCV/branch-relaxation.ll | 20 +-
test/CodeGen/RISCV/branch.ll | 7 -
test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll | 115 +--
test/CodeGen/RISCV/byval.ll | 20 +-
test/CodeGen/RISCV/calling-conv-sext-zext.ll | 117 ---
test/CodeGen/RISCV/calling-conv.ll | 1409 +++++++++++++++++---------
test/CodeGen/RISCV/calls.ll | 65 +-
test/CodeGen/RISCV/div.ll | 38 -
test/CodeGen/RISCV/fp128.ll | 66 +-
test/CodeGen/RISCV/frame.ll | 62 +-
test/CodeGen/RISCV/frameaddr-returnaddr.ll | 7 -
test/CodeGen/RISCV/i32-icmp.ll | 70 --
test/CodeGen/RISCV/imm.ll | 35 -
test/CodeGen/RISCV/indirectbr.ll | 6 -
test/CodeGen/RISCV/inline-asm.ll | 28 -
test/CodeGen/RISCV/jumptable.ll | 13 +-
test/CodeGen/RISCV/large-stack.ll | 223 ++--
test/CodeGen/RISCV/mem.ll | 84 --
test/CodeGen/RISCV/mul.ll | 22 -
test/CodeGen/RISCV/rem.ll | 6 -
test/CodeGen/RISCV/rotl-rotr.ll | 14 -
test/CodeGen/RISCV/select-cc.ll | 7 -
test/CodeGen/RISCV/sext-zext-trunc.ll | 210 ----
test/CodeGen/RISCV/shifts.ll | 9 -
test/CodeGen/RISCV/vararg.ll | 1050 ++++++++++++-------
test/CodeGen/RISCV/wide-mem.ll | 14 -
33 files changed, 1886 insertions(+), 2041 deletions(-)
diff --git a/lib/Target/RISCV/RISCVFrameLowering.cpp b/lib/Target/RISCV/RISCVFrameLowering.cpp
index 32ed896bc98..33703f5ec20 100644
--- a/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -22,7 +22,14 @@
using namespace llvm;
-bool RISCVFrameLowering::hasFP(const MachineFunction &MF) const { return true; }
+bool RISCVFrameLowering::hasFP(const MachineFunction &MF) const {
+ const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
+
+ const MachineFrameInfo &MFI = MF.getFrameInfo();
+ return MF.getTarget().Options.DisableFramePointerElim(MF) ||
+ RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() ||
+ MFI.isFrameAddressTaken();
+}
// Determines the size of the frame and maximum call frame size.
void RISCVFrameLowering::determineFrameLayout(MachineFunction &MF) const {
@@ -103,11 +110,6 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
- if (!hasFP(MF)) {
- report_fatal_error(
- "emitPrologue doesn't support framepointer-less functions");
- }
-
MachineFrameInfo &MFI = MF.getFrameInfo();
auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
MachineBasicBlock::iterator MBBI = MBB.begin();
@@ -143,17 +145,13 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
std::advance(MBBI, CSI.size());
// Generate new FP.
- adjustReg(MBB, MBBI, DL, FPReg, SPReg, StackSize - RVFI->getVarArgsSaveSize(),
- MachineInstr::FrameSetup);
+ if (hasFP(MF))
+ adjustReg(MBB, MBBI, DL, FPReg, SPReg,
+ StackSize - RVFI->getVarArgsSaveSize(), MachineInstr::FrameSetup);
}
void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
- if (!hasFP(MF)) {
- report_fatal_error(
- "emitEpilogue doesn't support framepointer-less functions");
- }
-
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
const RISCVRegisterInfo *RI = STI.getRegisterInfo();
MachineFrameInfo &MFI = MF.getFrameInfo();
@@ -174,6 +172,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
// necessary if the stack pointer was modified, meaning the stack size is
// unknown.
if (RI->needsStackRealignment(MF) || MFI.hasVarSizedObjects()) {
+ assert(hasFP(MF) && "frame pointer should not have been eliminated");
adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg,
-StackSize + RVFI->getVarArgsSaveSize(),
MachineInstr::FrameDestroy);
@@ -210,8 +209,10 @@ int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF,
Offset += MF.getFrameInfo().getStackSize();
} else {
FrameReg = RI->getFrameRegister(MF);
- assert(hasFP(MF) && "Offset calculation incorrect if !hasFP");
- Offset += RVFI->getVarArgsSaveSize();
+ if (hasFP(MF))
+ Offset += RVFI->getVarArgsSaveSize();
+ else
+ Offset += MF.getFrameInfo().getStackSize();
}
return Offset;
}
@@ -220,10 +221,12 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
BitVector &SavedRegs,
RegScavenger *RS) const {
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
- // TODO: Once frame pointer elimination is implemented, don't
- // unconditionally spill the frame pointer and return address.
- SavedRegs.set(RISCV::X1);
- SavedRegs.set(RISCV::X8);
+ // Unconditionally spill RA and FP only if the function uses a frame
+ // pointer.
+ if (hasFP(MF)) {
+ SavedRegs.set(RISCV::X1);
+ SavedRegs.set(RISCV::X8);
+ }
}
void RISCVFrameLowering::processFunctionBeforeFrameFinalized(
diff --git a/lib/Target/RISCV/RISCVRegisterInfo.cpp b/lib/Target/RISCV/RISCVRegisterInfo.cpp
index b634097bae3..6ad8bf7bca0 100644
--- a/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -71,9 +71,6 @@ void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) +
MI.getOperand(FIOperandNum + 1).getImm();
- assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
- "eliminateFrameIndex currently requires hasFP");
-
if (!isInt<32>(Offset)) {
report_fatal_error(
"Frame offsets outside of the signed 32-bit range not supported");
@@ -102,7 +99,8 @@ void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
}
unsigned RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
- return RISCV::X8;
+ const TargetFrameLowering *TFI = getFrameLowering(MF);
+ return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
}
const uint32_t *
diff --git a/test/CodeGen/RISCV/addc-adde-sube-subc.ll b/test/CodeGen/RISCV/addc-adde-sube-subc.ll
index ba5200591bf..54f5482b9e7 100644
--- a/test/CodeGen/RISCV/addc-adde-sube-subc.ll
+++ b/test/CodeGen/RISCV/addc-adde-sube-subc.ll
@@ -7,18 +7,11 @@
define i64 @addc_adde(i64 %a, i64 %b) {
; RV32I-LABEL: addc_adde:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: add a1, a1, a3
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a1, a1, a0
; RV32I-NEXT: addi a0, a2, 0
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = add i64 %a, %b
ret i64 %1
@@ -27,17 +20,10 @@ define i64 @addc_adde(i64 %a, i64 %b) {
define i64 @subc_sube(i64 %a, i64 %b) {
; RV32I-LABEL: subc_sube:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sub a1, a1, a3
; RV32I-NEXT: sltu a3, a0, a2
; RV32I-NEXT: sub a1, a1, a3
; RV32I-NEXT: sub a0, a0, a2
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = sub i64 %a, %b
ret i64 %1
diff --git a/test/CodeGen/RISCV/alu32.ll b/test/CodeGen/RISCV/alu32.ll
index bc2fc9aec82..e7c82181027 100644
--- a/test/CodeGen/RISCV/alu32.ll
+++ b/test/CodeGen/RISCV/alu32.ll
@@ -11,14 +11,7 @@
define i32 @addi(i32 %a) nounwind {
; RV32I-LABEL: addi:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a0, a0, 1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = add i32 %a, 1
ret i32 %1
@@ -27,14 +20,7 @@ define i32 @addi(i32 %a) nounwind {
define i32 @slti(i32 %a) nounwind {
; RV32I-LABEL: slti:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slti a0, a0, 2
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = icmp slt i32 %a, 2
%2 = zext i1 %1 to i32
@@ -44,14 +30,7 @@ define i32 @slti(i32 %a) nounwind {
define i32 @sltiu(i32 %a) nounwind {
; RV32I-LABEL: sltiu:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sltiu a0, a0, 3
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = icmp ult i32 %a, 3
%2 = zext i1 %1 to i32
@@ -61,14 +40,7 @@ define i32 @sltiu(i32 %a) nounwind {
define i32 @xori(i32 %a) nounwind {
; RV32I-LABEL: xori:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: xori a0, a0, 4
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = xor i32 %a, 4
ret i32 %1
@@ -77,14 +49,7 @@ define i32 @xori(i32 %a) nounwind {
define i32 @ori(i32 %a) nounwind {
; RV32I-LABEL: ori:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: ori a0, a0, 5
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = or i32 %a, 5
ret i32 %1
@@ -93,14 +58,7 @@ define i32 @ori(i32 %a) nounwind {
define i32 @andi(i32 %a) nounwind {
; RV32I-LABEL: andi:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 6
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = and i32 %a, 6
ret i32 %1
@@ -109,14 +67,7 @@ define i32 @andi(i32 %a) nounwind {
define i32 @slli(i32 %a) nounwind {
; RV32I-LABEL: slli:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slli a0, a0, 7
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = shl i32 %a, 7
ret i32 %1
@@ -125,14 +76,7 @@ define i32 @slli(i32 %a) nounwind {
define i32 @srli(i32 %a) nounwind {
; RV32I-LABEL: srli:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: srli a0, a0, 8
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = lshr i32 %a, 8
ret i32 %1
@@ -141,14 +85,7 @@ define i32 @srli(i32 %a) nounwind {
define i32 @srai(i32 %a) nounwind {
; RV32I-LABEL: srai:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: srai a0, a0, 9
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = ashr i32 %a, 9
ret i32 %1
@@ -159,14 +96,7 @@ define i32 @srai(i32 %a) nounwind {
define i32 @add(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: add:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = add i32 %a, %b
ret i32 %1
@@ -175,14 +105,7 @@ define i32 @add(i32 %a, i32 %b) nounwind {
define i32 @sub(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sub:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sub a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = sub i32 %a, %b
ret i32 %1
@@ -191,14 +114,7 @@ define i32 @sub(i32 %a, i32 %b) nounwind {
define i32 @sll(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sll:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sll a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = shl i32 %a, %b
ret i32 %1
@@ -207,14 +123,7 @@ define i32 @sll(i32 %a, i32 %b) nounwind {
define i32 @slt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: slt:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: slt a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = icmp slt i32 %a, %b
%2 = zext i1 %1 to i32
@@ -224,14 +133,7 @@ define i32 @slt(i32 %a, i32 %b) nounwind {
define i32 @sltu(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sltu:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sltu a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = icmp ult i32 %a, %b
%2 = zext i1 %1 to i32
@@ -241,14 +143,7 @@ define i32 @sltu(i32 %a, i32 %b) nounwind {
define i32 @xor(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: xor:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = xor i32 %a, %b
ret i32 %1
@@ -257,14 +152,7 @@ define i32 @xor(i32 %a, i32 %b) nounwind {
define i32 @srl(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: srl:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: srl a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = lshr i32 %a, %b
ret i32 %1
@@ -273,14 +161,7 @@ define i32 @srl(i32 %a, i32 %b) nounwind {
define i32 @sra(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sra:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: sra a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = ashr i32 %a, %b
ret i32 %1
@@ -289,14 +170,7 @@ define i32 @sra(i32 %a, i32 %b) nounwind {
define i32 @or(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: or:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: or a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = or i32 %a, %b
ret i32 %1
@@ -305,14 +179,7 @@ define i32 @or(i32 %a, i32 %b) nounwind {
define i32 @and(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: and:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = and i32 %a, %b
ret i32 %1
diff --git a/test/CodeGen/RISCV/analyze-branch.ll b/test/CodeGen/RISCV/analyze-branch.ll
index 6e339572d3d..5bd17b7d647 100644
--- a/test/CodeGen/RISCV/analyze-branch.ll
+++ b/test/CodeGen/RISCV/analyze-branch.ll
@@ -17,8 +17,6 @@ define void @test_bcc_fallthrough_taken(i32 %in) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a1, zero, 42
; RV32I-NEXT: bne a0, a1, .LBB0_3
; RV32I-NEXT: # %bb.1: # %true
@@ -26,7 +24,6 @@ define void @test_bcc_fallthrough_taken(i32 %in) nounwind {
; RV32I-NEXT: addi a0, a0, %lo(test_true)
; RV32I-NEXT: .LBB0_2: # %true
; RV32I-NEXT: jalr ra, a0, 0
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
@@ -55,8 +52,6 @@ define void @test_bcc_fallthrough_nottaken(i32 %in) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a1, zero, 42
; RV32I-NEXT: beq a0, a1, .LBB1_3
; RV32I-NEXT: # %bb.1: # %false
@@ -64,7 +59,6 @@ define void @test_bcc_fallthrough_nottaken(i32 %in) nounwind {
; RV32I-NEXT: addi a0, a0, %lo(test_false)
; RV32I-NEXT: .LBB1_2: # %true
; RV32I-NEXT: jalr ra, a0, 0
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
diff --git a/test/CodeGen/RISCV/bare-select.ll b/test/CodeGen/RISCV/bare-select.ll
index f277453e32a..a46afe27143 100644
--- a/test/CodeGen/RISCV/bare-select.ll
+++ b/test/CodeGen/RISCV/bare-select.ll
@@ -5,19 +5,12 @@
define i32 @bare_select(i1 %a, i32 %b, i32 %c) {
; RV32I-LABEL: bare_select:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: bne a0, zero, .LBB0_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: addi a1, a2, 0
; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: addi a0, a1, 0
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%1 = select i1 %a, i32 %b, i32 %c
ret i32 %1
diff --git a/test/CodeGen/RISCV/blockaddress.ll b/test/CodeGen/RISCV/blockaddress.ll
index 5a1438c2828..266bf4f2b27 100644
--- a/test/CodeGen/RISCV/blockaddress.ll
+++ b/test/CodeGen/RISCV/blockaddress.ll
@@ -9,8 +9,6 @@ define void @test_blockaddress() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a0, %hi(addr)
; RV32I-NEXT: addi a0, a0, %lo(addr)
; RV32I-NEXT: lui a1, %hi(.Ltmp0)
@@ -20,7 +18,6 @@ define void @test_blockaddress() nounwind {
; RV32I-NEXT: jalr zero, a0, 0
; RV32I-NEXT: .Ltmp0: # Block address taken
; RV32I-NEXT: .LBB0_1: # %block
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
diff --git a/test/CodeGen/RISCV/branch-relaxation.ll b/test/CodeGen/RISCV/branch-relaxation.ll
index a60fb9c421d..a7e2d1de4d2 100644
--- a/test/CodeGen/RISCV/branch-relaxation.ll
+++ b/test/CodeGen/RISCV/branch-relaxation.ll
@@ -6,10 +6,6 @@
define void @relax_bcc(i1 %a) {
; CHECK-LABEL: relax_bcc:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw ra, 12(sp)
-; CHECK-NEXT: sw s0, 8(sp)
-; CHECK-NEXT: addi s0, sp, 16
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: bne a0, zero, .LBB0_1
; CHECK-NEXT: jal zero, .LBB0_2
@@ -18,9 +14,6 @@ define void @relax_bcc(i1 %a) {
; CHECK-NEXT: .space 4096
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB0_2: # %tail
-; CHECK-NEXT: lw s0, 8(sp)
-; CHECK-NEXT: lw ra, 12(sp)
-; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, ra, 0
br i1 %a, label %iftrue, label %tail
@@ -35,13 +28,9 @@ tail:
define i32 @relax_jal(i1 %a) {
; CHECK-LABEL: relax_jal:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw ra, 12(sp)
-; CHECK-NEXT: sw s0, 8(sp)
-; CHECK-NEXT: addi s0, sp, 16
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: bne a0, zero, .LBB1_1
-; CHECK-NEXT: # %bb.4:
+; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: lui a0, %hi(.LBB1_2)
; CHECK-NEXT: jalr zero, a0, %lo(.LBB1_2)
; CHECK-NEXT: .LBB1_1: # %iftrue
@@ -50,15 +39,12 @@ define i32 @relax_jal(i1 %a) {
; CHECK-NEXT: #APP
; CHECK-NEXT: .space 1048576
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: jal zero, .LBB1_3
+; CHECK-NEXT: addi a0, zero, 1
+; CHECK-NEXT: jalr zero, ra, 0
; CHECK-NEXT: .LBB1_2: # %jmp
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB1_3: # %tail
; CHECK-NEXT: addi a0, zero, 1
-; CHECK-NEXT: lw s0, 8(sp)
-; CHECK-NEXT: lw ra, 12(sp)
-; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: jalr zero, ra, 0
br i1 %a, label %iftrue, label %jmp
diff --git a/test/CodeGen/RISCV/branch.ll b/test/CodeGen/RISCV/branch.ll
index 5139928120c..9192a268ebc 100644
--- a/test/CodeGen/RISCV/branch.ll
+++ b/test/CodeGen/RISCV/branch.ll
@@ -5,10 +5,6 @@
define void @foo(i32 %a, i32 *%b, i1 %c) {
; RV32I-LABEL: foo:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: beq a3, a0, .LBB0_12
; RV32I-NEXT: # %bb.1: # %test2
@@ -45,9 +41,6 @@ define void @foo(i32 %a, i32 *%b, i1 %c) {
; RV32I-NEXT: # %bb.11: # %test12
; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: .LBB0_12: # %end
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%val1 = load volatile i32, i32* %b
diff --git a/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll b/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
index fe3f8554500..8d257ce964f 100644
--- a/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
+++ b/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
@@ -15,10 +15,6 @@ declare i32 @llvm.ctpop.i32(i32)
define i16 @test_bswap_i16(i16 %a) nounwind {
; RV32I-LABEL: test_bswap_i16:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, 4080
; RV32I-NEXT: addi a1, a1, 0
; RV32I-NEXT: slli a2, a0, 8
@@ -26,9 +22,6 @@ define i16 @test_bswap_i16(i16 %a) nounwind {
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a0, a0, 16
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%tmp = call i16 @llvm.bswap.i16(i16 %a)
ret i16 %tmp
@@ -37,10 +30,6 @@ define i16 @test_bswap_i16(i16 %a) nounwind {
define i32 @test_bswap_i32(i32 %a) nounwind {
; RV32I-LABEL: test_bswap_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -256
; RV32I-NEXT: srli a2, a0, 8
@@ -54,9 +43,6 @@ define i32 @test_bswap_i32(i32 %a) nounwind {
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a0, a0, a1
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%tmp = call i32 @llvm.bswap.i32(i32 %a)
ret i32 %tmp
@@ -65,10 +51,6 @@ define i32 @test_bswap_i32(i32 %a) nounwind {
define i64 @test_bswap_i64(i64 %a) nounwind {
; RV32I-LABEL: test_bswap_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a3, a2, -256
; RV32I-NEXT: srli a2, a1, 8
@@ -92,9 +74,6 @@ define i64 @test_bswap_i64(i64 %a) nounwind {
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a1, a0, a1
; RV32I-NEXT: addi a0, a2, 0
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
%tmp = call i64 @llvm.bswap.i64(i64 %a)
ret i64 %tmp
@@ -105,8 +84,6 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a1, a0, 255
; RV32I-NEXT: beq a1, zero, .LBB3_2
; RV32I-NEXT: # %bb.1: # %cond.false
@@ -139,7 +116,6 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: addi a0, zero, 8
; RV32I-NEXT: .LBB3_3: # %cond.end
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
@@ -152,8 +128,6 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a1, a0, a1
@@ -188,7 +162,6 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: addi a0, zero, 16
; RV32I-NEXT: .LBB4_3: # %cond.end
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
@@ -201,8 +174,6 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: beq a0, zero, .LBB5_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi a1, a0, -1
@@ -234,7 +205,6 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV32I-NEXT: .LBB5_2:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB5_3: # %cond.end
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
@@ -247,8 +217,6 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: beq a0, zero, .LBB6_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: srli a1, a0, 1
@@ -288,7 +256,6 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB6_3: # %cond.end
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
@@ -301,16 +268,14 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
-; RV32I-NEXT: sw s0, 40(sp)
-; RV32I-NEXT: sw s1, 36(sp)
-; RV32I-NEXT: sw s2, 32(sp)
-; RV32I-NEXT: sw s3, 28(sp)
-; RV32I-NEXT: sw s4, 24(sp)
-; RV32I-NEXT: sw s5, 20(sp)
-; RV32I-NEXT: sw s6, 16(sp)
-; RV32I-NEXT: sw s7, 12(sp)
-; RV32I-NEXT: sw s8, 8(sp)
-; RV32I-NEXT: addi s0, sp, 48
+; RV32I-NEXT: sw s1, 40(sp)
+; RV32I-NEXT: sw s2, 36(sp)
+; RV32I-NEXT: sw s3, 32(sp)
+; RV32I-NEXT: sw s4, 28(sp)
+; RV32I-NEXT: sw s5, 24(sp)
+; RV32I-NEXT: sw s6, 20(sp)
+; RV32I-NEXT: sw s7, 16(sp)
+; RV32I-NEXT: sw s8, 12(sp)
; RV32I-NEXT: addi s2, a1, 0
; RV32I-NEXT: addi s3, a0, 0
; RV32I-NEXT: addi a0, s3, -1
@@ -363,15 +328,14 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: srli a0, s1, 24
; RV32I-NEXT: .LBB7_3:
; RV32I-NEXT: addi a1, zero, 0
-; RV32I-NEXT: lw s8, 8(sp)
-; RV32I-NEXT: lw s7, 12(sp)
-; RV32I-NEXT: lw s6, 16(sp)
-; RV32I-NEXT: lw s5, 20(sp)
-; RV32I-NEXT: lw s4, 24(sp)
-; RV32I-NEXT: lw s3, 28(sp)
-; RV32I-NEXT: lw s2, 32(sp)
-; RV32I-NEXT: lw s1, 36(sp)
-; RV32I-NEXT: lw s0, 40(sp)
+; RV32I-NEXT: lw s8, 12(sp)
+; RV32I-NEXT: lw s7, 16(sp)
+; RV32I-NEXT: lw s6, 20(sp)
+; RV32I-NEXT: lw s5, 24(sp)
+; RV32I-NEXT: lw s4, 28(sp)
+; RV32I-NEXT: lw s3, 32(sp)
+; RV32I-NEXT: lw s2, 36(sp)
+; RV32I-NEXT: lw s1, 40(sp)
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: jalr zero, ra, 0
@@ -384,8 +348,6 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: xori a0, a0, -1
; RV32I-NEXT: and a0, a0, a1
@@ -411,7 +373,6 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
; RV32I-NEXT: jalr ra, a2, 0
; RV32I-NEXT: srli a0, a0, 24
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
@@ -424,8 +385,6 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: xori a0, a0, -1
; RV32I-NEXT: and a0, a0, a1
@@ -451,7 +410,6 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
; RV32I-NEXT: jalr ra, a2, 0
; RV32I-NEXT: srli a0, a0, 24
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
@@ -464,8 +422,6 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: xori a0, a0, -1
; RV32I-NEXT: and a0, a0, a1
@@ -491,7 +447,6 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
; RV32I-NEXT: jalr ra, a2, 0
; RV32I-NEXT: srli a0, a0, 24
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
@@ -504,16 +459,14 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
-; RV32I-NEXT: sw s0, 40(sp)
-; RV32I-NEXT: sw s1, 36(sp)
-; RV32I-NEXT: sw s2, 32(sp)
-; RV32I-NEXT: sw s3, 28(sp)
-; RV32I-NEXT: sw s4, 24(sp)
-; RV32I-NEXT: sw s5, 20(sp)
-; RV32I-NEXT: sw s6, 16(sp)
-; RV32I-NEXT: sw s7, 12(sp)
-; RV32I-NEXT: sw s8, 8(sp)
-; RV32I-NEXT: addi s0, sp, 48
+; RV32I-NEXT: sw s1, 40(sp)
+; RV32I-NEXT: sw s2, 36(sp)
+; RV32I-NEXT: sw s3, 32(sp)
+; RV32I-NEXT: sw s4, 28(sp)
+; RV32I-NEXT: sw s5, 24(sp)
+; RV32I-NEXT: sw s6, 20(sp)
+; RV32I-NEXT: sw s7, 16(sp)
+; RV32I-NEXT: sw s8, 12(sp)
; RV32I-NEXT: addi s2, a1, 0
; RV32I-NEXT: addi s3, a0, 0
; RV32I-NEXT: addi a0, s3, -1
@@ -566,15 +519,14 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: srli a0, s1, 24
; RV32I-NEXT: .LBB11_3:
; RV32I-NEXT: addi a1, zero, 0
-; RV32I-NEXT: lw s8, 8(sp)
-; RV32I-NEXT: lw s7, 12(sp)
-; RV32I-NEXT: lw s6, 16(sp)
-; RV32I-NEXT: lw s5, 20(sp)
-; RV32I-NEXT: lw s4, 24(sp)
-; RV32I-NEXT: lw s3, 28(sp)
-; RV32I-NEXT: lw s2, 32(sp)
-; RV32I-NEXT: lw s1, 36(sp)
-; RV32I-NEXT: lw s0, 40(sp)
+; RV32I-NEXT: lw s8, 12(sp)
+; RV32I-NEXT: lw s7, 16(sp)
+; RV32I-NEXT: lw s6, 20(sp)
+; RV32I-NEXT: lw s5, 24(sp)
+; RV32I-NEXT: lw s4, 28(sp)
+; RV32I-NEXT: lw s3, 32(sp)
+; RV32I-NEXT: lw s2, 36(sp)
+; RV32I-NEXT: lw s1, 40(sp)
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: jalr zero, ra, 0
@@ -587,8 +539,6 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi a1, a1, 1365
; RV32I-NEXT: srli a2, a0, 1
@@ -611,7 +561,6 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
; RV32I-NEXT: jalr ra, a2, 0
; RV32I-NEXT: srli a0, a0, 24
-; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
diff --git a/test/CodeGen/RISCV/byval.ll b/test/CodeGen/RISCV/byval.ll
index 6c67f60a436..30ba8e6562e 100644
--- a/test/CodeGen/RISCV/byval.ll
+++ b/test/CodeGen/RISCV/byval.ll
@@ -8,14 +8,7 @@
define i32 @callee(%struct.Foo* byval %f) nounwind {
; RV32I-LABEL: callee:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: addi sp, sp, -16
-; RV32I-NEXT: sw ra, 12(sp)
-; RV32I-NEXT: sw s0, 8(sp)
-; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: lw s0, 8(sp)
-; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: jalr zero, ra, 0
entry:
%0 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i32 0, i32 0
@@ -29,29 +22,26 @@ define void @caller() nounwind {
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: addi s0, sp, 32
; RV32I-NEXT: lui a0, %hi(foo+12)
; RV32I-NEXT: addi a0, a0, %lo(foo+12)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -12(s0)
+; RV32I-NEXT: sw a0, 24(sp)
; RV32I-NEXT: lui a0, %hi(foo+8)
; RV32I-NEXT: addi a0, a0, %lo(foo+8)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -16(s0)
+; RV32I-NEXT: sw a0, 20(sp)
; RV32I-NEXT: lui a0, %hi(foo+4)
; RV32I-NEXT: addi a0, a0, %lo(foo+4)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -20(s0)
+; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: lui a0, %hi(foo)
; RV32I-NEXT: addi a0, a0, %lo(foo)
; RV32I-NEXT: lw a0, 0(a0)
-; RV32I-NEXT: sw a0, -24(s0)
+; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: lui a0, %hi(callee)
; RV32I-NEXT: addi a1, a0, %lo(callee)
-; RV32I-NEXT: addi a0, s0, -24