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0003-RISCV-Add-RISC-V-ELF-defines.patch
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0003-RISCV-Add-RISC-V-ELF-defines.patch
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <[email protected]>
Subject: [RISCV] Add RISC-V ELF defines
Add the necessary definitions for RISC-V ELF files, including relocs.
Also make necessary trivial change to ELFYaml, llvm-objdump, and
llvm-readobj in order to work with RISC-V ELFs.
Differential Revision: https://reviews.llvm.org/D23558
Upstream commit: https://reviews.llvm.org/rL285708
Upstream commit: https://reviews.llvm.org/rL285709
Upstream commit: https://reviews.llvm.org/rL285730
Includes additional relocation types and eflags support in ObjectYAML
submitted by Chih-Mao Chen,
https://reviews.llvm.org/D36455 https://reviews.llvm.org/rL310914
https://reviews.llvm.org/D38311
---
include/llvm/BinaryFormat/ELF.h | 17 ++++++++
include/llvm/BinaryFormat/ELFRelocs/RISCV.def | 59 +++++++++++++++++++++++++++
include/llvm/Object/ELFObjectFile.h | 13 ++++++
include/llvm/module.modulemap | 1 +
lib/Object/ELF.cpp | 7 ++++
lib/ObjectYAML/ELFYAML.cpp | 12 ++++++
test/Object/RISCV/elf-flags.yaml | 24 +++++++++++
test/Object/RISCV/lit.local.cfg | 2 +
tools/llvm-objdump/llvm-objdump.cpp | 1 +
tools/llvm-readobj/ELFDumper.cpp | 11 +++++
10 files changed, 147 insertions(+)
create mode 100644 include/llvm/BinaryFormat/ELFRelocs/RISCV.def
create mode 100644 test/Object/RISCV/elf-flags.yaml
create mode 100644 test/Object/RISCV/lit.local.cfg
diff --git a/include/llvm/BinaryFormat/ELF.h b/include/llvm/BinaryFormat/ELF.h
index 38090afb0c3..a2321e72c98 100644
--- a/include/llvm/BinaryFormat/ELF.h
+++ b/include/llvm/BinaryFormat/ELF.h
@@ -309,6 +309,7 @@ enum {
EM_NORC = 218, // Nanoradio Optimized RISC
EM_CSR_KALIMBA = 219, // CSR Kalimba architecture family
EM_AMDGPU = 224, // AMD GPU architecture
+ EM_RISCV = 243, // RISC-V
EM_LANAI = 244, // Lanai 32-bit processor
EM_BPF = 247, // Linux kernel bpf virtual machine
@@ -617,6 +618,22 @@ enum {
#include "ELFRelocs/Lanai.def"
};
+// RISCV Specific e_flags
+enum : unsigned {
+ EF_RISCV_RVC = 0x0001,
+ EF_RISCV_FLOAT_ABI = 0x0006,
+ EF_RISCV_FLOAT_ABI_SOFT = 0x0000,
+ EF_RISCV_FLOAT_ABI_SINGLE = 0x0002,
+ EF_RISCV_FLOAT_ABI_DOUBLE = 0x0004,
+ EF_RISCV_FLOAT_ABI_QUAD = 0x0006,
+ EF_RISCV_RVE = 0x0008
+};
+
+// ELF Relocation types for RISC-V
+enum {
+#include "ELFRelocs/RISCV.def"
+};
+
// ELF Relocation types for S390/zSeries
enum {
#include "ELFRelocs/SystemZ.def"
diff --git a/include/llvm/BinaryFormat/ELFRelocs/RISCV.def b/include/llvm/BinaryFormat/ELFRelocs/RISCV.def
new file mode 100644
index 00000000000..5cc4c0ec302
--- /dev/null
+++ b/include/llvm/BinaryFormat/ELFRelocs/RISCV.def
@@ -0,0 +1,59 @@
+
+#ifndef ELF_RELOC
+#error "ELF_RELOC must be defined"
+#endif
+
+ELF_RELOC(R_RISCV_NONE, 0)
+ELF_RELOC(R_RISCV_32, 1)
+ELF_RELOC(R_RISCV_64, 2)
+ELF_RELOC(R_RISCV_RELATIVE, 3)
+ELF_RELOC(R_RISCV_COPY, 4)
+ELF_RELOC(R_RISCV_JUMP_SLOT, 5)
+ELF_RELOC(R_RISCV_TLS_DTPMOD32, 6)
+ELF_RELOC(R_RISCV_TLS_DTPMOD64, 7)
+ELF_RELOC(R_RISCV_TLS_DTPREL32, 8)
+ELF_RELOC(R_RISCV_TLS_DTPREL64, 9)
+ELF_RELOC(R_RISCV_TLS_TPREL32, 10)
+ELF_RELOC(R_RISCV_TLS_TPREL64, 11)
+ELF_RELOC(R_RISCV_BRANCH, 16)
+ELF_RELOC(R_RISCV_JAL, 17)
+ELF_RELOC(R_RISCV_CALL, 18)
+ELF_RELOC(R_RISCV_CALL_PLT, 19)
+ELF_RELOC(R_RISCV_GOT_HI20, 20)
+ELF_RELOC(R_RISCV_TLS_GOT_HI20, 21)
+ELF_RELOC(R_RISCV_TLS_GD_HI20, 22)
+ELF_RELOC(R_RISCV_PCREL_HI20, 23)
+ELF_RELOC(R_RISCV_PCREL_LO12_I, 24)
+ELF_RELOC(R_RISCV_PCREL_LO12_S, 25)
+ELF_RELOC(R_RISCV_HI20, 26)
+ELF_RELOC(R_RISCV_LO12_I, 27)
+ELF_RELOC(R_RISCV_LO12_S, 28)
+ELF_RELOC(R_RISCV_TPREL_HI20, 29)
+ELF_RELOC(R_RISCV_TPREL_LO12_I, 30)
+ELF_RELOC(R_RISCV_TPREL_LO12_S, 31)
+ELF_RELOC(R_RISCV_TPREL_ADD, 32)
+ELF_RELOC(R_RISCV_ADD8, 33)
+ELF_RELOC(R_RISCV_ADD16, 34)
+ELF_RELOC(R_RISCV_ADD32, 35)
+ELF_RELOC(R_RISCV_ADD64, 36)
+ELF_RELOC(R_RISCV_SUB8, 37)
+ELF_RELOC(R_RISCV_SUB16, 38)
+ELF_RELOC(R_RISCV_SUB32, 39)
+ELF_RELOC(R_RISCV_SUB64, 40)
+ELF_RELOC(R_RISCV_GNU_VTINHERIT, 41)
+ELF_RELOC(R_RISCV_GNU_VTENTRY, 42)
+ELF_RELOC(R_RISCV_ALIGN, 43)
+ELF_RELOC(R_RISCV_RVC_BRANCH, 44)
+ELF_RELOC(R_RISCV_RVC_JUMP, 45)
+ELF_RELOC(R_RISCV_RVC_LUI, 46)
+ELF_RELOC(R_RISCV_GPREL_I, 47)
+ELF_RELOC(R_RISCV_GPREL_S, 48)
+ELF_RELOC(R_RISCV_TPREL_I, 49)
+ELF_RELOC(R_RISCV_TPREL_S, 50)
+ELF_RELOC(R_RISCV_RELAX, 51)
+ELF_RELOC(R_RISCV_SUB6, 52)
+ELF_RELOC(R_RISCV_SET6, 53)
+ELF_RELOC(R_RISCV_SET8, 54)
+ELF_RELOC(R_RISCV_SET16, 55)
+ELF_RELOC(R_RISCV_SET32, 56)
+ELF_RELOC(R_RISCV_32_PCREL, 57)
diff --git a/include/llvm/Object/ELFObjectFile.h b/include/llvm/Object/ELFObjectFile.h
index 5eda163acfc..9c691e1c283 100644
--- a/include/llvm/Object/ELFObjectFile.h
+++ b/include/llvm/Object/ELFObjectFile.h
@@ -981,6 +981,8 @@ StringRef ELFObjectFile<ELFT>::getFileFormatName() const {
return "ELF32-mips";
case ELF::EM_PPC:
return "ELF32-ppc";
+ case ELF::EM_RISCV:
+ return "ELF32-riscv";
case ELF::EM_SPARC:
case ELF::EM_SPARC32PLUS:
return "ELF32-sparc";
@@ -1001,6 +1003,8 @@ StringRef ELFObjectFile<ELFT>::getFileFormatName() const {
return (IsLittleEndian ? "ELF64-aarch64-little" : "ELF64-aarch64-big");
case ELF::EM_PPC64:
return "ELF64-ppc64";
+ case ELF::EM_RISCV:
+ return "ELF64-riscv";
case ELF::EM_S390:
return "ELF64-s390";
case ELF::EM_SPARCV9:
@@ -1053,6 +1057,15 @@ template <class ELFT> Triple::ArchType ELFObjectFile<ELFT>::getArch() const {
return Triple::ppc;
case ELF::EM_PPC64:
return IsLittleEndian ? Triple::ppc64le : Triple::ppc64;
+ case ELF::EM_RISCV:
+ switch (EF.getHeader()->e_ident[ELF::EI_CLASS]) {
+ case ELF::ELFCLASS32:
+ return Triple::riscv32;
+ case ELF::ELFCLASS64:
+ return Triple::riscv64;
+ default:
+ report_fatal_error("Invalid ELFCLASS!");
+ }
case ELF::EM_S390:
return Triple::systemz;
diff --git a/include/llvm/module.modulemap b/include/llvm/module.modulemap
index de27c5f62bd..d8b07c4f54d 100644
--- a/include/llvm/module.modulemap
+++ b/include/llvm/module.modulemap
@@ -56,6 +56,7 @@ module LLVM_BinaryFormat {
textual header "BinaryFormat/ELFRelocs/Mips.def"
textual header "BinaryFormat/ELFRelocs/PowerPC64.def"
textual header "BinaryFormat/ELFRelocs/PowerPC.def"
+ textual header "BinaryFormat/ELFRelocs/RISCV.def"
textual header "BinaryFormat/ELFRelocs/Sparc.def"
textual header "BinaryFormat/ELFRelocs/SystemZ.def"
textual header "BinaryFormat/ELFRelocs/x86_64.def"
diff --git a/lib/Object/ELF.cpp b/lib/Object/ELF.cpp
index 2b9244c3c7c..92a64f48924 100644
--- a/lib/Object/ELF.cpp
+++ b/lib/Object/ELF.cpp
@@ -102,6 +102,13 @@ StringRef llvm::object::getELFRelocationTypeName(uint32_t Machine,
break;
}
break;
+ case ELF::EM_RISCV:
+ switch (Type) {
+#include "llvm/BinaryFormat/ELFRelocs/RISCV.def"
+ default:
+ break;
+ }
+ break;
case ELF::EM_S390:
switch (Type) {
#include "llvm/BinaryFormat/ELFRelocs/SystemZ.def"
diff --git a/lib/ObjectYAML/ELFYAML.cpp b/lib/ObjectYAML/ELFYAML.cpp
index 084eafc03c0..928b7b2b1c2 100644
--- a/lib/ObjectYAML/ELFYAML.cpp
+++ b/lib/ObjectYAML/ELFYAML.cpp
@@ -213,6 +213,7 @@ void ScalarEnumerationTraits<ELFYAML::ELF_EM>::enumeration(
ECase(EM_78KOR);
ECase(EM_56800EX);
ECase(EM_AMDGPU);
+ ECase(EM_RISCV);
ECase(EM_LANAI);
ECase(EM_BPF);
#undef ECase
@@ -359,6 +360,14 @@ void ScalarBitSetTraits<ELFYAML::ELF_EF>::bitset(IO &IO,
BCase(EF_AVR_ARCH_XMEGA6);
BCase(EF_AVR_ARCH_XMEGA7);
break;
+ case ELF::EM_RISCV:
+ BCase(EF_RISCV_RVC);
+ BCaseMask(EF_RISCV_FLOAT_ABI_SOFT, EF_RISCV_FLOAT_ABI);
+ BCaseMask(EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI);
+ BCaseMask(EF_RISCV_FLOAT_ABI_DOUBLE, EF_RISCV_FLOAT_ABI);
+ BCaseMask(EF_RISCV_FLOAT_ABI_QUAD, EF_RISCV_FLOAT_ABI);
+ BCase(EF_RISCV_RVE);
+ break;
case ELF::EM_AMDGPU:
BCaseMask(EF_AMDGPU_MACH_NONE, EF_AMDGPU_MACH);
BCaseMask(EF_AMDGPU_MACH_R600_R600, EF_AMDGPU_MACH);
@@ -616,6 +625,9 @@ void ScalarEnumerationTraits<ELFYAML::ELF_REL>::enumeration(
case ELF::EM_ARC:
#include "llvm/BinaryFormat/ELFRelocs/ARC.def"
break;
+ case ELF::EM_RISCV:
+#include "llvm/BinaryFormat/ELFRelocs/RISCV.def"
+ break;
case ELF::EM_LANAI:
#include "llvm/BinaryFormat/ELFRelocs/Lanai.def"
break;
diff --git a/test/Object/RISCV/elf-flags.yaml b/test/Object/RISCV/elf-flags.yaml
new file mode 100644
index 00000000000..ff8637f000a
--- /dev/null
+++ b/test/Object/RISCV/elf-flags.yaml
@@ -0,0 +1,24 @@
+# RUN: yaml2obj %s > %t
+# RUN: llvm-readobj -file-headers %t | FileCheck -check-prefix=OBJ %s
+# RUN: obj2yaml %t | FileCheck -check-prefix=YAML %s
+
+# OBJ: Flags [ (0xD)
+# OBJ-NEXT: EF_RISCV_FLOAT_ABI_DOUBLE (0x4)
+# OBJ-NEXT: EF_RISCV_RVC (0x1)
+# OBJ-NEXT: EF_RISCV_RVE (0x8)
+# OBJ-NEXT: ]
+
+# YAML: FileHeader:
+# YAML-NEXT: Class: ELFCLASS32
+# YAML-NEXT: Data: ELFDATA2LSB
+# YAML-NEXT: Type: ET_EXEC
+# YAML-NEXT: Machine: EM_RISCV
+# YAML-NEXT: Flags: [ EF_RISCV_RVC, EF_RISCV_FLOAT_ABI_DOUBLE, EF_RISCV_RVE ]
+
+--- !ELF
+FileHeader:
+ Class: ELFCLASS32
+ Data: ELFDATA2LSB
+ Type: ET_EXEC
+ Machine: EM_RISCV
+ Flags: [ EF_RISCV_RVC, EF_RISCV_FLOAT_ABI_DOUBLE, EF_RISCV_RVE ]
diff --git a/test/Object/RISCV/lit.local.cfg b/test/Object/RISCV/lit.local.cfg
new file mode 100644
index 00000000000..c63820126f8
--- /dev/null
+++ b/test/Object/RISCV/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'RISCV' in config.root.targets:
+ config.unsupported = True
diff --git a/tools/llvm-objdump/llvm-objdump.cpp b/tools/llvm-objdump/llvm-objdump.cpp
index 9f590ad8018..3be2c423bb5 100644
--- a/tools/llvm-objdump/llvm-objdump.cpp
+++ b/tools/llvm-objdump/llvm-objdump.cpp
@@ -756,6 +756,7 @@ static std::error_code getRelocationValueString(const ELFObjectFile<ELFT> *Obj,
case ELF::EM_HEXAGON:
case ELF::EM_MIPS:
case ELF::EM_BPF:
+ case ELF::EM_RISCV:
res = Target;
break;
case ELF::EM_WEBASSEMBLY:
diff --git a/tools/llvm-readobj/ELFDumper.cpp b/tools/llvm-readobj/ELFDumper.cpp
index ac8747a2f32..36cda459225 100644
--- a/tools/llvm-readobj/ELFDumper.cpp
+++ b/tools/llvm-readobj/ELFDumper.cpp
@@ -1011,6 +1011,7 @@ static const EnumEntry<unsigned> ElfMachineType[] = {
ENUM_ENT(EM_78KOR, "EM_78KOR"),
ENUM_ENT(EM_56800EX, "EM_56800EX"),
ENUM_ENT(EM_AMDGPU, "EM_AMDGPU"),
+ ENUM_ENT(EM_RISCV, "RISC-V"),
ENUM_ENT(EM_WEBASSEMBLY, "EM_WEBASSEMBLY"),
ENUM_ENT(EM_LANAI, "EM_LANAI"),
ENUM_ENT(EM_BPF, "EM_BPF"),
@@ -1292,6 +1293,14 @@ static const EnumEntry<unsigned> ElfHeaderAMDGPUFlags[] = {
LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_XNACK)
};
+static const EnumEntry<unsigned> ElfHeaderRISCVFlags[] = {
+ LLVM_READOBJ_ENUM_ENT(ELF, EF_RISCV_RVC),
+ LLVM_READOBJ_ENUM_ENT(ELF, EF_RISCV_FLOAT_ABI_SINGLE),
+ LLVM_READOBJ_ENUM_ENT(ELF, EF_RISCV_FLOAT_ABI_DOUBLE),
+ LLVM_READOBJ_ENUM_ENT(ELF, EF_RISCV_FLOAT_ABI_QUAD),
+ LLVM_READOBJ_ENUM_ENT(ELF, EF_RISCV_RVE)
+};
+
static const EnumEntry<unsigned> ElfSymOtherFlags[] = {
LLVM_READOBJ_ENUM_ENT(ELF, STV_INTERNAL),
LLVM_READOBJ_ENUM_ENT(ELF, STV_HIDDEN),
@@ -3747,6 +3756,8 @@ template <class ELFT> void LLVMStyle<ELFT>::printFileHeaders(const ELFO *Obj) {
else if (e->e_machine == EM_AMDGPU)
W.printFlags("Flags", e->e_flags, makeArrayRef(ElfHeaderAMDGPUFlags),
unsigned(ELF::EF_AMDGPU_MACH));
+ else if (e->e_machine == EM_RISCV)
+ W.printFlags("Flags", e->e_flags, makeArrayRef(ElfHeaderRISCVFlags));
else
W.printFlags("Flags", e->e_flags);
W.printNumber("HeaderSize", e->e_ehsize);
--
2.16.2