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0001-Revert-upstreamed-RISC-V-changes.patch
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0001-Revert-upstreamed-RISC-V-changes.patch
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <[email protected]>
Subject: Revert upstreamed RISC-V changes
This allows the patch series to be maintained and modified on an ongoing
basis.
---
docs/CompilerWriterInfo.rst | 4 -
include/llvm/ADT/Triple.h | 2 -
include/llvm/BinaryFormat/ELF.h | 17 -
include/llvm/BinaryFormat/ELFRelocs/RISCV.def | 59 -
include/llvm/Object/ELFObjectFile.h | 15 -
include/llvm/module.modulemap | 1 -
lib/Object/ELF.cpp | 7 -
lib/Object/ELFObjectFile.cpp | 13 -
lib/ObjectYAML/ELFYAML.cpp | 12 -
lib/Support/Triple.cpp | 21 -
lib/Target/LLVMBuild.txt | 1 -
lib/Target/RISCV/AsmParser/CMakeLists.txt | 3 -
lib/Target/RISCV/AsmParser/LLVMBuild.txt | 23 -
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 967 ----------------
lib/Target/RISCV/CMakeLists.txt | 31 -
lib/Target/RISCV/Disassembler/CMakeLists.txt | 3 -
lib/Target/RISCV/Disassembler/LLVMBuild.txt | 24 -
.../RISCV/Disassembler/RISCVDisassembler.cpp | 285 -----
lib/Target/RISCV/InstPrinter/CMakeLists.txt | 3 -
lib/Target/RISCV/InstPrinter/LLVMBuild.txt | 23 -
lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp | 90 --
lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h | 53 -
lib/Target/RISCV/LLVMBuild.txt | 35 -
lib/Target/RISCV/MCTargetDesc/CMakeLists.txt | 10 -
lib/Target/RISCV/MCTargetDesc/LLVMBuild.txt | 23 -
lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 326 ------
lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 110 --
.../RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp | 79 --
lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp | 39 -
lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h | 24 -
lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h | 58 -
lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp | 25 -
lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.h | 31 -
.../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 209 ----
lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp | 102 --
lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h | 76 --
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 92 --
lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h | 62 --
.../RISCV/MCTargetDesc/RISCVTargetStreamer.cpp | 18 -
.../RISCV/MCTargetDesc/RISCVTargetStreamer.h | 22 -
lib/Target/RISCV/RISCV.h | 37 -
lib/Target/RISCV/RISCV.td | 96 --
lib/Target/RISCV/RISCVAsmPrinter.cpp | 127 ---
lib/Target/RISCV/RISCVCallingConv.td | 20 -
lib/Target/RISCV/RISCVFrameLowering.cpp | 248 -----
lib/Target/RISCV/RISCVFrameLowering.h | 60 -
lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 124 ---
lib/Target/RISCV/RISCVISelLowering.cpp | 1080 ------------------
lib/Target/RISCV/RISCVISelLowering.h | 94 --
lib/Target/RISCV/RISCVInstrFormats.td | 285 -----
lib/Target/RISCV/RISCVInstrFormatsC.td | 147 ---
lib/Target/RISCV/RISCVInstrInfo.cpp | 368 ------
lib/Target/RISCV/RISCVInstrInfo.h | 79 --
lib/Target/RISCV/RISCVInstrInfo.td | 652 -----------
lib/Target/RISCV/RISCVInstrInfoA.td | 77 --
lib/Target/RISCV/RISCVInstrInfoC.td | 444 --------
lib/Target/RISCV/RISCVInstrInfoD.td | 174 ---
lib/Target/RISCV/RISCVInstrInfoF.td | 222 ----
lib/Target/RISCV/RISCVInstrInfoM.td | 51 -
lib/Target/RISCV/RISCVMCInstLower.cpp | 105 --
lib/Target/RISCV/RISCVMachineFunctionInfo.h | 44 -
lib/Target/RISCV/RISCVRegisterInfo.cpp | 110 --
lib/Target/RISCV/RISCVRegisterInfo.h | 57 -
lib/Target/RISCV/RISCVRegisterInfo.td | 206 ----
lib/Target/RISCV/RISCVSubtarget.cpp | 48 -
lib/Target/RISCV/RISCVSubtarget.h | 85 --
lib/Target/RISCV/RISCVTargetMachine.cpp | 92 --
lib/Target/RISCV/RISCVTargetMachine.h | 46 -
lib/Target/RISCV/TargetInfo/CMakeLists.txt | 3 -
lib/Target/RISCV/TargetInfo/LLVMBuild.txt | 23 -
lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp | 30 -
test/CodeGen/RISCV/addc-adde-sube-subc.ll | 30 -
test/CodeGen/RISCV/alloca.ll | 65 --
test/CodeGen/RISCV/alu32.ll | 186 ----
test/CodeGen/RISCV/analyze-branch.ll | 85 --
test/CodeGen/RISCV/bare-select.ll | 17 -
test/CodeGen/RISCV/blockaddress.ll | 30 -
test/CodeGen/RISCV/branch-relaxation.ll | 65 --
test/CodeGen/RISCV/branch.ll | 110 --
test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll | 569 ----------
test/CodeGen/RISCV/byval.ll | 51 -
test/CodeGen/RISCV/calling-conv-sext-zext.ll | 380 -------
test/CodeGen/RISCV/calling-conv.ll | 1132 -------------------
test/CodeGen/RISCV/calls.ll | 158 ---
test/CodeGen/RISCV/div.ll | 241 ----
test/CodeGen/RISCV/fp128.ll | 128 ---
test/CodeGen/RISCV/frame.ll | 58 -
test/CodeGen/RISCV/frameaddr-returnaddr.ll | 92 --
test/CodeGen/RISCV/get-setcc-result-type.ll | 35 -
test/CodeGen/RISCV/i32-icmp.ll | 114 --
test/CodeGen/RISCV/imm.ll | 47 -
test/CodeGen/RISCV/indirectbr.ll | 40 -
test/CodeGen/RISCV/inline-asm.ll | 55 -
test/CodeGen/RISCV/jumptable.ll | 58 -
test/CodeGen/RISCV/large-stack.ll | 172 ---
test/CodeGen/RISCV/lit.local.cfg | 2 -
test/CodeGen/RISCV/mem.ll | 202 ----
test/CodeGen/RISCV/mul.ll | 189 ----
test/CodeGen/RISCV/rem.ll | 45 -
test/CodeGen/RISCV/rotl-rotr.ll | 38 -
test/CodeGen/RISCV/select-cc.ll | 100 --
test/CodeGen/RISCV/sext-zext-trunc.ll | 285 -----
test/CodeGen/RISCV/shifts.ll | 51 -
test/CodeGen/RISCV/vararg.ll | 1171 --------------------
test/CodeGen/RISCV/wide-mem.ll | 34 -
test/MC/RISCV/cnop.s | 26 -
test/MC/RISCV/csr-aliases.s | 117 --
test/MC/RISCV/elf-flags.s | 13 -
test/MC/RISCV/elf-header.s | 42 -
test/MC/RISCV/fixups-compressed.s | 25 -
test/MC/RISCV/fixups-diagnostics.s | 18 -
test/MC/RISCV/fixups.s | 50 -
test/MC/RISCV/hilo-constaddr.s | 39 -
test/MC/RISCV/lit.local.cfg | 3 -
test/MC/RISCV/priv-invalid.s | 7 -
test/MC/RISCV/priv-valid.s | 34 -
test/MC/RISCV/relocations.s | 97 --
test/MC/RISCV/rv32-relaxation.s | 75 --
test/MC/RISCV/rv32a-invalid.s | 17 -
test/MC/RISCV/rv32a-valid.s | 148 ---
test/MC/RISCV/rv32c-invalid.s | 83 --
test/MC/RISCV/rv32c-only-valid.s | 15 -
test/MC/RISCV/rv32c-valid.s | 105 --
test/MC/RISCV/rv32d-invalid.s | 21 -
test/MC/RISCV/rv32d-valid.s | 161 ---
test/MC/RISCV/rv32dc-invalid.s | 12 -
test/MC/RISCV/rv32dc-valid.s | 29 -
test/MC/RISCV/rv32f-invalid.s | 34 -
test/MC/RISCV/rv32f-valid.s | 166 ---
test/MC/RISCV/rv32fc-invalid.s | 12 -
test/MC/RISCV/rv32fc-valid.s | 33 -
test/MC/RISCV/rv32i-aliases-invalid.s | 8 -
test/MC/RISCV/rv32i-aliases-valid.s | 20 -
test/MC/RISCV/rv32i-invalid.s | 148 ---
test/MC/RISCV/rv32i-valid.s | 240 ----
test/MC/RISCV/rv32m-invalid.s | 9 -
test/MC/RISCV/rv32m-valid.s | 35 -
test/MC/RISCV/rv64-relaxation.s | 64 --
test/MC/RISCV/rv64a-invalid.s | 14 -
test/MC/RISCV/rv64a-valid.s | 190 ----
test/MC/RISCV/rv64c-invalid.s | 29 -
test/MC/RISCV/rv64c-valid.s | 58 -
test/MC/RISCV/rv64d-aliases-valid.s | 27 -
test/MC/RISCV/rv64d-invalid.s | 11 -
test/MC/RISCV/rv64d-valid.s | 50 -
test/MC/RISCV/rv64dc-valid.s | 29 -
test/MC/RISCV/rv64f-aliases-valid.s | 27 -
test/MC/RISCV/rv64f-invalid.s | 9 -
test/MC/RISCV/rv64f-valid.s | 38 -
test/MC/RISCV/rv64i-aliases-invalid.s | 6 -
test/MC/RISCV/rv64i-aliases-valid.s | 20 -
test/MC/RISCV/rv64i-invalid.s | 20 -
test/MC/RISCV/rv64i-valid.s | 99 --
test/MC/RISCV/rv64m-valid.s | 21 -
test/MC/RISCV/rvd-aliases-valid.s | 78 --
test/MC/RISCV/rvf-aliases-valid.s | 125 ---
test/MC/RISCV/rvi-aliases-valid.s | 145 ---
test/Object/RISCV/elf-flags.yaml | 24 -
test/Object/RISCV/lit.local.cfg | 2 -
tools/llvm-objdump/llvm-objdump.cpp | 1 -
tools/llvm-readobj/ELFDumper.cpp | 11 -
unittests/ADT/TripleTest.cpp | 36 -
utils/UpdateTestChecks/asm.py | 18 -
163 files changed, 17261 deletions(-)
delete mode 100644 include/llvm/BinaryFormat/ELFRelocs/RISCV.def
delete mode 100644 lib/Target/RISCV/AsmParser/CMakeLists.txt
delete mode 100644 lib/Target/RISCV/AsmParser/LLVMBuild.txt
delete mode 100644 lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
delete mode 100644 lib/Target/RISCV/CMakeLists.txt
delete mode 100644 lib/Target/RISCV/Disassembler/CMakeLists.txt
delete mode 100644 lib/Target/RISCV/Disassembler/LLVMBuild.txt
delete mode 100644 lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
delete mode 100644 lib/Target/RISCV/InstPrinter/CMakeLists.txt
delete mode 100644 lib/Target/RISCV/InstPrinter/LLVMBuild.txt
delete mode 100644 lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
delete mode 100644 lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h
delete mode 100644 lib/Target/RISCV/LLVMBuild.txt
delete mode 100644 lib/Target/RISCV/MCTargetDesc/CMakeLists.txt
delete mode 100644 lib/Target/RISCV/MCTargetDesc/LLVMBuild.txt
delete mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
delete mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
delete mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
delete mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
delete mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
delete mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
delete mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
delete mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.h
delete mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
delete mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
delete mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h
delete mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
delete mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
delete mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
delete mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
delete mode 100644 lib/Target/RISCV/RISCV.h
delete mode 100644 lib/Target/RISCV/RISCV.td
delete mode 100644 lib/Target/RISCV/RISCVAsmPrinter.cpp
delete mode 100644 lib/Target/RISCV/RISCVCallingConv.td
delete mode 100644 lib/Target/RISCV/RISCVFrameLowering.cpp
delete mode 100644 lib/Target/RISCV/RISCVFrameLowering.h
delete mode 100644 lib/Target/RISCV/RISCVISelDAGToDAG.cpp
delete mode 100644 lib/Target/RISCV/RISCVISelLowering.cpp
delete mode 100644 lib/Target/RISCV/RISCVISelLowering.h
delete mode 100644 lib/Target/RISCV/RISCVInstrFormats.td
delete mode 100644 lib/Target/RISCV/RISCVInstrFormatsC.td
delete mode 100644 lib/Target/RISCV/RISCVInstrInfo.cpp
delete mode 100644 lib/Target/RISCV/RISCVInstrInfo.h
delete mode 100644 lib/Target/RISCV/RISCVInstrInfo.td
delete mode 100644 lib/Target/RISCV/RISCVInstrInfoA.td
delete mode 100644 lib/Target/RISCV/RISCVInstrInfoC.td
delete mode 100644 lib/Target/RISCV/RISCVInstrInfoD.td
delete mode 100644 lib/Target/RISCV/RISCVInstrInfoF.td
delete mode 100644 lib/Target/RISCV/RISCVInstrInfoM.td
delete mode 100644 lib/Target/RISCV/RISCVMCInstLower.cpp
delete mode 100644 lib/Target/RISCV/RISCVMachineFunctionInfo.h
delete mode 100644 lib/Target/RISCV/RISCVRegisterInfo.cpp
delete mode 100644 lib/Target/RISCV/RISCVRegisterInfo.h
delete mode 100644 lib/Target/RISCV/RISCVRegisterInfo.td
delete mode 100644 lib/Target/RISCV/RISCVSubtarget.cpp
delete mode 100644 lib/Target/RISCV/RISCVSubtarget.h
delete mode 100644 lib/Target/RISCV/RISCVTargetMachine.cpp
delete mode 100644 lib/Target/RISCV/RISCVTargetMachine.h
delete mode 100644 lib/Target/RISCV/TargetInfo/CMakeLists.txt
delete mode 100644 lib/Target/RISCV/TargetInfo/LLVMBuild.txt
delete mode 100644 lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
delete mode 100644 test/CodeGen/RISCV/addc-adde-sube-subc.ll
delete mode 100644 test/CodeGen/RISCV/alloca.ll
delete mode 100644 test/CodeGen/RISCV/alu32.ll
delete mode 100644 test/CodeGen/RISCV/analyze-branch.ll
delete mode 100644 test/CodeGen/RISCV/bare-select.ll
delete mode 100644 test/CodeGen/RISCV/blockaddress.ll
delete mode 100644 test/CodeGen/RISCV/branch-relaxation.ll
delete mode 100644 test/CodeGen/RISCV/branch.ll
delete mode 100644 test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
delete mode 100644 test/CodeGen/RISCV/byval.ll
delete mode 100644 test/CodeGen/RISCV/calling-conv-sext-zext.ll
delete mode 100644 test/CodeGen/RISCV/calling-conv.ll
delete mode 100644 test/CodeGen/RISCV/calls.ll
delete mode 100644 test/CodeGen/RISCV/div.ll
delete mode 100644 test/CodeGen/RISCV/fp128.ll
delete mode 100644 test/CodeGen/RISCV/frame.ll
delete mode 100644 test/CodeGen/RISCV/frameaddr-returnaddr.ll
delete mode 100644 test/CodeGen/RISCV/get-setcc-result-type.ll
delete mode 100644 test/CodeGen/RISCV/i32-icmp.ll
delete mode 100644 test/CodeGen/RISCV/imm.ll
delete mode 100644 test/CodeGen/RISCV/indirectbr.ll
delete mode 100644 test/CodeGen/RISCV/inline-asm.ll
delete mode 100644 test/CodeGen/RISCV/jumptable.ll
delete mode 100644 test/CodeGen/RISCV/large-stack.ll
delete mode 100644 test/CodeGen/RISCV/lit.local.cfg
delete mode 100644 test/CodeGen/RISCV/mem.ll
delete mode 100644 test/CodeGen/RISCV/mul.ll
delete mode 100644 test/CodeGen/RISCV/rem.ll
delete mode 100644 test/CodeGen/RISCV/rotl-rotr.ll
delete mode 100644 test/CodeGen/RISCV/select-cc.ll
delete mode 100644 test/CodeGen/RISCV/sext-zext-trunc.ll
delete mode 100644 test/CodeGen/RISCV/shifts.ll
delete mode 100644 test/CodeGen/RISCV/vararg.ll
delete mode 100644 test/CodeGen/RISCV/wide-mem.ll
delete mode 100644 test/MC/RISCV/cnop.s
delete mode 100644 test/MC/RISCV/csr-aliases.s
delete mode 100644 test/MC/RISCV/elf-flags.s
delete mode 100644 test/MC/RISCV/elf-header.s
delete mode 100644 test/MC/RISCV/fixups-compressed.s
delete mode 100644 test/MC/RISCV/fixups-diagnostics.s
delete mode 100644 test/MC/RISCV/fixups.s
delete mode 100644 test/MC/RISCV/hilo-constaddr.s
delete mode 100644 test/MC/RISCV/lit.local.cfg
delete mode 100644 test/MC/RISCV/priv-invalid.s
delete mode 100644 test/MC/RISCV/priv-valid.s
delete mode 100644 test/MC/RISCV/relocations.s
delete mode 100644 test/MC/RISCV/rv32-relaxation.s
delete mode 100644 test/MC/RISCV/rv32a-invalid.s
delete mode 100644 test/MC/RISCV/rv32a-valid.s
delete mode 100644 test/MC/RISCV/rv32c-invalid.s
delete mode 100644 test/MC/RISCV/rv32c-only-valid.s
delete mode 100644 test/MC/RISCV/rv32c-valid.s
delete mode 100644 test/MC/RISCV/rv32d-invalid.s
delete mode 100644 test/MC/RISCV/rv32d-valid.s
delete mode 100644 test/MC/RISCV/rv32dc-invalid.s
delete mode 100644 test/MC/RISCV/rv32dc-valid.s
delete mode 100644 test/MC/RISCV/rv32f-invalid.s
delete mode 100644 test/MC/RISCV/rv32f-valid.s
delete mode 100644 test/MC/RISCV/rv32fc-invalid.s
delete mode 100644 test/MC/RISCV/rv32fc-valid.s
delete mode 100644 test/MC/RISCV/rv32i-aliases-invalid.s
delete mode 100644 test/MC/RISCV/rv32i-aliases-valid.s
delete mode 100644 test/MC/RISCV/rv32i-invalid.s
delete mode 100644 test/MC/RISCV/rv32i-valid.s
delete mode 100644 test/MC/RISCV/rv32m-invalid.s
delete mode 100644 test/MC/RISCV/rv32m-valid.s
delete mode 100644 test/MC/RISCV/rv64-relaxation.s
delete mode 100644 test/MC/RISCV/rv64a-invalid.s
delete mode 100644 test/MC/RISCV/rv64a-valid.s
delete mode 100644 test/MC/RISCV/rv64c-invalid.s
delete mode 100644 test/MC/RISCV/rv64c-valid.s
delete mode 100644 test/MC/RISCV/rv64d-aliases-valid.s
delete mode 100644 test/MC/RISCV/rv64d-invalid.s
delete mode 100644 test/MC/RISCV/rv64d-valid.s
delete mode 100644 test/MC/RISCV/rv64dc-valid.s
delete mode 100644 test/MC/RISCV/rv64f-aliases-valid.s
delete mode 100644 test/MC/RISCV/rv64f-invalid.s
delete mode 100644 test/MC/RISCV/rv64f-valid.s
delete mode 100644 test/MC/RISCV/rv64i-aliases-invalid.s
delete mode 100644 test/MC/RISCV/rv64i-aliases-valid.s
delete mode 100644 test/MC/RISCV/rv64i-invalid.s
delete mode 100644 test/MC/RISCV/rv64i-valid.s
delete mode 100644 test/MC/RISCV/rv64m-valid.s
delete mode 100644 test/MC/RISCV/rvd-aliases-valid.s
delete mode 100644 test/MC/RISCV/rvf-aliases-valid.s
delete mode 100644 test/MC/RISCV/rvi-aliases-valid.s
delete mode 100644 test/Object/RISCV/elf-flags.yaml
delete mode 100644 test/Object/RISCV/lit.local.cfg
diff --git a/docs/CompilerWriterInfo.rst b/docs/CompilerWriterInfo.rst
index 60f102472c6..4e5d8dc2026 100644
--- a/docs/CompilerWriterInfo.rst
+++ b/docs/CompilerWriterInfo.rst
@@ -74,10 +74,6 @@ AMDGPU
Refer to :doc:`AMDGPUUsage` for additional documentation.
-RISC-V
-------
-* `RISC-V User-Level ISA Specification <https://riscv.org/specifications/>`_
-
SPARC
-----
diff --git a/include/llvm/ADT/Triple.h b/include/llvm/ADT/Triple.h
index 00fa9c08299..965bd246b83 100644
--- a/include/llvm/ADT/Triple.h
+++ b/include/llvm/ADT/Triple.h
@@ -66,8 +66,6 @@ public:
ppc64le, // PPC64LE: powerpc64le
r600, // R600: AMD GPUs HD2XXX - HD6XXX
amdgcn, // AMDGCN: AMD GCN GPUs
- riscv32, // RISC-V (32-bit): riscv32
- riscv64, // RISC-V (64-bit): riscv64
sparc, // Sparc: sparc
sparcv9, // Sparcv9: Sparcv9
sparcel, // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
diff --git a/include/llvm/BinaryFormat/ELF.h b/include/llvm/BinaryFormat/ELF.h
index a2321e72c98..38090afb0c3 100644
--- a/include/llvm/BinaryFormat/ELF.h
+++ b/include/llvm/BinaryFormat/ELF.h
@@ -309,7 +309,6 @@ enum {
EM_NORC = 218, // Nanoradio Optimized RISC
EM_CSR_KALIMBA = 219, // CSR Kalimba architecture family
EM_AMDGPU = 224, // AMD GPU architecture
- EM_RISCV = 243, // RISC-V
EM_LANAI = 244, // Lanai 32-bit processor
EM_BPF = 247, // Linux kernel bpf virtual machine
@@ -618,22 +617,6 @@ enum {
#include "ELFRelocs/Lanai.def"
};
-// RISCV Specific e_flags
-enum : unsigned {
- EF_RISCV_RVC = 0x0001,
- EF_RISCV_FLOAT_ABI = 0x0006,
- EF_RISCV_FLOAT_ABI_SOFT = 0x0000,
- EF_RISCV_FLOAT_ABI_SINGLE = 0x0002,
- EF_RISCV_FLOAT_ABI_DOUBLE = 0x0004,
- EF_RISCV_FLOAT_ABI_QUAD = 0x0006,
- EF_RISCV_RVE = 0x0008
-};
-
-// ELF Relocation types for RISC-V
-enum {
-#include "ELFRelocs/RISCV.def"
-};
-
// ELF Relocation types for S390/zSeries
enum {
#include "ELFRelocs/SystemZ.def"
diff --git a/include/llvm/BinaryFormat/ELFRelocs/RISCV.def b/include/llvm/BinaryFormat/ELFRelocs/RISCV.def
deleted file mode 100644
index 5cc4c0ec302..00000000000
--- a/include/llvm/BinaryFormat/ELFRelocs/RISCV.def
+++ /dev/null
@@ -1,59 +0,0 @@
-
-#ifndef ELF_RELOC
-#error "ELF_RELOC must be defined"
-#endif
-
-ELF_RELOC(R_RISCV_NONE, 0)
-ELF_RELOC(R_RISCV_32, 1)
-ELF_RELOC(R_RISCV_64, 2)
-ELF_RELOC(R_RISCV_RELATIVE, 3)
-ELF_RELOC(R_RISCV_COPY, 4)
-ELF_RELOC(R_RISCV_JUMP_SLOT, 5)
-ELF_RELOC(R_RISCV_TLS_DTPMOD32, 6)
-ELF_RELOC(R_RISCV_TLS_DTPMOD64, 7)
-ELF_RELOC(R_RISCV_TLS_DTPREL32, 8)
-ELF_RELOC(R_RISCV_TLS_DTPREL64, 9)
-ELF_RELOC(R_RISCV_TLS_TPREL32, 10)
-ELF_RELOC(R_RISCV_TLS_TPREL64, 11)
-ELF_RELOC(R_RISCV_BRANCH, 16)
-ELF_RELOC(R_RISCV_JAL, 17)
-ELF_RELOC(R_RISCV_CALL, 18)
-ELF_RELOC(R_RISCV_CALL_PLT, 19)
-ELF_RELOC(R_RISCV_GOT_HI20, 20)
-ELF_RELOC(R_RISCV_TLS_GOT_HI20, 21)
-ELF_RELOC(R_RISCV_TLS_GD_HI20, 22)
-ELF_RELOC(R_RISCV_PCREL_HI20, 23)
-ELF_RELOC(R_RISCV_PCREL_LO12_I, 24)
-ELF_RELOC(R_RISCV_PCREL_LO12_S, 25)
-ELF_RELOC(R_RISCV_HI20, 26)
-ELF_RELOC(R_RISCV_LO12_I, 27)
-ELF_RELOC(R_RISCV_LO12_S, 28)
-ELF_RELOC(R_RISCV_TPREL_HI20, 29)
-ELF_RELOC(R_RISCV_TPREL_LO12_I, 30)
-ELF_RELOC(R_RISCV_TPREL_LO12_S, 31)
-ELF_RELOC(R_RISCV_TPREL_ADD, 32)
-ELF_RELOC(R_RISCV_ADD8, 33)
-ELF_RELOC(R_RISCV_ADD16, 34)
-ELF_RELOC(R_RISCV_ADD32, 35)
-ELF_RELOC(R_RISCV_ADD64, 36)
-ELF_RELOC(R_RISCV_SUB8, 37)
-ELF_RELOC(R_RISCV_SUB16, 38)
-ELF_RELOC(R_RISCV_SUB32, 39)
-ELF_RELOC(R_RISCV_SUB64, 40)
-ELF_RELOC(R_RISCV_GNU_VTINHERIT, 41)
-ELF_RELOC(R_RISCV_GNU_VTENTRY, 42)
-ELF_RELOC(R_RISCV_ALIGN, 43)
-ELF_RELOC(R_RISCV_RVC_BRANCH, 44)
-ELF_RELOC(R_RISCV_RVC_JUMP, 45)
-ELF_RELOC(R_RISCV_RVC_LUI, 46)
-ELF_RELOC(R_RISCV_GPREL_I, 47)
-ELF_RELOC(R_RISCV_GPREL_S, 48)
-ELF_RELOC(R_RISCV_TPREL_I, 49)
-ELF_RELOC(R_RISCV_TPREL_S, 50)
-ELF_RELOC(R_RISCV_RELAX, 51)
-ELF_RELOC(R_RISCV_SUB6, 52)
-ELF_RELOC(R_RISCV_SET6, 53)
-ELF_RELOC(R_RISCV_SET8, 54)
-ELF_RELOC(R_RISCV_SET16, 55)
-ELF_RELOC(R_RISCV_SET32, 56)
-ELF_RELOC(R_RISCV_32_PCREL, 57)
diff --git a/include/llvm/Object/ELFObjectFile.h b/include/llvm/Object/ELFObjectFile.h
index 4d001039238..5eda163acfc 100644
--- a/include/llvm/Object/ELFObjectFile.h
+++ b/include/llvm/Object/ELFObjectFile.h
@@ -80,8 +80,6 @@ public:
SubtargetFeatures getARMFeatures() const;
- SubtargetFeatures getRISCVFeatures() const;
-
void setARMSubArch(Triple &TheTriple) const override;
};
@@ -983,8 +981,6 @@ StringRef ELFObjectFile<ELFT>::getFileFormatName() const {
return "ELF32-mips";
case ELF::EM_PPC:
return "ELF32-ppc";
- case ELF::EM_RISCV:
- return "ELF32-riscv";
case ELF::EM_SPARC:
case ELF::EM_SPARC32PLUS:
return "ELF32-sparc";
@@ -1005,8 +1001,6 @@ StringRef ELFObjectFile<ELFT>::getFileFormatName() const {
return (IsLittleEndian ? "ELF64-aarch64-little" : "ELF64-aarch64-big");
case ELF::EM_PPC64:
return "ELF64-ppc64";
- case ELF::EM_RISCV:
- return "ELF64-riscv";
case ELF::EM_S390:
return "ELF64-s390";
case ELF::EM_SPARCV9:
@@ -1059,15 +1053,6 @@ template <class ELFT> Triple::ArchType ELFObjectFile<ELFT>::getArch() const {
return Triple::ppc;
case ELF::EM_PPC64:
return IsLittleEndian ? Triple::ppc64le : Triple::ppc64;
- case ELF::EM_RISCV:
- switch (EF.getHeader()->e_ident[ELF::EI_CLASS]) {
- case ELF::ELFCLASS32:
- return Triple::riscv32;
- case ELF::ELFCLASS64:
- return Triple::riscv64;
- default:
- report_fatal_error("Invalid ELFCLASS!");
- }
case ELF::EM_S390:
return Triple::systemz;
diff --git a/include/llvm/module.modulemap b/include/llvm/module.modulemap
index d8b07c4f54d..de27c5f62bd 100644
--- a/include/llvm/module.modulemap
+++ b/include/llvm/module.modulemap
@@ -56,7 +56,6 @@ module LLVM_BinaryFormat {
textual header "BinaryFormat/ELFRelocs/Mips.def"
textual header "BinaryFormat/ELFRelocs/PowerPC64.def"
textual header "BinaryFormat/ELFRelocs/PowerPC.def"
- textual header "BinaryFormat/ELFRelocs/RISCV.def"
textual header "BinaryFormat/ELFRelocs/Sparc.def"
textual header "BinaryFormat/ELFRelocs/SystemZ.def"
textual header "BinaryFormat/ELFRelocs/x86_64.def"
diff --git a/lib/Object/ELF.cpp b/lib/Object/ELF.cpp
index 92a64f48924..2b9244c3c7c 100644
--- a/lib/Object/ELF.cpp
+++ b/lib/Object/ELF.cpp
@@ -102,13 +102,6 @@ StringRef llvm::object::getELFRelocationTypeName(uint32_t Machine,
break;
}
break;
- case ELF::EM_RISCV:
- switch (Type) {
-#include "llvm/BinaryFormat/ELFRelocs/RISCV.def"
- default:
- break;
- }
- break;
case ELF::EM_S390:
switch (Type) {
#include "llvm/BinaryFormat/ELFRelocs/SystemZ.def"
diff --git a/lib/Object/ELFObjectFile.cpp b/lib/Object/ELFObjectFile.cpp
index e806c8f28b1..3c1bdf5a1de 100644
--- a/lib/Object/ELFObjectFile.cpp
+++ b/lib/Object/ELFObjectFile.cpp
@@ -238,25 +238,12 @@ SubtargetFeatures ELFObjectFileBase::getARMFeatures() const {
return Features;
}
-SubtargetFeatures ELFObjectFileBase::getRISCVFeatures() const {
- SubtargetFeatures Features;
- unsigned PlatformFlags = getPlatformFlags();
-
- if (PlatformFlags & ELF::EF_RISCV_RVC) {
- Features.AddFeature("c");
- }
-
- return Features;
-}
-
SubtargetFeatures ELFObjectFileBase::getFeatures() const {
switch (getEMachine()) {
case ELF::EM_MIPS:
return getMIPSFeatures();
case ELF::EM_ARM:
return getARMFeatures();
- case ELF::EM_RISCV:
- return getRISCVFeatures();
default:
return SubtargetFeatures();
}
diff --git a/lib/ObjectYAML/ELFYAML.cpp b/lib/ObjectYAML/ELFYAML.cpp
index 928b7b2b1c2..084eafc03c0 100644
--- a/lib/ObjectYAML/ELFYAML.cpp
+++ b/lib/ObjectYAML/ELFYAML.cpp
@@ -213,7 +213,6 @@ void ScalarEnumerationTraits<ELFYAML::ELF_EM>::enumeration(
ECase(EM_78KOR);
ECase(EM_56800EX);
ECase(EM_AMDGPU);
- ECase(EM_RISCV);
ECase(EM_LANAI);
ECase(EM_BPF);
#undef ECase
@@ -360,14 +359,6 @@ void ScalarBitSetTraits<ELFYAML::ELF_EF>::bitset(IO &IO,
BCase(EF_AVR_ARCH_XMEGA6);
BCase(EF_AVR_ARCH_XMEGA7);
break;
- case ELF::EM_RISCV:
- BCase(EF_RISCV_RVC);
- BCaseMask(EF_RISCV_FLOAT_ABI_SOFT, EF_RISCV_FLOAT_ABI);
- BCaseMask(EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI);
- BCaseMask(EF_RISCV_FLOAT_ABI_DOUBLE, EF_RISCV_FLOAT_ABI);
- BCaseMask(EF_RISCV_FLOAT_ABI_QUAD, EF_RISCV_FLOAT_ABI);
- BCase(EF_RISCV_RVE);
- break;
case ELF::EM_AMDGPU:
BCaseMask(EF_AMDGPU_MACH_NONE, EF_AMDGPU_MACH);
BCaseMask(EF_AMDGPU_MACH_R600_R600, EF_AMDGPU_MACH);
@@ -625,9 +616,6 @@ void ScalarEnumerationTraits<ELFYAML::ELF_REL>::enumeration(
case ELF::EM_ARC:
#include "llvm/BinaryFormat/ELFRelocs/ARC.def"
break;
- case ELF::EM_RISCV:
-#include "llvm/BinaryFormat/ELFRelocs/RISCV.def"
- break;
case ELF::EM_LANAI:
#include "llvm/BinaryFormat/ELFRelocs/Lanai.def"
break;
diff --git a/lib/Support/Triple.cpp b/lib/Support/Triple.cpp
index 5062fc43266..9b1a739c911 100644
--- a/lib/Support/Triple.cpp
+++ b/lib/Support/Triple.cpp
@@ -41,8 +41,6 @@ StringRef Triple::getArchTypeName(ArchType Kind) {
case ppc: return "powerpc";
case r600: return "r600";
case amdgcn: return "amdgcn";
- case riscv32: return "riscv32";
- case riscv64: return "riscv64";
case sparc: return "sparc";
case sparcv9: return "sparcv9";
case sparcel: return "sparcel";
@@ -143,9 +141,6 @@ StringRef Triple::getArchTypePrefix(ArchType Kind) {
case shave: return "shave";
case wasm32:
case wasm64: return "wasm";
-
- case riscv32:
- case riscv64: return "riscv";
}
}
@@ -278,8 +273,6 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
.Case("ppc64le", ppc64le)
.Case("r600", r600)
.Case("amdgcn", amdgcn)
- .Case("riscv32", riscv32)
- .Case("riscv64", riscv64)
.Case("hexagon", hexagon)
.Case("sparc", sparc)
.Case("sparcel", sparcel)
@@ -405,8 +398,6 @@ static Triple::ArchType parseArch(StringRef ArchName) {
.Case("nios2", Triple::nios2)
.Case("r600", Triple::r600)
.Case("amdgcn", Triple::amdgcn)
- .Case("riscv32", Triple::riscv32)
- .Case("riscv64", Triple::riscv64)
.Case("hexagon", Triple::hexagon)
.Cases("s390x", "systemz", Triple::systemz)
.Case("sparc", Triple::sparc)
@@ -656,8 +647,6 @@ static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
case Triple::r600:
case Triple::renderscript32:
case Triple::renderscript64:
- case Triple::riscv32:
- case Triple::riscv64:
case Triple::shave:
case Triple::sparc:
case Triple::sparcel:
@@ -1196,7 +1185,6 @@ static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
case llvm::Triple::nvptx:
case llvm::Triple::ppc:
case llvm::Triple::r600:
- case llvm::Triple::riscv32:
case llvm::Triple::sparc:
case llvm::Triple::sparcel:
case llvm::Triple::tce:
@@ -1226,7 +1214,6 @@ static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
case llvm::Triple::nvptx64:
case llvm::Triple::ppc64:
case llvm::Triple::ppc64le:
- case llvm::Triple::riscv64:
case llvm::Triple::sparcv9:
case llvm::Triple::systemz:
case llvm::Triple::x86_64:
@@ -1281,7 +1268,6 @@ Triple Triple::get32BitArchVariant() const {
case Triple::nvptx:
case Triple::ppc:
case Triple::r600:
- case Triple::riscv32:
case Triple::sparc:
case Triple::sparcel:
case Triple::tce:
@@ -1305,7 +1291,6 @@ Triple Triple::get32BitArchVariant() const {
case Triple::nvptx64: T.setArch(Triple::nvptx); break;
case Triple::ppc64: T.setArch(Triple::ppc); break;
case Triple::sparcv9: T.setArch(Triple::sparc); break;
- case Triple::riscv64: T.setArch(Triple::riscv32); break;
case Triple::x86_64: T.setArch(Triple::x86); break;
case Triple::amdil64: T.setArch(Triple::amdil); break;
case Triple::hsail64: T.setArch(Triple::hsail); break;
@@ -1350,7 +1335,6 @@ Triple Triple::get64BitArchVariant() const {
case Triple::nvptx64:
case Triple::ppc64:
case Triple::ppc64le:
- case Triple::riscv64:
case Triple::sparcv9:
case Triple::systemz:
case Triple::x86_64:
@@ -1367,7 +1351,6 @@ Triple Triple::get64BitArchVariant() const {
case Triple::nvptx: T.setArch(Triple::nvptx64); break;
case Triple::ppc: T.setArch(Triple::ppc64); break;
case Triple::sparc: T.setArch(Triple::sparcv9); break;
- case Triple::riscv32: T.setArch(Triple::riscv64); break;
case Triple::x86: T.setArch(Triple::x86_64); break;
case Triple::amdil: T.setArch(Triple::amdil64); break;
case Triple::hsail: T.setArch(Triple::hsail64); break;
@@ -1402,8 +1385,6 @@ Triple Triple::getBigEndianArchVariant() const {
case Triple::nvptx64:
case Triple::nvptx:
case Triple::r600:
- case Triple::riscv32:
- case Triple::riscv64:
case Triple::shave:
case Triple::spir64:
case Triple::spir:
@@ -1490,8 +1471,6 @@ bool Triple::isLittleEndian() const {
case Triple::nvptx:
case Triple::ppc64le:
case Triple::r600:
- case Triple::riscv32:
- case Triple::riscv64:
case Triple::shave:
case Triple::sparcel:
case Triple::spir64:
diff --git a/lib/Target/LLVMBuild.txt b/lib/Target/LLVMBuild.txt
index 0d899a9c782..87d5ce11751 100644
--- a/lib/Target/LLVMBuild.txt
+++ b/lib/Target/LLVMBuild.txt
@@ -32,7 +32,6 @@ subdirectories =
Mips
Nios2
PowerPC
- RISCV
Sparc
SystemZ
WebAssembly
diff --git a/lib/Target/RISCV/AsmParser/CMakeLists.txt b/lib/Target/RISCV/AsmParser/CMakeLists.txt
deleted file mode 100644
index 10d0c89537c..00000000000
--- a/lib/Target/RISCV/AsmParser/CMakeLists.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-add_llvm_library(LLVMRISCVAsmParser
- RISCVAsmParser.cpp
- )
diff --git a/lib/Target/RISCV/AsmParser/LLVMBuild.txt b/lib/Target/RISCV/AsmParser/LLVMBuild.txt
deleted file mode 100644
index a9ad92c872e..00000000000
--- a/lib/Target/RISCV/AsmParser/LLVMBuild.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-;===- ./lib/Target/RISCV/AsmParser/LLVMBuild.txt ---------------*- Conf -*--===;
-;
-; The LLVM Compiler Infrastructure
-;
-; This file is distributed under the University of Illinois Open Source
-; License. See LICENSE.TXT for details.
-;
-;===------------------------------------------------------------------------===;
-;
-; This is an LLVMBuild description file for the components in this subdirectory.
-;
-; For more information on the LLVMBuild system, please see:
-;
-; http://llvm.org/docs/LLVMBuild.html
-;
-;===------------------------------------------------------------------------===;
-
-[component_0]
-type = Library
-name = RISCVAsmParser
-parent = RISCV
-required_libraries = MC MCParser RISCVDesc RISCVInfo Support
-add_to_library_groups = RISCV
diff --git a/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
deleted file mode 100644
index 035c1ef6ac7..00000000000
--- a/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ /dev/null
@@ -1,967 +0,0 @@
-//===-- RISCVAsmParser.cpp - Parse RISCV assembly to MCInst instructions --===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "MCTargetDesc/RISCVBaseInfo.h"
-#include "MCTargetDesc/RISCVMCExpr.h"
-#include "MCTargetDesc/RISCVMCTargetDesc.h"
-#include "llvm/ADT/STLExtras.h"
-#include "llvm/ADT/StringSwitch.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCParser/MCAsmLexer.h"
-#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
-#include "llvm/MC/MCParser/MCTargetAsmParser.h"
-#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/MC/MCStreamer.h"
-#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/Support/Casting.h"
-#include "llvm/Support/TargetRegistry.h"
-
-using namespace llvm;
-
-namespace {
-struct RISCVOperand;
-
-class RISCVAsmParser : public MCTargetAsmParser {
- SMLoc getLoc() const { return getParser().getTok().getLoc(); }
- bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); }
-
- unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
- unsigned Kind) override;
-
- bool generateImmOutOfRangeError(OperandVector &Operands, uint64_t ErrorInfo,
- int Lower, int Upper, Twine Msg);
-
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
- OperandVector &Operands, MCStreamer &Out,
- uint64_t &ErrorInfo,
- bool MatchingInlineAsm) override;
-
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
-
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
- SMLoc NameLoc, OperandVector &Operands) override;
-
- bool ParseDirective(AsmToken DirectiveID) override;
-
-// Auto-generated instruction matching functions
-#define GET_ASSEMBLER_HEADER
-#include "RISCVGenAsmMatcher.inc"
-
- OperandMatchResultTy parseImmediate(OperandVector &Operands);
- OperandMatchResultTy parseRegister(OperandVector &Operands,
- bool AllowParens = false);
- OperandMatchResultTy parseMemOpBaseReg(OperandVector &Operands);
- OperandMatchResultTy parseOperandWithModifier(OperandVector &Operands);
-
- bool parseOperand(OperandVector &Operands);
-
-public:
- enum RISCVMatchResultTy {
- Match_Dummy = FIRST_TARGET_MATCH_RESULT_TY,
-#define GET_OPERAND_DIAGNOSTIC_TYPES
-#include "RISCVGenAsmMatcher.inc"
-#undef GET_OPERAND_DIAGNOSTIC_TYPES
- };
-
- static bool classifySymbolRef(const MCExpr *Expr,
- RISCVMCExpr::VariantKind &Kind,
- int64_t &Addend);
-
- RISCVAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
- const MCInstrInfo &MII, const MCTargetOptions &Options)
- : MCTargetAsmParser(Options, STI, MII) {
- setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
- }
-};
-
-/// RISCVOperand - Instances of this class represent a parsed machine
-/// instruction
-struct RISCVOperand : public MCParsedAsmOperand {
-
- enum KindTy {
- Token,
- Register,
- Immediate,
- } Kind;
-
- bool IsRV64;
-
- struct RegOp {
- unsigned RegNum;
- };
-
- struct ImmOp {
- const MCExpr *Val;
- };
-
- SMLoc StartLoc, EndLoc;
- union {
- StringRef Tok;
- RegOp Reg;
- ImmOp Imm;
- };
-
- RISCVOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
-
-public:
- RISCVOperand(const RISCVOperand &o) : MCParsedAsmOperand() {
- Kind = o.Kind;
- IsRV64 = o.IsRV64;
- StartLoc = o.StartLoc;
- EndLoc = o.EndLoc;
- switch (Kind) {
- case Register:
- Reg = o.Reg;
- break;
- case Immediate:
- Imm = o.Imm;
- break;
- case Token:
- Tok = o.Tok;
- break;
- }
- }
-
- bool isToken() const override { return Kind == Token; }
- bool isReg() const override { return Kind == Register; }
- bool isImm() const override { return Kind == Immediate; }
- bool isMem() const override { return false; }
-
- bool evaluateConstantImm(int64_t &Imm, RISCVMCExpr::VariantKind &VK) const {
- const MCExpr *Val = getImm();
- bool Ret = false;
- if (auto *RE = dyn_cast<RISCVMCExpr>(Val)) {
- Ret = RE->evaluateAsConstant(Imm);
- VK = RE->getKind();
- } else if (auto CE = dyn_cast<MCConstantExpr>(Val)) {
- Ret = true;
- VK = RISCVMCExpr::VK_RISCV_None;
- Imm = CE->getValue();
- }
- return Ret;
- }
-
- // True if operand is a symbol with no modifiers, or a constant with no
- // modifiers and isShiftedInt<N-1, 1>(Op).
- template <int N> bool isBareSimmNLsb0() const {
- int64_t Imm;
- RISCVMCExpr::VariantKind VK;
- if (!isImm())
- return false;
- bool IsConstantImm = evaluateConstantImm(Imm, VK);
- bool IsValid;
- if (!IsConstantImm)
- IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm);
- else
- IsValid = isShiftedInt<N - 1, 1>(Imm);
- return IsValid && VK == RISCVMCExpr::VK_RISCV_None;
- }
-
- // Predicate methods for AsmOperands defined in RISCVInstrInfo.td
-
- /// Return true if the operand is a valid for the fence instruction e.g.
- /// ('iorw').
- bool isFenceArg() const {
- if (!isImm())
- return false;
- const MCExpr *Val = getImm();
- auto *SVal = dyn_cast<MCSymbolRefExpr>(Val);
- if (!SVal || SVal->getKind() != MCSymbolRefExpr::VK_None)
- return false;
-
- StringRef Str = SVal->getSymbol().getName();
- // Letters must be unique, taken from 'iorw', and in ascending order. This
- // holds as long as each individual character is one of 'iorw' and is
- // greater than the previous character.
- char Prev = '\0';
- for (char c : Str) {
- if (c != 'i' && c != 'o' && c != 'r' && c != 'w')
- return false;
- if (c <= Prev)
- return false;
- Prev = c;
- }
- return true;
- }
-
- /// Return true if the operand is a valid floating point rounding mode.
- bool isFRMArg() const {
- if (!isImm())
- return false;
- const MCExpr *Val = getImm();
- auto *SVal = dyn_cast<MCSymbolRefExpr>(Val);
- if (!SVal || SVal->getKind() != MCSymbolRefExpr::VK_None)
- return false;
-
- StringRef Str = SVal->getSymbol().getName();
-
- return RISCVFPRndMode::stringToRoundingMode(Str) != RISCVFPRndMode::Invalid;
- }
-
- bool isUImmLog2XLen() const {
- int64_t Imm;
- RISCVMCExpr::VariantKind VK;
- if (!isImm())
- return false;
- if (!evaluateConstantImm(Imm, VK) || VK != RISCVMCExpr::VK_RISCV_None)
- return false;
- return (isRV64() && isUInt<6>(Imm)) || isUInt<5>(Imm);
- }
-
- bool isUImmLog2XLenNonZero() const {
- int64_t Imm;
- RISCVMCExpr::VariantKind VK;
- if (!isImm())
- return false;
- if (!evaluateConstantImm(Imm, VK) || VK != RISCVMCExpr::VK_RISCV_None)
- return false;
- if (Imm == 0)
- return false;
- return (isRV64() && isUInt<6>(Imm)) || isUInt<5>(Imm);
- }
-
- bool isUImm5() const {
- int64_t Imm;
- RISCVMCExpr::VariantKind VK;
- if (!isImm())
- return false;