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PCB layout and cap value are flawed #1

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Bort-Plate opened this issue Feb 23, 2016 · 0 comments

Bort-Plate commented Feb 23, 2016

The PCB traces and cap values do not match the datasheet for the Grideye.

The Data sheet has Pin 10 (AVDD-PC) going to a 1uF cap, then a 20Ω resistor, then ground. And Pin 12 goes to a 1.5uF cap then ground.

But, the "proto1" PCB from this git has pins 10 and 12 swapped, with pin 12 getting the resistor, AND the cap value is wrong (0.1uF instead of 1uF)!

This also means that the PCB layout that currently exists on oshpark.com is also wrong!

Bort-Plate changed the title ~~PCB is flawed~~ PCB layout and cap value is flawed

Bort-Plate changed the title ~~PCB layout and cap value is flawed~~ PCB layout and cap value are flawed

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