From 06a104f6ed827b90943ede4bf5600ef93fa71f8b Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Tue, 18 Jul 2023 10:28:36 -0300 Subject: [PATCH] rtmlamp_ohwr refactoring [WIP] --- .../rtmlamp_ohwr/cnv_ldac_pulse_gen.vhd | 40 +++++++++++++++++++ hdl/modules/rtmlamp_ohwr/rtmlamp_ohwr.vhd | 18 ++++----- 2 files changed, 49 insertions(+), 9 deletions(-) create mode 100644 hdl/modules/rtmlamp_ohwr/cnv_ldac_pulse_gen.vhd diff --git a/hdl/modules/rtmlamp_ohwr/cnv_ldac_pulse_gen.vhd b/hdl/modules/rtmlamp_ohwr/cnv_ldac_pulse_gen.vhd new file mode 100644 index 0000000..85b493e --- /dev/null +++ b/hdl/modules/rtmlamp_ohwr/cnv_ldac_pulse_gen.vhd @@ -0,0 +1,40 @@ +------------------------------------------------------------------------------- +-- Title : CNV and LDAC pulse generator +------------------------------------------------------------------------------- +-- Author : Augusto Fraga Giachero +-- Company : CNPEM LNLS-GIE +-- Platform : FPGA-generic +-- Standard : VHDL 2008 +------------------------------------------------------------------------------- +-- Description: Generate synchronized out of phase CNV and LDAC pulses +------------------------------------------------------------------------------- +-- Copyright (c) 2023 CNPEM +-- Licensed under GNU Lesser General Public License (LGPL) v3.0 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2023-07-17 1.0 augusto.fraga Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity cnv_ldac_pulse_gen is + generic ( + g_ldac_width : natural range 1 to 256; + g_ldac_polarity : string := "ACTIVE_HIGH"; + g_cnv_width : natural range 1 to 256; + g_cnv_polarity : string := "ACTIVE_HIGH" + ); + port ( + clk_i : std_logic; + rst_n : std_logic; + cnv_o : std_logic; + ldac_o : std_logic + ); +end entity; + +architecture rtl of cnv_ldac_pulse_gen is +begin +end architecture; diff --git a/hdl/modules/rtmlamp_ohwr/rtmlamp_ohwr.vhd b/hdl/modules/rtmlamp_ohwr/rtmlamp_ohwr.vhd index 429fa4c..78814f0 100644 --- a/hdl/modules/rtmlamp_ohwr/rtmlamp_ohwr.vhd +++ b/hdl/modules/rtmlamp_ohwr/rtmlamp_ohwr.vhd @@ -60,17 +60,17 @@ port ( --------------------------------------------------------------------------- -- clock and reset interface --------------------------------------------------------------------------- - clk_i : in std_logic; - rst_n_i : in std_logic; + clk_sys_i : in std_logic; + rst_sys_n_i : in std_logic; - clk_ref_i : in std_logic := '0'; - rst_ref_n_i : in std_logic := '1'; + clk_ref_i : in std_logic; + rst_ref_n_i : in std_logic; - rst_fast_spi_n_i : in std_logic; clk_fast_spi_i : in std_logic; + rst_fast_spi_n_i : in std_logic; --------------------------------------------------------------------------- - -- RTM ADC interface + -- RTM ADC interface (clock domain: clk_fast_spi_i) --------------------------------------------------------------------------- adc_octo_cnv_o : out std_logic; adc_octo_sck_p_o : out std_logic; @@ -98,7 +98,7 @@ port ( adc_quad_sdoc_n_i : in std_logic := '1'; --------------------------------------------------------------------------- - -- RTM DAC interface + -- RTM DAC interface (clock domain: clk_ref_i) --------------------------------------------------------------------------- dac_cs_n_o : out std_logic; dac_ldac_n_o : out std_logic; @@ -106,7 +106,7 @@ port ( dac_sdi_o : out std_logic_vector(g_CHANNELS-1 downto 0); --------------------------------------------------------------------------- - -- RTM Serial registers interface + -- RTM Serial registers interface (clock domain: clk_sys_i) --------------------------------------------------------------------------- amp_shift_clk_o : out std_logic; amp_shift_dout_i : in std_logic := '0'; @@ -117,7 +117,7 @@ port ( amp_shift_str_o : out std_logic; --------------------------------------------------------------------------- - -- Channel control + -- Channel control (clock domain: clk_ref_i) --------------------------------------------------------------------------- ch_ctrl_i : in t_rtmlamp_ch_ctrl_in_array(g_CHANNELS-1 downto 0); ch_ctrl_o : out t_rtmlamp_ch_ctrl_out_array(g_CHANNELS-1 downto 0);